TWI438891B - Memory devices - Google Patents

Description

Memory component

The present invention relates to a memory unit, and more particularly to a dynamic random access memory (DRAM) unit.

The demand for high-capacity, high-speed, and low-power memory components continues to grow. There are typically two types of memory components, namely static random access memory (SRAM) components and dynamic random access memory components. Although SRAM can operate at very high speeds, it can occupy a large area on a large-scale integration (LSI) because it is a six-cell (6T) cell structure. Moreover, it is difficult to reduce the area of the SRAM cell due to the matching problem between the cell transistors. A DRAM cell composed of a transistor and a capacitor (1T/1C) can have a relatively small cell size and a relatively high operating speed. However, conventional 1T/1C DRAM cells may face a problem that new materials for stacked capacitors, such as high dielectric constant films, may be required due to the reduced feature size of the components, or may be required for storage with vertical shapes. Take the high aspect ratio trench of the channel-type capacitor combined with the transistor. To overcome this problem, a variety of methods have been used. One of the methods is to use stacked tunneling The gain cell of the crystal. Another method is magnetic random access. However, the former may require a new component structure, while the latter introduces new materials into the metal-oxide-semiconductor (MOS) process, which means it takes a long time to import both. Production of scale memory.

In view of this situation, another memory called a capacitor-less 1T DRAM or a floating-body cell (FBC) is provided. This new memory cell uses a partially depleted (PD) silicon-on-insulator (SOI) metal-oxide-semiconductor (MOSFET). The floating body acts as a storage node. Therefore, 1T DRAM cells can eliminate the need for complex storage capacitors, which means that 1T DRAM cells can have good process compatibility with logic components.

1A and 1B show schematic diagrams of a prior art 1T DRAM cell 10 in different states. The 1T DRAM cell 10 includes a source region 11, a drain region 12, a gate region 13, a cell body 15, and a buried oxide (Box) layer 14, wherein the source region 11, the drain region 12, and the cell body 15 Both contain 矽. 1A shows a 1T DRAM cell 10 in a logic "1" state, and FIG. 1B shows a 1T DRAM cell 10 in a logic "0" state. According to the prior art, for 1T DRAM cells 10. The logic "1" state can be written by way of gate induced drain leakage (GIDL) or impact free (II). The logic "0" state can be accomplished by forward biasing of the PN junction, which exists in source-body bonding and drain-body bonding. Therefore, when the threshold voltage (Vth) is changed, the 1T DRAM cell 10 can sense whether or not most carriers (holes) are accumulated in the floating body. Set the source to 0 volts, connect the drain to the bit line, and connect the gate to the word line. When excess holes are present in the floating body and Vth is lowered, the cell state can be regarded as "1". On the other hand, when the excess hole is cleared out of the floating body by the forward bias on the body-drain junction and the Vth rises, the cell state can be regarded as "0". The difference in the drain current of the "1" and "0" states can be sensed in the linear current region to avoid changing the number of holes formed by the II current. By performing a read operation within the linear current region, the 1T DRAM cell can perform a non-destructive read operation during the update interval.

The 1T DRAM cell does not require complex storage capacitors, which saves unit size. However, it is necessary to provide good memory data storage and/or sufficient write speed for 1T DRAM cells.

Most embodiments may include a memory element. In one embodiment, the memory component includes: a source region and a drain region of a first dopant type, The source region and the drain region comprise a first semiconductor material; the second dopant type body region, the body region being between the source region and the drain region, the body region comprising the second semiconductor material; above the at least the body region a gate dielectric layer; and a gate comprising a conductive material over the gate dielectric layer. In particular, one of the first semiconductor material and the second semiconductor material is lattice matched to the other of the first semiconductor material and the second semiconductor material and has one of the other than the first semiconductor material and the second semiconductor material The energy gap is small.

One embodiment includes a method of operating a memory device, the memory device having a body region disposed between a source region and a drain region; a gate dielectric layer over the body region; and a gate dielectric layer The gate above. In one embodiment, a method of operating a memory device can include applying a gate voltage and a first gate voltage to write a first state indicating signal into a memory device; and applying a second gate voltage and adding a positive A bias is applied to the body-drain junction or body-source junction to write a second status indication signal into the memory element.

Now, reference will be made in detail to the examples of the invention shown in the drawings. Wherever possible, the same reference numerals,,,, Although the reference has been made to a specific exemplary embodiment to the present invention The embodiment of the invention has been described in detail, and it is apparent that various modifications and changes can be made to the embodiments without departing from the spirit and scope of the invention. Therefore, the specification and drawings are to be regarded as illustrative rather

2A through 2F are schematic cross-sectional views showing the fabrication of a transistor (1T) p-type metal oxide semiconductor (PMOS) cell in accordance with one example of the present invention. Referring to FIG. 2A, an insulating layer may be formed on a substrate (not shown), such as a buried oxide layer 21, and an n-type germanium layer 22, a gate oxide layer 23, and a heavily doped p may be sequentially provided thereon. Type (p+) polysilicon layer 24. An oxide layer 25 and a tantalum nitride (SiN) layer 26, which may serve as a hard mask layer, may be provided over the p+ polysilicon layer 24. In various embodiments, other similar materials may be provided in place of the tantalum nitride used in the tantalum nitride layer 26.

Referring to FIG. 2B, a patterned photoresist (PR) layer 27 may be formed on the SiN layer 26 for patterning the p+ polysilicon layer 24. Referring to FIG. 2C, a patterned SiN layer 26' and a patterned oxide layer 25' may be formed by an etching process or other suitable process using the patterned PR layer 27 as a mask. The patterned PR layer 27 can then be removed. Next, a patterned p+ polysilicon layer 24' can be formed by etching the p+ polysilicon layer 24 using the patterned SiN layer 26' and the patterned oxide layer 25' as a mask. Sidewall spacers 28 may be formed along both sides of the patterned p+ polysilicon layer 24'. In one example, sidewall spacers 28 may include an oxide liner, while in another example, an oxide liner and along may be included The nitride spacer of the oxide liner. Next, referring to FIG. 2D, a patterned gate oxide layer 23' and a patterned n-type germanium layer 22' may be formed by a trench etching process or other suitable process.

Referring to FIG. 2E, the semiconductor layer 29 may be deposited or epitaxially grown and then planarized. The semiconductor layer 29 may comprise a semiconductor material whose lattice can be lattice matched to the germanium and whose energy gap can be smaller than the energy gap of the germanium. In one example, the semiconductor layer 29 can comprise germanium (SiGe) or crystalline SiGe. Referring to FIG. 2F, the semiconductor layer 29 can be etched back and a p+ implant process can be performed to form a pair of p+ diffusion regions 29' that serve as the source and drain regions of the PMOS cell. The patterned SiN layer 26' and the patterned oxide layer 25' can then be removed.

The use of semiconductor SiGe in the germanium and drain/source regions of the cell of the PMOS cell of the present invention is source/drain compared to conventional PMOS cells including germanium and drain/source regions. A smaller energy gap is provided between the conductive strip (Ec) and the valence band (Ev) in the region. Therefore, since the energy gap in the p+ drain region is smaller, under the same bias conditions, the band-to-band tunneling mechanism is generated by the p+ region generated from the gate to the drain ( That is, when BTBT) (or gate induced drain leakage current (GIDL)) is written to logic "1", it can inject electrons into the cell of the current PMOS cell more efficiently than in the prior art. Moreover, since the conductive strip edge (Ec) in the body region shown in FIG. 4A is lower, electrons stored in the cell body of the current PMOS cell can pass through the source/drain region and the unit body. The heterogeneous junction is well constrained. It prevents electrons from leaking into the source and drain regions. Therefore, the reliability of data storage can be improved by this or similar structure.

In other exemplary embodiments, the material in the drain region and the source region of the PMOS cell (such as SiGe or crystalline SiGe) may be replaced by other semiconductor materials, the lattice of which matches the lattice of germanium, and the energy gap ratio. The energy gap of the crucible is small, and the edge of the conductive strip is higher than the edge of the conductive strip of the crucible.

FIG. 3 is a schematic cross-sectional view showing a 1T n-type metal oxide semiconductor (NMOS) unit 30 according to an example of the present invention. Referring to FIG. 3, the NMOS cell 30 may include a buried oxide layer 31 on a substrate (not shown), a p-type SiGe layer 32 serving as a unit body of the NMOS cell 30 over the buried oxide layer 31, and used as an NMOS. The heavily doped n-type (n+) germanium region 39 of the source region and the drain region of the cell 30, the gate oxide layer 33 over the p-SiGe layer 32, and the n+ polysilicon layer used as the gate of the NMOS cell 30 34. The NMOS cell 30 can be fabricated in a manner similar to that in Figures 2A through 2F and will therefore not be discussed here.

The use of germanium in the drain/source region of the NMOS cell 30 and SiGe in the cell body can have the following advantages. When the impact caused by the channel current is freely written to logic "1", the depletion region constituting the strong electric field may exist in the body near the drain region. Since the energy gap in the body region is small, electron-hole pairs can be generated more efficiently by impact free. Electrons flow into the bungee and the hole It stays in the unit body 32 of the NMOS unit 30. Moreover, since the edge of the valence band in the body region shown in FIG. 4B is higher, the hole stored in the unit body 32 of the NMOS unit 30 in the logic "1" state can be the drain/source region of the NMOS unit 30. A heterojunction constraint between 39 and unit body 32. Therefore, leakage of holes into the source region and the drain region can be prevented. The reliability of data preservation is also improved.

As indicated above, the method of fabricating a memory device may thus include: providing a substrate 21; forming a first semiconductor material and a body region 22 of a first dopant type on the substrate 21; forming a source region and a drain of the second semiconductor material a region 29', wherein the source region and the drain region 29' are of a second dopant type, and the body region 22 is interposed between the source region and the drain region 29'; forming a gate dielectric over the body region 22. The electric layer 23; and a gate 24 is formed over the gate dielectric layer 23. In some examples, the first semiconductor material can include germanium, and the second semiconductor material can be lattice matched to the germanium and can have a smaller energy gap than germanium. In one example, the second semiconductor material can include germanium. Alternatively, it may be reversed that the second semiconductor material may comprise germanium, and the first semiconductor material may be lattice matched to the germanium and may have a smaller energy gap than the energy gap of germanium. In one example, the first semiconductor material can include germanium. In some examples, the substrate can include a buried oxide layer, such as a semiconductor substrate having a buried oxide layer formed thereon.

Therefore, as shown in FIG. 2F or FIG. 3, the memory element may include: first a dopant type source region and a drain region 29', and including or using a first semiconductor material; a second dopant type body region 22 interposed between the source region and the drain region 29', and A second semiconductor material is included or used; a gate dielectric layer 23 over at least the body region 22; and a gate 24 comprising a conductive material over the gate dielectric layer 23. In particular, one of the first semiconductor material and the second semiconductor material is lattice matched to the other of the first semiconductor material and the second semiconductor material and has one of the other than the first semiconductor material and the second semiconductor material The energy gap is small. In some examples, a conductive strip edge of a material having a smaller energy gap may be higher than a conductive strip edge of a material having a larger energy gap. In some examples, a valence band edge of a material having a smaller energy gap may be higher than a valence band edge of a material having a larger energy gap. In some examples, a conductive strip edge of a material having a smaller energy gap may be higher than a conductive strip edge of a material having a larger energy gap, and a valence band edge of a material having a smaller energy gap may have a larger energy The valence of the material of the gap is high. In some examples, the material having a smaller energy gap may be p-type doped.

In one example, the first semiconductor material can be Si and the second semiconductor material can be germanium. Additionally, the first semiconductor material can be germanium and the second semiconductor material can be germanium. The first semiconductor material and the second semiconductor material can be in various combinations. In some examples, a semiconductor material having a smaller energy gap may have a P-type dopant and a semiconductor material having a larger energy gap. The material may have an N-type dopant. In some examples, a conductive strip edge of a semiconductor material having a larger energy gap may be lower than a conductive strip edge of a semiconductor material having a smaller energy gap. In other examples, the valence band edge of a semiconductor material having a larger energy gap may be lower than the valence band edge of a semiconductor material having a smaller energy gap.

The first dopant type may be one of a P type and an N type, and the second dopant type may be one of a P type and an N type. In some examples, the P-type doped region is composed of SiGe. The memory element can include a buried oxide layer 21 under the drain and source regions 29, and below the body region 22. In one example, gate dielectric or gate oxide (GOX) layer 23 may comprise silicon oxide (SiO _x).

Different methods of operation may be used depending on the material of the source region and the drain region 29' and the body region 22 when operating the memory device. In general, the memory device can have the structure shown above, such as having a body region 22 disposed between the source region and the drain region 29', a gate dielectric layer 23 over the body region 22, and a gate. Gate 24 above the dielectric layer 23. In one example, the method of operation can include applying a gate voltage and a first gate voltage to write a first state indicating signal into the memory device; and applying a second gate voltage and applying a forward bias to the body-汲A pole bond or body-source bond, the second state indicating signal is written into the memory component. In particular, a gate voltage and a first gate voltage are applied to write a first state indicating signal at the NMOS device The case may cause the channel current induced impact to free to inject holes into the body region or, in the case of a PMOS device, to cause band-to-band tunneling to inject electrons into the body region. In some examples, the first state indication signal stored in the body region is constrained by a heterojunction of the body-drain junction and the body-source junction. The method of operation can be applied to PMOS and NMOS memory elements having source/drain regions and body regions, respectively, using or including doped SiGe, such as P-SiGe source/drain in PMOS or P in NMOS -SiGe body.

In describing a representative example of the invention, the specification shows the method and/or process of the invention in a particular sequence of steps. However, when a method or process does not rely on a particular order of the steps set forth herein, the method or process should not be limited to the specific order of the steps described. It will be understood by those skilled in the art that other sequential steps may be employed. Therefore, the specific sequence of steps set forth in this specification should not be construed as limiting the scope of the claims. In addition, the scope of the application of the method and/or the process of the present invention should not be limited to the order of the described steps, and it will be readily understood by those skilled in the art without departing from the spirit and scope of the invention. Underneath, you can change the order.

10‧‧‧1T DRAM unit

11‧‧‧ source area

12‧‧‧Bungee area

13‧‧‧ gate area

14‧‧‧ buried oxide layer

15‧‧‧unit

21‧‧‧ buried oxide layer

22‧‧‧n type layer

22'‧‧‧n type layer

23‧‧‧ gate oxide layer

23'‧‧‧ gate oxide layer

24‧‧‧p+ polysilicon layer

24'‧‧‧p+ polycrystalline layer

25‧‧‧Oxide layer

25'‧‧‧Oxide layer

26‧‧‧矽 nitride layer

26'‧‧‧ nitride layer

27‧‧‧Photoresist layer

28‧‧‧ sidewall spacer

29‧‧‧Semiconductor layer

29'‧‧‧Source and bungee regions

30‧‧‧ NMOS unit

31‧‧‧ buried oxide layer

32‧‧‧p-type SiGe layer

33‧‧‧ gate oxide layer

34‧‧‧n+ polysilicon layer

39‧‧‧n type (n+)矽 area

1A and 1B are diagrams showing prior art in different states Schematic of a 1T DRAM cell.

2A through 2F are schematic cross-sectional views showing a method of fabricating a 1T PMOS cell in accordance with one embodiment of the present invention.

3 is a schematic cross-sectional view showing a 1T NMOS cell in accordance with an embodiment of the present invention.

4A is a diagram showing a diagram of a PMOS cell in accordance with an embodiment of the present invention showing the difference in edge band gap between the body and the source/drain regions of the data retention.

4B is a diagram showing a diagram of a NMOS cell in accordance with an embodiment of the present invention showing the edge band gap energy gap between the body and the source/drain regions that enhances data conservation.

30‧‧‧ NMOS unit

31‧‧‧ buried oxide layer

32‧‧‧p-type SiGe layer

33‧‧‧ gate oxide layer

34‧‧‧n+ polysilicon layer

39‧‧‧n type (n+)矽 area

Claims (21)

A memory element comprising: a source region and a drain region of a first dopant type, the source region and the drain region comprising a first semiconductor material; a body region of a second dopant type, the body a region between the source region and the drain region, the body region including a second semiconductor material; a gate dielectric layer over at least the body region; and a dielectric at the gate a gate above the layer, the gate comprising a conductive material, wherein one of the first semiconductor material and the second semiconductor material is between the first semiconductor material and the second semiconductor material Another lattice is matched and has a smaller energy gap than the energy gap of the other of the first semiconductor material and the second semiconductor material. The memory component of claim 1, wherein the first semiconductor material comprises one of tantalum and niobium, and the second semiconductor material comprises one of tantalum and niobium. The memory component of claim 2, wherein the first dopant type is one of a P type and an N type, and the second dopant type is a P type and an N type. One. The memory component of claim 1, wherein Semiconductor materials having a smaller energy gap include P-type dopants, and semiconductor materials having larger energy gaps include N-type dopants. The memory device of claim 1, wherein the conductive material edge of the semiconductor material having a larger energy gap is lower than the conductive tape edge of the semiconductor material having a smaller energy gap. The memory device of claim 1, wherein the valence band edge of the semiconductor material having a larger energy gap is lower than the valence band edge of the semiconductor material having a smaller energy gap. The memory device of claim 1, further comprising a buried oxide layer under the drain region, the source region, and the body region. The memory device of claim 1, wherein the gate dielectric layer comprises hafnium oxide. A method of operating a memory device having a body region disposed between a source region and a drain region, a gate dielectric layer over the body region, and a dielectric at the gate a gate over the layer, wherein the source region and the drain region comprise a first semiconductor material, and the body region comprises a second semiconductor material, the method of operating the memory device comprising: applying a gate voltage And a first gate voltage to write a first state indicating signal into the memory component; Applying a second gate voltage and applying a forward bias to the body-drain junction or body-source junction to write a second state indicating signal into the memory device, wherein the first semiconductor material and One of the second semiconductor materials is lattice matched to the other of the first semiconductor material and the second semiconductor material, and has a ratio of the first semiconductor material and the second semiconductor material The other has a small energy gap. The method of operating a memory device according to claim 9, wherein applying the gate voltage and the first gate voltage comprises generating a channel current induced impact free to inject a hole into the NMOS device. Within the body region. The method of operating a memory device of claim 9, wherein applying the drain voltage and the first gate voltage comprises generating a band-to-band tunneling to inject electrons into the PMOS device Within the body area. A method of operating a memory device as recited in claim 9, comprising: said first storage stored in said body region by said body-drain joint and said body-source bonded heterojunction constraint Status indication signal. The method of operating a memory device according to claim 9, wherein the memory component comprises a PMOS memory component and One of the NMOS memory elements, wherein the N-type doped region comprises Si and the P-type doped region comprises SiGe. The method of operating a memory device of claim 9, comprising erasing the second state indicating signal by applying a forward bias to the body-drain junction or the body-source bond. The method of operating a memory device of claim 9, wherein applying a forward bias to the body-drain bond comprises implanting electrons into the body region of the NMOS device. The method of operating a memory device of claim 9, wherein applying a forward bias to the body-drain junction results in a hole injection into the body region of the PMOS device. A method of fabricating a memory device, comprising: providing a substrate; forming a body region of a first semiconductor material on the substrate, the body region being a first dopant type; forming a source region and a drain of the second semiconductor material a region, the source region and the drain region being a second dopant type, the body region being interposed between the source region and the drain region; forming a gate over the body region a dielectric layer; and forming a gate over the gate dielectric layer, wherein the first semiconductor material and the second semiconductor material One of the lattices matching the other of the first semiconductor material and the second semiconductor material and having a smaller energy gap than the other of the first semiconductor material and the second semiconductor material Energy gap. The method of manufacturing a memory device according to claim 17, wherein the first semiconductor material comprises germanium, and the second semiconductor material is lattice-matched with germanium and has a smaller energy gap than germanium. . The method of manufacturing a memory device according to claim 17, wherein the second semiconductor material comprises germanium, and the first semiconductor material is lattice-matched with germanium and has a smaller energy gap than germanium. . The method of manufacturing a memory device according to claim 17, wherein one of the first semiconductor material and the second semiconductor material comprises germanium. The method of manufacturing a memory device according to claim 17, wherein the substrate comprises a buried oxide layer.