TWI430583B - Digital/analog converter with current compensation - Google Patents

Description

Digital analog converter with current compensation

The present invention relates to a digital analog converter, and more particularly to a digital analog converter with current compensation function.

The digital analog converter is a conversion device that converts one or more sets of digital signals into analog signals. The analog output signal of the digital analog converter is highly susceptible to external environment, process drift and circuit design to generate signal offset. This phenomenon will greatly affect the linearity of the analog output signal. Therefore, the differential digital analog converter disclosed in U.S. Patent No. 7,242,338 B2 is used to improve this phenomenon. Please refer to FIG. 4, the differential digital position. The analog converter 20 has a first signal input buffer 21, a second signal input buffer 22, a plurality of bit switches 23, at least one thermometer code switch 24, a plurality of R-2R resistor structures 25, and a first The output terminal 26 and the second output terminal 27, wherein the bit switch 23 and the thermometer code switch 24 are electrically connected to the first signal input buffer 21 and the second signal input buffer 22, each of the R- The 2R resistor structure 25 is electrically connected to each of the bit switch 23 and the thermometer code switch 24, and the first output end 26 and the second output end 27 are electrically connected to the R-2R resistor structures 25, the differential Digital analogy The converter 20 determines whether the first signal input buffer 21 and the second signal input buffer 22 respectively input a first reference signal and a second reference signal by using the bit switches 23 to compensate for the first The terminal voltage of the output terminal 26 and the second output terminal 27, however, the R-2R resistor structures 25 are easily affected by the process drift, so that the resistance value varies between R and 2R, and each of the R-2R resistor structures A mismatch between 25 will greatly reduce the linearity of the differential digital analog converter 20.

A digital analog converter with current compensation, comprising a signal transmission group, a digital analog conversion circuit, a current compensation circuit and a voltage output terminal, the signal transmission group having a first control signal end and a second control a signal control terminal, a third control signal terminal, a fourth control signal terminal and a fifth control signal terminal, wherein the digital analog conversion circuit has a first inverter group, a first transistor group and a resistor. The first inverter group is electrically connected to the signal transmitting group, the first transistor group is electrically connected to the first inverter group, and the resistor is electrically connected to the first transistor group, the current compensation circuit The device has a gate group, a second inverter group and a second transistor group, and the gate group is electrically connected to the first control signal end of the signal sending group, the second control signal end, and the a third control signal terminal, the fourth control signal terminal and the fifth control signal terminal, the second inverter group is electrically connected to the gate group, and the second transistor group is electrically connected to the second electrode Phase set, the first transistor set, the second set And a peer group based electrically connected to the resistive voltage output terminal. The present invention performs a current compensation operation on the digital analog conversion circuit by using the current compensation circuit, and uses the first control signal terminal, the second control signal terminal, the third control signal terminal, and the fourth control signal terminal. The fifth control signal end serves as a current compensation input end of the current compensation circuit, and the electrical connection between the control signal terminal and the gate group of the current compensation circuit can effectively improve the current of the digital analog conversion circuit. Linearity and the high precision of this digital analog converter.

Referring to FIG. 1 , FIG. 2 and FIG. 3 , which is a preferred embodiment of the present invention, a current-compensated digital analog converter 10 includes a a signal transmission group 11, a digital analog conversion circuit 12, a current compensation circuit 13, and a voltage output terminal 14, the signal transmission group 11 has a first control signal terminal 111, a second control signal terminal 112, and a third The control signal terminal 113, a fourth control signal terminal 114 and a fifth control signal terminal 115, the digital analog conversion circuit 12 has a first inverter group 121, a first transistor group 122 and a resistor 123. The first inverter group 121 is electrically connected to the signal transmitting group 11. The first transistor group 122 is electrically connected to the first inverter group 121. The resistor 123 is electrically connected to the first transistor. The current compensation circuit 13 has a gate group 131, a second inverter group 132 and a second transistor group 133. The gate group 131 is electrically connected to the first control signal terminal 111. The second control signal terminal 112, the third control signal terminal 113, the fourth control signal terminal 114 and the fifth control signal terminal 115 are electrically connected to the gate group 131. The second transistor group 133 is electrically connected to the second inverter group 132, and the first transistor group 122 The second transistor group 133 and the resistor 123 are electrically connected to the voltage output terminal 14. In this embodiment, the first transistor group 122 and the second transistor group 133 are composed of a plurality of gold oxide half fields. It is composed of a metal-oxide-semiconductor field-effect transistor (MOSFET).

Referring to FIG. 2 again, in the embodiment, the signal sending group 11 further has a sixth control signal end 116, a seventh control signal end 117, and an eighth control signal end 118. The phase detector group 121 is electrically connected to the sixth control signal terminal 116, the seventh control signal terminal 117 and the eighth control signal terminal 118, and each of the transmitting terminals can provide a digital control signal. The first inverter group 121 has a first inverter 1211 electrically connected to the first control signal end 111, and a second inverter 1212 electrically connected to the second control signal end 112. The third inverter 1213 electrically connected to the third control signal end 113, the fourth inverter 1214 electrically connected to the fourth control signal end 114, and the fifth electrically connected to the fifth control signal end 115 a fifth inverter 1215, a sixth inverter 1216 electrically connected to the sixth control signal end 116, a seventh inverter 1217 electrically connected to the seventh control signal end 117, and an electrical connection The eighth inverter 1218 of the control signal terminal 118, please refer to FIG. 2 again. The first transistor group 122 of the digital analog conversion circuit 12 has a first transistor 122a and a second transistor 122b. a third transistor 122c, a fourth transistor 122d, a fifth transistor 122e, a sixth transistor 122f, a seventh transistor 122g, an eighth transistor 122h, a ninth transistor 122i, and a The tenth transistor 122j, each of the inverters is electrically connected to each of the transistors, and preferably, the first transistor 122a is electrically Connecting the ninth transistor 122i, the second transistor 122b is electrically connected to the tenth transistor 122j, the third transistor 122c, the fourth transistor 122d, the fifth transistor 122e, the sixth transistor 122f, The seventh transistor 122g, the eighth transistor 122h, the ninth transistor 122i, and the tenth transistor transistor 122j are electrically connected to the resistor 123 and the voltage output terminal 14. In this embodiment, the ninth transistor The 122i and the tenth transistor 122j are used to increase the output impedance to reduce the current fluctuation caused by the first control signal end 111 and the second control signal end 112 when the signal is switched, thereby reducing noise interference. The 汲 extreme of the ninth transistor 122i is the Most Significant Bit (MSB) end, and the 汲 extreme of the eighth transistor 122h is the least significant bit (Least Significant) The first transistor group 122 has an eleventh transistor 122k electrically connected to the first transistor 122a, and is electrically connected to the second transistor. Referring to FIG. 2, the first transistor group 122 further has an eleventh transistor 122k electrically connected to the first transistor 122a. a twelfth transistor 122l of 122b, a thirteenth transistor 122m electrically connected to the third transistor 122c, a fourteenth transistor 122n electrically connected to the fourth transistor 122d, and an electrical connection a fifteenth transistor 122o of the fifth transistor 122e, a sixteenth transistor 122p electrically connected to the sixth transistor 122f, a seventeenth transistor 122q electrically connected to the seventh transistor 122g, and a The eighteenth transistor 122r of the eighth transistor 122h is electrically connected to the eighth transistor 122r. In the embodiment, the digital analog converter 10 further has a bias input terminal 15 electrically connected to the bias input terminal 15 a first transistor group 122 and a second transistor group 133, the bias input terminal 15 is configured to generate a plurality of current sources, the size of the current sources being from the least significant bit end to the most significant bit end The power of 2 is increased. In addition, the electro-crystalline systems can be regarded as a switch, and the open relationships are used to determine the Whether the current source is circulating or not.

Please refer to FIG. 3 again, because the signal offset of the sixth control signal end 116, the seventh control signal end 117 and the eighth control signal end 118 in the control signal time interval is not obvious, the embodiment is The first control signal terminal 111, the second control signal terminal 112, the third control signal terminal 113, the fourth control signal terminal 114 and the fifth control signal terminal 115 are selected as the current compensation input of the current compensation circuit 13. In this embodiment, the gate group 131 of the current compensation circuit 13 has a first gate 1311, a second gate 1312, a third gate 1313, a fourth gate 1314, and a gate group 131. Fifth and Gate 1315, a sixth and gate 1316, a seventh And a gate 1317, an eighth and a gate 1318, a ninth gate 1319 and a tenth gate 131a, wherein the first gate 1311 is electrically connected to the first control signal end 111 and the second control signal end 112. The second gate 1312 is electrically connected to the first control signal end 111 and the third control signal end 113. The third gate 1313 is electrically connected to the fourth control signal end 114. The gate 1314 is electrically connected to the fourth control signal terminal 114 and the fifth control signal terminal 115. The fifth gate 1315 is electrically connected to the third control signal terminal 113 and the fifth control signal terminal 115. The gate 1316 is electrically connected to the third control signal terminal 113 and the fourth control signal terminal 114. The first gate 1311 has an output terminal 1311a, and the output terminal 1311a is electrically connected to the third gate 1313. , seventh and gate 1317, eighth and gate 1318, ninth and gate 1319, and tenth gate 131a, please refer to FIG. 3 again. The second inverter group 132 of the current compensation circuit 13 has a first An inverter 1321, a second inverter 1322, a third inverter 1323, a fourth inverter 1324, a fifth inverter 1325, a sixth inverter 1326 and a seventh inverter 1327, the first inverter 1321 is electrically connected to the first gate 1311, and the second inverter 1322 is electrically connected to the second gate The third inverter 1323 is electrically connected to the third gate 1313. The fourth inverter 1324 is electrically connected to the seventh gate 1317. The fifth inverter 1325 is electrically connected to the third inverter 1325. The eighth and third gates 1326 are electrically connected to the ninth gate 1319. The seventh inverter 1327 is electrically connected to the tenth gate 131a. Please refer to FIG. 3 again. The second transistor group 133 of the current compensation circuit 13 has a first transistor 133a, a second transistor 133b, a third transistor 133c, a fourth transistor 133d, a fifth transistor 133e, and a first transistor 133a. a sixth transistor 133f, a seventh transistor 133g, an eighth transistor 133h, and a ninth transistor a body 133i, a tenth transistor 133j, an eleventh transistor 133k, a twelfth transistor 133l, a thirteenth transistor 133m, and a fourteenth transistor 133n, the first inverter 1321 The second transistor 1323 is electrically connected to the second transistor 133b, and the third inverter 1323 is electrically connected to the third transistor 133c. The third inverter 1325 is electrically connected to the fifth transistor 133e, and the sixth inverter 1326 is electrically connected to the sixth transistor 133f. The seventh inverter 1327 is electrically connected to the seventh transistor 133g. The eighth transistor 133h is electrically connected to the first transistor 133a. The ninth transistor 133i is electrically connected to the second transistor. 133b, the tenth transistor 133j is electrically connected to the third transistor 133c, the eleventh transistor 133k is electrically connected to the fourth transistor 133d, and the twelfth transistor 133l is electrically connected to the first a fifth transistor 133e, the thirteenth transistor 133m is electrically connected to the sixth transistor 133f, and the fourteenth transistor 133n is electrically connected After the seventh transistor 133g is compensated by the current of the current compensation circuit 13, the digital analog converter 10 outputs integrated nonlinearity (INL) and differential nonlinearity (Differential Non-linearity). , DNL) can be less than 0.5LSB.

The first control signal terminal 111, the second control signal terminal 112, the third control signal terminal 113, the fourth control signal terminal 114 and the fifth control signal terminal 115 are used as the current compensation circuit 13 The current compensation input terminal is electrically connected to the gate group 131 of the current compensation circuit 13 by the control signal terminal, so that the digital analog conversion The integrated nonlinearity (INL) and the differential nonlinearity (DNL) generated by the circuit 12 can be less than 0.5LSB, and the digital analog conversion is achieved with high precision and high linearity. The requirements of the device 10.

The scope of the present invention is defined by the scope of the appended claims, and any changes and modifications made by those skilled in the art without departing from the spirit and scope of the invention are within the scope of the present invention. .

10‧‧‧Digital analog converter with current compensation

11‧‧‧Signal Sending Group

111‧‧‧First control signal end

112‧‧‧second control signal end

113‧‧‧ third control signal end

114‧‧‧fourth control signal end

115‧‧‧ fifth control signal end

116‧‧‧ sixth control signal end

117‧‧‧ seventh control signal end

118‧‧‧8th control signal end

12‧‧‧Digital analog conversion circuit

121‧‧‧First Inverter Group

1211‧‧‧First Inverter

1212‧‧‧Second inverter

1213‧‧‧ Third Inverter

1214‧‧‧fourth inverter

1215‧‧‧ fifth inverter

1216‧‧‧ sixth inverter

1217‧‧‧ seventh inverter

1218‧‧‧ eighth inverter

122‧‧‧First transistor group

122a‧‧‧First transistor

122b‧‧‧second transistor

122c‧‧‧ Third transistor

122d‧‧‧fourth transistor

122e‧‧‧ fifth transistor

122f‧‧‧ sixth transistor

122g‧‧‧ seventh transistor

122h‧‧‧8th transistor

122i‧‧‧Ninth transistor

122j‧‧‧10th transistor

122k‧‧‧Eleventh transistor

122l‧‧‧12th transistor

122m‧‧‧Thirteenth transistor

122n‧‧‧fourteenth transistor

122o‧‧‧ fifteenth crystal

122p‧‧‧16th transistor

122q‧‧‧17th transistor

122r‧‧‧18th transistor

123‧‧‧resistance

13‧‧‧ Current compensation circuit

131‧‧‧ and the gate group

1311‧‧‧First Gate

1311a‧‧‧output

1312‧‧‧Second Gate

1313‧‧‧third gate

1314‧‧‧4th gate

1315‧‧‧ Fifth Gate

1316‧‧‧ sixth gate

1317‧‧‧ seventh and gate

1318‧‧‧ eighth gate

1319‧‧‧ninth gate

131a‧‧‧10th Gate

132‧‧‧Second inverter group

1321‧‧‧First Inverter

1322‧‧‧Second inverter

1323‧‧‧ third inverter

1324‧‧‧fourth inverter

1325‧‧‧ fifth inverter

1326‧‧‧ sixth inverter

1327‧‧‧ seventh inverter

133‧‧‧Second transistor group

133a‧‧‧First transistor

133b‧‧‧second transistor

133c‧‧‧ Third transistor

133d‧‧‧fourth transistor

133e‧‧‧ fifth transistor

133f‧‧‧ sixth transistor

133g‧‧‧ seventh transistor

133h‧‧‧ eighth transistor

133i‧‧‧ninth transistor

133j‧‧‧10th transistor

133k‧‧‧Eleventh transistor

133l‧‧‧ twelfth transistor

133m‧‧‧ thirteenth crystal

133n‧‧‧fourteenth transistor

14‧‧‧Voltage output

15‧‧‧ bias input

20‧‧‧Differential digital analog converter

21‧‧‧First signal input buffer

22‧‧‧Second signal input buffer

23‧‧‧ bit switch

24‧‧‧ Thermometer code switch

25‧‧‧R-2R resistance structure

26‧‧‧ first output

27‧‧‧second output

1 is a block diagram of a circuit of a digitally compensated digital analog converter in accordance with a preferred embodiment of the present invention.

2 is a circuit diagram of a digital analog conversion circuit of a current-compensated digital analog converter in accordance with a preferred embodiment of the present invention.

Figure 3 is a circuit diagram of a current compensation circuit of a current compensated digital analog converter in accordance with a preferred embodiment of the present invention.

Figure 4: Circuit diagram of a conventional digital analog converter.

11‧‧‧Signal Sending Group

111‧‧‧First control signal end

112‧‧‧second control signal end

113‧‧‧ third control signal end

114‧‧‧fourth control signal end

115‧‧‧ fifth control signal end

13‧‧‧ Current compensation circuit

131‧‧‧ and the gate group

1311a‧‧‧output

1311‧‧‧First Gate

1312‧‧‧Second Gate

1313‧‧‧third gate

1314‧‧‧4th gate

1315‧‧‧ Fifth Gate

1316‧‧‧ sixth gate

1317‧‧‧ seventh and gate

1318‧‧‧ eighth gate

1319‧‧‧ninth gate

131a‧‧‧10th Gate

132‧‧‧Second inverter group

1321‧‧‧First Inverter

1322‧‧‧Second inverter

1323‧‧‧ third inverter

1324‧‧‧fourth inverter

1325‧‧‧ fifth inverter

1326‧‧‧ sixth inverter

1327‧‧‧ seventh inverter

133‧‧‧Second transistor group

133a‧‧‧First transistor

133b‧‧‧second transistor

133c‧‧‧ Third transistor

133d‧‧‧fourth transistor

133e‧‧‧ fifth transistor

133f‧‧‧ sixth transistor

133g‧‧‧ seventh transistor

133h‧‧‧ eighth transistor

133i‧‧‧ninth transistor

133j‧‧‧10th transistor

133k‧‧‧Eleventh transistor

133l‧‧‧ twelfth transistor

133m‧‧‧ thirteenth crystal

133n‧‧‧fourteenth transistor

14‧‧‧Voltage output

15‧‧‧ bias input

Claims (7)

A digital analog converter with current compensation includes: a signal transmission group having a first control signal terminal, a second control signal terminal, a third control signal terminal, and a fourth control signal terminal; a fifth analog signal terminal; a digital analog conversion circuit having a first inverter group, a first transistor group and a resistor, the first inverter group being electrically connected to the signal transmitting group, The first transistor group is electrically connected to the first inverter group, the resistor is electrically connected to the first transistor group; a current compensation circuit has a gate group and a second inverter And a second transistor group electrically connected to the first control signal end, the second control signal end, the third control signal end, and the fourth control signal end of the signal transmitting group a second control signal terminal, the second inverter group is electrically connected to the gate group, the second transistor group is electrically connected to the second inverter group; and a voltage output terminal, the first The transistor group, the resistor and the second transistor group are electrically connected to the voltage The end. The current-compensated digital analog converter according to the first aspect of the invention, wherein the gate group of the current compensation circuit has a first gate, a second gate, a third gate, and a gate 4th gate, 1 fifth gate, 1 sixth gate, 1 seventh gate, 1 eighth gate, 1 ninth gate and 10th gate, wherein the first and the gate are electrically connected The first and the second control signal terminals are electrically connected to the first and third control signal terminals, and the third and second gates are electrically connected to the fourth control signal terminal, the fourth And the gate is electrically connected to the fourth and fifth control signal terminals, and the fifth and the gate are electrically connected Connected to the third and the fifth control signal terminals, the sixth gate is electrically connected to the third and fourth control signal terminals, and the first gate system has an output terminal, and the output terminal is electrically connected The third, seventh, eighth, ninth and tenth gates. The current-compensated digital analog converter according to the second aspect of the invention, wherein the second inverter group of the current compensation circuit has a first inverter, a second inverter, and a third An inverter, a fourth inverter, a fifth inverter, a sixth inverter, and a seventh inverter, the first inverter is electrically connected to the first gate, the first The second inverter is electrically connected to the second gate, the third inverter is electrically connected to the third gate, and the fourth inverter is electrically connected to the seventh gate, the fifth The phase detector is electrically connected to the eighth gate, and the sixth inverter is electrically connected to the ninth gate. The seventh inverter is electrically connected to the tenth gate. The current-compensated digital analog converter according to the third aspect of the invention, wherein the second transistor group of the current compensation circuit has a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a a twelfth transistor, a thirteenth transistor, and a fourteenth transistor, wherein the first inverter is electrically connected to the first transistor, and the second inverter is electrically connected to the second a third inverter electrically connected to the third transistor, the fourth inverter is electrically connected to the fourth transistor, and the fifth inverter is electrically connected to the fifth transistor, The sixth inverter is electrically connected to the sixth transistor, the seventh inverter is electrically connected to the seventh transistor, and the eighth electro-crystal system is electrically connected to the first transistor, the ninth The electro-crystal system is electrically connected to the second transistor, and the tenth electro-crystal system is electrically connected to the third electro-crystal The eleventh electromorphic system is electrically connected to the fourth transistor, the twelfth electromorphic system is electrically connected to the fifth transistor, and the thirteenth electromorphic system is electrically connected to the sixth transistor. The fourteenth electro-crystal system is electrically connected to the seventh transistor. The current-compensated digital analog converter according to the first aspect of the invention, wherein the first transistor group of the digital analog conversion circuit has a first transistor, a second transistor, and a third transistor. a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor, the first transistor system The ninth transistor is electrically connected to the tenth transistor, and the third, fourth, fifth, sixth, seventh, eighth, ninth and tenth electromorphic systems are electrically connected The resistor and the voltage output are electrically connected. The current-compensated digital analog converter of claim 1, further comprising a bias input terminal electrically connected to the first transistor group and the second transistor group. The current-compensated digital analog converter according to the first aspect of the invention, wherein the signal transmitting group further has a sixth control signal end, a seventh control signal end and an eighth control signal end, the inversion The device group is electrically connected to the sixth, seventh and eighth control signal terminals.