TWI425440B - Hybrid multisample/supersample antialiasing - Google Patents

Description

Composite multiple sample/supersample anti-frequency stack

DETAILED DESCRIPTION OF THE INVENTION The present invention is generally directed to anti-aliasing techniques for mapping processing, and more particularly to dynamically adjusting the number of samples that are obscured by each pixel segment.

Previously, the graphics processor was configured to perform anti-aliasing by multi-sampling or oversampling. In multi-sampling, each pixel segment is shaded once and the resulting color values are copied to all covered sub-pixel samples. In oversampling, each pixel segment is shaded N times, one for each covered sub-pixel sample.

Multiple sampling is well suited for anti-stacking element edges because it is important that those samples are covered by the introduced primitives. The pattern is basically filtered out in advance, so the color value of the shading has a sufficiently low spatial frequency, so that it is appropriate to shield each pixel once. However, there are some effects, such as the transparency of the pattern and the high-frequency reflection of the glare, which can have a higher frequency than the pixel, and need to complete the shading at a frequency higher than the pixel to avoid the artificial factor of the stack. Oversampling basically needs to avoid these kinds of frequency stacks. However, shading each sample in the pixel can be quite expensive because shading is essentially the most expensive job in imaging. At the same time, some oversampling embodiments require input primitives to be processed many times, each time for each sub-pixel sample, which adds additional inefficiency. A shading rate greater than once per pixel but less than each sample is sufficient to alleviate the above-mentioned frequency stack.

Accordingly, the present technology requires a system and method for using pixel shading rates that are suitable for the geometry currently being developed. The shading rate can be lowered to improve image quality or reduced to improve shading performance.

A system and method for dynamically adjusting the pixel sampling rate during priming of a primitive can improve image quality or increase shading performance. The shading rate varies from one pixel (multiple sampling) to one sample per sample (sampled) or varies between them to improve image quality or increase shading performance. For a development target (image buffer) given the number of samples per pixel, the number of shutter passes can be dynamically selected. The combination of the supersample and the multiple sample antiband stack is used when the cluster of one pixel samples (multiple samples) is processed each time a fragment shutter is passed. The supersample clusters are combined for each pixel to produce an anti-aliased pixel.

Various embodiments of the method for using a composite anti-frequency stacking shading primitive in an arithmetic unit configured to generate multiple samples per pixel include receiving a drawing primitive and determining for use in anti-frequency The number of supersample clusters of each pixel that intersects the drawing primitive. The drawing primitive is opaquely multiplexed by a segment shading unit in the computing device, wherein the number of multiple passes for generating each composite anti-frequency stack of the drawing primitive is less than or equal to the super The number of sample clusters.

Various embodiments of the present invention include an arithmetic device configured to illuminate a drawing primitive using a composite anti-frequency stack. The computing device includes a field decoder coupled to a segment shading unit. The field resolver includes a composite anti-stack control unit configured to receive the drawing primitives and determine a number of supersample clusters for each of the pixels of the mapping primitives . The segment shading unit is configured to block the drawing primitives by using multiple passes, wherein the number of multiple passes of the pixels for generating each composite anti-frequency stack of the intersecting one drawing primitive is less than or equal to the super The number of sample clusters.

In the following description, numerous specific details are set forth to provide a more complete understanding of the invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without one or more of these specific details. In other instances, well-known features are not described in order to avoid obscuring the invention.

System Overview

The first figure is a block diagram of an operational system 100 configured to implement one or more aspects of the present invention. The computer system 100 includes a central processing unit (CPU) 102 and a system memory 104 that communicate via a bus path including a memory bridge 105. The memory bridge 105 can be, for example, a north bridge wafer that is connected to an I/O (input/output) bridge 107 via a bus or other communication path 106 (e.g., a HyperTransport link). The I/O bridge 107 can be, for example, a south bridge wafer that receives user input from one or more user input devices 108 (eg, a keyboard, mouse) and forwards the input via path 106 and memory bridge 105. Go to the CPU 102. A parallel processing subsystem 112 is coupled to the memory bridge 105 via a bus or other communication path 113 (e.g., PCI Express, accelerated graphics port or HyperTransport link); in one embodiment, the parallel processing subsystem 112 is a A graphics subsystem that passes pixels to a display device 110 (eg, a conventional CRT or LCD type of monitor). A device driver 103 stored in system memory 104 is coupled between programs executed by CPU 102, such as an application, and parallel processing subsystem 112, which translates program instructions, which are executed by parallel processing subsystem 112 as needed. .

A system disk 114 is also coupled to the I/O bridge 107. A switch 116 provides a connection between the I/O bridge 107 and other components such as the network adapter 118 and the various embedded cards 120, 121. Other components (not explicitly shown), including USB or other port connections, CD drives, DVD drives, thin film recording devices, and the like, may also be coupled to I/O bridge 107. The communication paths interconnected to the various components in the first figure can be implemented using any suitable protocol, such as PCI (Peripheral Component Interconnect), PCI Express (PCI-E), AGP (Accelerated Drawing, "Accelerated Graphics Port"), HyperTransport, or any other bus or peer-to-peer protocol, and connections between different devices, may use different protocols as are known in the art.

A specific embodiment of a parallel processing subsystem 112 is shown in the second figure. Parallel processing subsystem 112 includes one or more Parallel Processing Units (PPUs) 202, each coupled to a local parallel processing (PP) memory 204. In summary, a parallel processing subsystem includes a number (U) of PPUs, where U ≧ 1. (Several instances of the analog component are labeled here to identify the reference number of the object, and the number in parentheses identifies the desired instance). The PPU 202 and the PP memory 204 can be implemented, for example, using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), and a memory device.

As with the details shown in PPU 202(0), each PPU 202 includes a master interface 206 that communicates with other portions of system 100 via communication path 113, which is coupled to memory bridge 105 (or in an alternative The specific embodiment is directly connected to the CPU 102). In one embodiment, the communication path 113 is a PCI-E link in which a dedicated line is assigned to each PPU 202 as is known in the art. It can also use other communication paths. The master interface 206 generates packets (or other signals) for transmission over the communication path 113, and also receives all incoming packets (or other signals) from the communication path 113 and directs them to the appropriate components of the PPU 202. For example, commands regarding processing operations may be directed to a front end unit 212, and commands for memory operations (eg, read or written from PP memory 204) may be directed to a memory interface 214. The master interface 206, the front end unit 212, and the memory interface 214 may be generally designed, and since they are not critical to the present invention, detailed description thereof will be omitted.

Each PPU 202 preferably implements a highly parallel processor. As shown in the details of PPU 202(0), a PPU 202 includes C cores 208, where C ≧ 1. Each processor core 208 is capable of executing a large number (e.g., tens or hundreds) of threads simultaneously, each of which is an instance of a program; a specific embodiment of a multi-thread processing core 208 is described below. Core 208 receives processing operations to be performed via a network allocation unit 210, which receives commands from a front end unit 212 that define processing operations. The work distribution unit 210 can implement a variety of algorithms for assigning work. For example, in one embodiment, the work distribution unit 210 receives a "READY" signal from each core 208 indicating whether the core has sufficient resources to accept a new processing job. When a new processing job arrives, the work distribution unit 210 assigns the work to a core 208 to establish the ready signal; if no core 208 establishes the ready signal, the work distribution unit 210 maintains the new processing until A ready signal is established by a core 208. Those skilled in the art will appreciate that other algorithms may be used and that the particular method by which work distribution unit 210 allocates incoming processing work is not critical to the invention.

Core 208 is in communication with memory interface 214 for reading or writing from a plurality of external memory devices. In one embodiment, the memory interface 214 includes an interface that is adjustable to communicate with the local PP memory 204 and to the host interface 206, whereby the core 208 can be interfaced with the system memory 104 or not at the PPU 202. Other local memory communicates. The memory interface 214 may be a conventional design and a detailed description thereof will be omitted.

The core 208 can be programmed to perform processing for a wide variety of applications, including but not limited to linear and non-linear data conversion, filtering of film and/or sound data, modeling operations (eg, applying physical laws to determine the position of an object). , speed and other properties), image development jobs (such as vertex shaders, geometry shutters and/or pixel shader programs) and more. The PPU 202 can transfer data from the system memory 104 and/or the local PP memory 204 to internal (on-wafer) memory, process the data, and write the resulting data back to the system memory 104 and/or local PP memory. 204, wherein the material is accessible by other system components, including, for example, CPU 102 or another parallel processing subsystem 112.

Referring again to the first figure, in some embodiments, some or all of the PPUs 202 in the parallel processing subsystem 112 are graphics processors having a visualization pipeline that can be configured to execute with respect to the CPU 102 and/or The system memory 104 generates various operations of the pixel data via the drawing data supplied from the memory bridge 105 and the bus bar 113, and interacts with the local PP memory 204 (which can be used as a drawing memory, including, for example, a conventional image frame buffer). To store and update pixel data, pass pixel data to display device 110 and the like. In some embodiments, parallel processing subsystem 112 can include one or more PPUs 202 that can operate as a graphics processor and one or more other PPUs 202 that can be used for general purpose operations. The PPUs 202 can be the same or different, and each PPU 202 can have its own proprietary PP memory device(s) 204 or no proprietary (multiple) PP memory devices.

In operation, CPU 102 is the master processor of system 100 that controls and coordinates the operations of other system components. In particular, CPU 102 issues commands to control the operation of PPU 202. In some embodiments, CPU 102 writes one of each PPU command stream to a pushbuffer (not explicitly shown in the first figure), which can be located in system memory 104, PP memory. The body 204 or another storage location that is simultaneously accessible by the CPU 102 and the PPU 202. The PPU 202 reads the command stream from the push-in buffer and executes the command asynchronously with the job of the CPU 102. Accordingly, PPU 202 can be configured to distribute the processing of CPU 102 to increase the processing traffic and/or performance of system 100.

It will be appreciated that the systems shown herein are merely illustrative and that there are many variations and modifications possible. The connection topology, including the number and configuration of the bridges, can be modified as needed. For example, in some embodiments, system memory 104 is directly coupled to CPU 102 rather than through a bridge, while other devices communicate with system memory 104 via memory bridge 105 and CPU 102. In other alternative topologies, parallel processing subsystem 112 is coupled to I/O bridge 107 or directly to CPU 102 rather than to memory bridge 105. In still other embodiments, I/O bridge 107 and memory bridge 105 can be integrated into a single wafer. The particular components shown herein are optional; for example, they can support any number of embedded cards or peripheral devices. In some embodiments, switch 116 is omitted and network adapter 118 and embedded cards 120, 121 are directly connected to I/O bridge 107.

The connection of PPU 202 to other portions of system 100 can also vary. In some embodiments, the PP system 112 is implemented as an embedded card that can be inserted into an expansion slot of the system 100. In other embodiments, PPU 202 can be integrated on a single wafer, such as memory bridge 105 or I/O bridge 107, using a bus bridge. In still other embodiments, some or all of the components of PPU 202 may be integrated with CPU 102 on a single wafer.

A PPU can have any number of local PP memories, does not include local memory, and can use local memory and system memory in any combination. For example, a PPU 202 can be a graphics processor in a unified memory architecture (UMA) embodiment; in these embodiments, only a little or no dedicated graphics (PP) memory is provided. Body, while PPU 202 will use system memory exclusively or almost exclusively. In a UMA embodiment, a PPU 202 can be integrated into a bridge wafer or processor chip, or provided as a discrete wafer having a high speed link (eg, PCI-E), such as through a bridge wafer Connect the PPU to the system memory.

As noted above, it can include any number of PPUs 202 in a parallel processing subsystem. For example, multiple PPUs 202 can be provided on a single embedded card, or multiple embedded cards can be connected to communication path 113, or one or more PPUs 202 can be integrated into a bridge wafer. The PPUs in a multi-PPU system may be the same or different from each other; for example, different PPUs may have different numbers of cores, different numbers of local PP memories, and the like. When there are multiple PPUs 202, they can operate in parallel to process data at a higher traffic than is possible with a single PPU 202. Systems incorporating one or more PPUs 202 can be implemented with a variety of configurations and style factors, including desktop, laptop, or palm-sized personal computers, servers, workstations, game consoles, embedded systems, and the like.

Core overview

The third diagram is a block diagram of the core 208 of the parallel computing subsystem 112 of the second diagram in accordance with one or more aspects of the present invention. PPU 202 includes a core 208 (or multiple cores 208) configured to execute a large number of threads in parallel, wherein the term "thread" refers to an instance of a context that is executed on a particular input data set. a specific program. In some embodiments, a single instruction, multiple-data (multiple-data, SIMD) instruction issuance technique is used to support parallel execution of a large number of threads without the need to provide multiple independent instruction units.

In one embodiment, each core 208 includes an array of P (eg, 8 or 16 etc.) parallel processing engines 302 configured to receive SIMD instructions from a single instruction unit 312. Each processing engine 302 is preferably a functional unit (e.g., an arithmetic logic unit, etc.) that includes an identical combination. The functional units can be pipelined to allow a new instruction to be issued before a previous instruction has been completed, as is well known in the art. It can provide any combination of functional units. In a specific embodiment, the functional units support a variety of operations, including integer and floating point arithmetic (eg, addition and multiplication), comparison operations, Boolean operations (AND, OR, XOR), bit offsets, and various Algebraic functions (such as plane interpolation, trigonometric functions, exponentials, and logarithmic functions, etc.); and the same functional unit hardware can be utilized to perform different operations.

Each processing engine 302 uses a space in a local register file (LRF) 304 for storing its local input data, intermediate results, and the like. In one embodiment, the local register file 304 is divided into P lines by physical or logical regions, each of which has a certain number of items (where each item can store, for example, a 32-bit character). A line is assigned to each processing engine 302, and corresponding items in different lines can present data of different threads executing the same program to implement SIMD execution. In some embodiments, each processing engine 302 can only access LRF items in the line assigned to it. The total number of items in the local register file 304 is preferably sufficiently large to support multiple synchronization threads per processing engine 302.

Each processing engine 302 also has access to a on-wafer shared memory 306 that is shared among all processing engines 302 in core 208. The shared memory 306 can be expanded as needed, and in some embodiments, any processing engine 302 can read or write from any location in the shared memory 306 with equal low hysteresis (eg, as compared to Access local register file 304). In some embodiments, the shared memory 306 is implemented as a shared scratchpad file; in other embodiments, the shared memory 306 can be implemented using shared cache memory.

In addition to shared memory 306, some embodiments may provide additional on-wafer parametric memory and/or cache(s) 308 that may be implemented, for example, as a conventional RAM or cache. The parameter memory/cache 308 can be used, for example, to save state parameters and/or other data (e.g., various constants) that would be required by multiple threads. The processing engine 302 can also access the off-chip "universal" memory through the memory interface 214, which can include, for example, the PP memory 204 and/or the system memory 104, and the system memory 104 can be accessed via the host interface 206. . It should be understood that any memory other than PPU 202 can be used as general purpose memory.

In one embodiment, each processing engine 302 is multi-threaded and can execute up to a certain number of G (e.g., 24) threads, for example by maintaining it in the local register file 304. The current status information associated with each thread is associated with different parts of the specified line. Processing engine 302 is preferably designed to quickly switch from one thread to another so that instructions from different threads can be issued in any order without loss of efficiency. Because each thread can correspond to a different context, multiple contexts can be processed on multiple loops when different threads are issued for each loop.

Instruction unit 312 is configured such that for any given processing loop, it issues an instruction (INSTR) to each P processing engine 302. Each processing engine 302 can receive different instructions for any given processing loop while multiple contexts are simultaneously processing. When all P processing engines 302 process a single context, core 208 implements a P-to-SIMD micro-architecture. Since each processing engine 302 is also multi-threaded, its highest synchronization supports G threads, and the core 208 in this embodiment may have up to P*G synchronous execution threads. For example, if P=16 and G=24, the core 208 supports up to 384 synchronization threads for a single context or N*24 synchronization threads for each context, where N is the processing engine 302 assigned to the context. Number of.

The operation of core 208 is preferably controlled via a work distribution unit 200. In some embodiments, the work distribution unit 200 receives metrics (eg, primitive data, vertex data, and/or pixel data) of the material to be processed, and includes data or instructions that define how the material is to be processed (eg, The position of the program that is to be executed is pushed into the buffer. The work distribution unit 210 can load the data to be processed into the shared memory 306 and load the parameters into the parameter memory 308. Work allocation unit 210 also initializes each new context in instruction unit 312 and then signals instruction unit 312 to begin execution of the context. Instruction unit 312 reads the instructions into the buffer and executes the instructions to produce the processed data. When the execution of a context is completed, the core 208 is preferably notified to the work distribution unit 210. Work distribution unit 210 can then initialize other programs, such as receiving output data from shared memory 306, and/or preparing core 208 to perform additional context.

It will be appreciated that the parallel processing units and core architectures described herein are merely illustrative and that many variations and modifications are possible. It can include any number of processing engines. In some embodiments, each processing engine 302 has its own local register file, and the allocation of local register file entries for each thread can be fixed or set as desired. In particular, items of local register file 304 can be allocated to handle each context. Moreover, when only one core 208 is shown, a PPU 202 can include any number of cores 208, which are preferably of the same design as each other such that the execution behavior does not receive a special processing job depending on which core 208 receives. . Each core 208 preferably operates independently of the other cores 208 and has its own processing engine, shared memory, and the like.

Drawing pipeline architecture

The fourth figure is a conceptual diagram of a drawing processing pipeline 400 in accordance with one or more aspects of the present invention. PPU 202 can be configured to form a graphics processing pipeline 400. For example, core 208 can be configured to perform the functions of one or more vertex processing units 444, geometry processing unit 448, and a fragment processing unit 460. Multiple functions in data composer 442, primitive composer 446, scan field parser 445, and scan field work unit 465 may also be performed by core 208. In addition, the drawing processing pipeline 40 can use one or more of the vertex processing unit 444, the geometry processing unit 448, the fragment processing unit 460, the data composer 442, the primitive composer 446, the scan field parser 455, and the scan field work unit 465. A dedicated processing unit is implemented.

The data composer 442 is a processing unit that collects vertex data of high-order surfaces, primitives, and the like, and outputs the vertex data to the vertex processing unit 444. Vertex processing unit 444 is a programmable execution unit configured to execute a vertex shader program that converts vertex data as specified by the vertex shader program. For example, vertex processing unit 444 can be programmed to convert the vertex data from an object coordinate representation (object space) to another coordinate system, such as world space or a normalized device coordinate (NDC) space. Vertex processing unit 444 can read the data stored in PP memory 204 or system memory 104 for processing the vertex data.

The primitive composer 446 receives the processed vertex data from the vertex processing unit 444 and constructs drawing primitives, such as points, lines, triangles, or the like, for processing by the geometry processing unit 448. Geometry processing unit 448 is a programmable execution unit configured to execute a geometry shader program that converts graphics primitives received from primitive component 446 in accordance with the designation of the geometry shader program. For example, geometry processing unit 448 can be programmed to distinguish the drawing primitives from one or more new drawing primitives and calculate parameters, such as plane equation coefficients, which are used to rasterize the new drawing primitives. . In some embodiments of the invention, geometry processing unit 448 may also add or remove elements in the geometry stream. Geometry processing unit 448 outputs the parameters and vertices that specify a new drawing primitive to scan field parser 455 or to memory interface 214. Geometry processing unit 448 can read the data stored in PP memory 204 or system memory 104 for processing the geometry.

The field parser 455 scans and converts the new drawing primitives and outputs the fragment and coverage data to the fragment processing unit 260. When the anti-frequency stack is used to generate image data, the field resolver 455 is configured to generate sub-pixel sample coverage data. When a composite anti-aliasing stack is used, a composite anti-stack control unit 500, which may be present in the field decoder 455, is configured to determine the number of passing fragment processing units 460 for processing each primitive , as described in the fifth C and sixth figures.

Fragment processing unit 460 is a programmable execution unit configured to execute a fragment shader program that converts the segments received from field field parser 455 as specified by the fragment shader programs. For example, segment processing unit 460 can be programmed to perform jobs, such as individual corrections, pattern mapping, shading, blending, and the like, to generate segments that are to be output to the field of view unit 465. The fragment processing unit 460 can read the data stored in the PP memory 204 or the system memory 104 for processing the fragment data. The segments are shaded at the pixel, sample or supersample cluster granularity depending on the sampling rate selected by the composite anti-aliasing control unit.

The memory interface 214 generates a read request for data stored in the drawing memory and performs a pattern filtering operation such as bilinear, triple linear, anisotropic, and the like. In some embodiments of the invention, the memory interface 214 can be configured to decompress data. In particular, the memory interface 214 can be configured to decompress fixed length block encoded material, such as compressed data represented in DXT format. The fieldwork unit 465 is a processing unit that performs field parser jobs, such as templates, Z-type tests, and the like, and outputs pixel data as processed drawing data for storage in the drawing memory. The processed graphics data may be stored in a graphics memory, such as PP memory 204, and/or system memory 104, for display on display device 110, or for further use by CPU 102 or a parallel processing subsystem. 112 processing. In some embodiments of the invention, the fieldwork unit 465 is configured to compress z or color material that is written to the memory and decompressed the z or color material read from the memory.

Composite anti-frequency stack

As previously mentioned, the PPU 202 can be configured to perform shading at various sampling rates to improve image quality or improve shading performance. A composite anti-stack control unit determines the passage of some of the shutters for each pixel in the shading-based cell. A supersample cluster of one or more multiple samples (sub-pixel samples) per pixel may be processed by one of the cores 208 configured to pass each of the fragment processing units 460 to generate for all multiple samples in the supersample cluster Do a copy of one of the single shaded color values. After developing a scene, the samples of the supersample clusters are combined to produce an image of the anti-alias stack.

The number of sub-pixel samples and shutter passes per primitive is increased to improve image quality. The number of sub-pixel samples is determined when the application is enabled and is persisted for each pixel of a development target (image buffer). The composite anti-stack control unit can dynamically determine the number of shading passes based on the development state, such as Alpha test enable/disable, pattern map content, user-provided quality/performance control, or the like. By.

Figure 5A shows supersample clusters 503, 511 and multiple samples 502, 504 and 513 in a pixel 501 in accordance with one or more aspects of the present invention. When eight sub-pixel samples are used for anti-aliasing, a combination of a plurality of different multiple samples and super-sample clusters can be used to generate the eight sub-pixel samples. In the example shown in FIG. 5A, each of the three hypersample clusters 503 and the supersample clusters 511 includes two multiple samples of a total of eight sub-pixel sample positions of the pixel 501, such as multiples in the supersample cluster 511. Samples 502 and 504. The other eight sub-pixel sample configurations include a maximum of eight hypersample clusters, each having one multiple sample, or at least one hypersample cluster with eight super samples. Shading is performed once for each supersample cluster, and the shading value, such as color, is stored for all of the multiple samples within the supersample cluster.

The shutter attributes may be sampled at a location of a particular multiple sample in the supersample cluster, or they may be sampled at or near some other sample cluster. For example, in Section 5A the segment attributes (colors, texture coordinates, and the like) may be sampled at the entity multiple sample locations, such as multiple samples 502 in the oversample cluster 511. Furthermore, when the segment only partially covers a supersample cluster, it is preferred to adjust the location at which the attribute is sampled to be within the region of the multiple samples covered by the supersample cluster. This is often referred to as centroid sampling, although the term is applied here to the supersample cluster rather than to the entire pixel segment.

Figure 5B shows a segment 509 and a centroid position 517 in a supersample cluster 511 in accordance with one or more aspects of the present invention. In some embodiments of the invention, centroid sampling is used to modify the location at which the attribute is evaluated to preferably correspond to the screen area that is actually covered by the segment. In some embodiments of the invention, the sample interpolation unit 510 can be configured to sample each hypersample cluster at a particular multiple sample location or at an approximate centroid location.

The centroid may be the geometric centroid of the plurality of covered samples, or it may be, for example, by selecting the covered multiple samples of the supersample cluster closest to the centroid of the entire covered supersample cluster approximate. For example, a centroid position 517 is a multiple sample position of an operation at the geometric center of the supersample cluster 511, which is used to represent the color of the sample of the supersample cluster 511 because the position of the multiple sample 502 is near an edge, rather than Near the center of segment 509. A shading value is computed at the centroid position 517 to more accurately represent the segment color compared to the multi-sample 502.

FIG. 5C is a block diagram of a portion of a graphics processing pipeline 400 in accordance with one or more aspects of the present invention, including a field decoder 455, a segment processing unit 460, and a field operator unit 465. Other processing units may be included within scan field parser 455, segment processing unit 460, and scan field work unit 465. Those other processing units are not shown in the fifth C diagram, as they may be schematic designs, and since they are not critical to the invention, a detailed description thereof will be omitted.

The field parser 455 receives the primitives from the geometry processing unit 448 and produces a fragment for each pixel intersected by the primitive. A composite anti-stack control unit 500 (as needed within the field resolver 455) can be configured to dynamically determine the number of shutter passes for processing the segments of each primitive based on the development state, For example, Alfa test enables/disables, map map content, user-provided quality/performance controls, or the like.

The composite anti-stack control unit 500 improves the anti-overlap efficiency by performing more shading of the primitives, which will benefit from a higher shading rate and lower the shading rate of other components. The hybrid anti-stack control unit 500 can be configured by the user, the application or device driver 103 to operate with a variety of quality settings. These ranges from the lowest quality setting "forever multiple samples" to the highest quality setting "forever sample". The intermediate quality setting can take into account the state of the visualization pipeline when determining the number of shading passes. For example, if the Alfa test or the shutter pixel deletion is enabled, more shading is required. Conversely, when high performance is specified, the Alpha test and the shutter pixel deletion are disabled, and the sampling rate can be reduced by the composite anti-stack control unit 500. The composite anti-overlap control unit 500 can also determine the number of shading passes in consideration of the characteristics of the pixel shutter or pattern sampler setting. Those skilled in the art will appreciate the various conditions used by the hybrid anti-stack control unit 500 to determine the number of shading passes. In conventional drawing systems, the sampling rate is determined for all of the primitives in a scene based on user-provided or fixed settings. Moreover, sampling of such conventional systems is limited to multiple sampling or oversampling, and is not an intermediate choice.

In one embodiment, the field decoder 455 generates a 2x2 square pixel segment that is received by the composite anti-aliasing integrator unit 515. When the composite anti-stack control unit 500 sets pass =1 (ie, when multi-sampling), the composite anti-stack integrator unit 515 transmits the uncorrected four-square to segment processing unit 460. However, when the composite anti-stack control unit 500 is set to pass N>1, the composite anti-stack integrator unit 515 outputs each of the four blocks to the segment processing unit 460 a plurality of times, which includes corresponding to the shutter. Pass the number. The composite anti-aliasing integrator unit 515 can mask the coverage transmitted to the segment processing unit 460 such that only multiple samples corresponding to the currently passed supersample cluster are enabled. In other embodiments, the segment processing unit 460 can mask the coverage based on the number of passes provided to it by the composite anti-aliasing integrator unit 515. It is noted that other embodiments may be integrated in an area other than a 2x2 segment four squares, such as a single pixel, a 4x4 segment square, or the like. It is advantageous to integrate in the region of pixels (four squares) outside the primitive, because the map map data may be reused for the passage of a specific four-block follower, thereby integrating over the primitive, which can To be larger, the pattern data is retrieved from the memory (eg, PP memory 204 or system memory 104).

Importantly, the geometric operations required to produce the segments are not repeated for each shutter pass. Conversely, a conventional system that uses the same mask to supersample to a multiple sample buffer substantially repeats the geometric operations for each shutter pass. Note that the primitive attributes sampled in the fragment processing unit 460 need only be computed once, regardless of the number of composite anti-aliasing passes, since they will be referenced by the four squares of the subsequent integration and then ignored.

In the fragment processing unit 460, the present lookup table uses the composite anti-aliasing parameters and the number of passes to determine where the interpolated fragment parameters are sampled. The sample lookup table 505 can select a centroid location or a multiple sample location for each supersample cluster. The multiple sample positions are output to the same present interpolation unit 510, which computes one or more interpolated parameters, such as color channels (red, green, blue, Alpha), pattern coordinates, and the like. For each supersample cluster, that is, a parameter interpolated for one of each pixel in the four squares of the pixel. A shutter 520 uses the techniques known to those skilled in the art to perform a fragment shutter program or the like to process the set of interpolated parameters for each pixel in the four squares of the pixel, thereby generating each supersample. A shaded pixel value of the cluster, such as color.

During the shading, due to the Alpha test or the shutter pixel deletion, the sub-pixel samples of each super-sample cluster can be excluded (culled or deleted), so that the coverage generated by the field is modified to be deleted based on the pixels. Or Alfa test results to produce a back-end shutter coverage. Because the supersample clusters are processed in independent pass shutters 520, the oversample clusters can be individually excluded during the Alfa test. Conversely, when conventional multi-sampling is used to process all sub-pixel samples in a single shading pass, all sub-pixel samples can be maintained or excluded, resulting in a rougher one of the lower quality images. Test granularity.

The shutter 520 outputs the shaded pixel values and the sub-pixel coverage (which may be modified compared to the coverage provided by the field resolver 455) to a color buffer 535 and a coverage aggregator 530, respectively. The coverage aggregator 530 accumulates each of the shutters to generate aggregated coverage information for each pixel through the subsequent segment shade coverage. The color buffer 535 accumulates the shading value of each pixel. The aggregated coverage information is output to the field work unit 465 when the shading value of the last shutter pass is received. The shading value of the four squares of the pixel may be output with the aggregated coverage information, or may be output later, such as after the Z-test is completed by the fieldwork unit 465. In other embodiments of the invention, coverage aggregator 530 and color buffer 535 may be omitted.

Coverage aggregation and color values are combined into a color buffer that is advantageous in systems where the samples of each pixel are collectively in memory, so multiple samples can be written or read using a single memory transaction. . Other embodiments may omit the coverage aggregator 530. The coverage aggregator 530 is less advantageous in systems that do not continuously store sample values of one pixel in memory.

A selective z/color compression unit 550 within the fieldwork unit 465 receives the aggregated coverage information, and another representation of the z-value or z, or the depth value of the segments (after the z-test), And generating a compressed z value for a pixel region. The Z/color compression unit 550 can also receive the aggregated color values of the segments and produce a compressed color value for a pixel region. This compression can be improved when applied to a large group of pixels. Thus, a number of pixels and four squares can be grouped together and tested by the z-type before the result is compressed. Importantly, the composite anti-frequency stack does not exclude or reduce the effectiveness of z-compression. Z-type compression is preferably used to reduce the memory bandwidth requirements for accessing the z-buffer, and in some embodiments, accessing the memory footprint.

Figure 6 is a flow diagram of the method steps for performing a composite anti-frequency stack in accordance with one or more aspects of the present invention. In step 610, the composite anti-stack control unit 500 receives a primitive. In step 615, the composite anti-stack control unit 500 determines if the composite anti-frequency stack is enabled, and if not enabled, the segment is processed using a conventional anti-frequency stack. If the composite anti-frequency stack is enabled in step 615, then in step 635 the composite anti-stack control unit 500 determines the composite anti-aliasing parameters for the primitive. More specifically, the composite anti-stack control unit 500 determines the number of super-sample clusters (passer passes) to be used when shading each pixel intersected by the primitive.

In step 640, the field resolver 455 generates a sample level coverage of the portion of the coverage of the primitive. The granularity of this coverage may be rough or fine, but at least one pixel and four squares. The field resolver 455 outputs coverage information of a four squares intersecting the primitive to the composite anti-aliasing integrator unit 515. The composite anti-stack integrator unit 515 expands each of the four squares based on the composite anti-frequency stacking parameters to block the four squares in multiple passes. The composite anti-stack integrator unit 515 can be configured to bypass the shutter pass when all of the multiple samples are uncovered in an oversampled cluster based on the coverage information. In step 643, the composite anti-stack integrator unit 515 determines the number of passes (first, second, etc.) and outputs the four squares of the pixels and the number of passes to the segment processing unit 460. As previously mentioned, when the number of passes is greater than one, the composite anti-stack integrator unit 515 can mask the coverage information. The sample lookup table 505 indexes the number of passes and the number of the multiple samples to read the stylized values of the multiple sample locations, including the location within the supersample cluster for interpolating the segment parameters Said. The interpolated parameters are computed by the sample interpolation unit 510 for the supersample cluster.

In step 645, the segment processing unit 460 blocks the four squares of the pixel, producing a shading value for each of the supersample clusters, i.e., one of each pixel in the four squares of the pixel. Within a supersample cluster, the shading value will be used for each multisample covered by the primitive. The segment processing unit 460 also outputs the four-block rear-span shutter coverage of the pixel. The back-end shutter coverage can be different from the scanned field coverage information because multiple samples can be eliminated during shading, as previously described.

In step 650, the composite anti-stack integrator unit 515 determines whether the other four shutters will be used to process the four squares of the pixel, and if so, steps 643 and 645 pass for the other shutter (second, third) Wait) to repeat. If the composite anti-aliasing integrator unit 515 determines in step 650 that another shutter is not required to process the pixel four squares, then in step 660, the coverage aggregator 530 is combined with each shutter through a subsequent segment of the shutter. Range to generate coverage information for the aggregation of the four squares of the pixel. In step 660, the coverage aggregator 530 can also combine each of the shutters to generate an aggregated color value of the four squares of the pixel by the subsequent shade color value. The coverage aggregator 530 can be configured to aggregate the back-end shade color and coverage information at a multiple four-block level. In step 665, field field unit 465 executes the field job to determine which shading values are to be written to the picture frame buffer. The field job can be performed at the four-block or multiple four-block level. The Z/color compression unit 550 within the field work unit 465 can compress the z and/or color data of the four squares of the pixel before the z and/or color material is stored in the z buffer and/or color buffer.

In step 670, the scan field parser 455 determines if there is another pixel four blocks intersecting the primitive, and if so, in step 640, the scan field parser 455 processes a different overlay by the primitive. Pixels four squares. If, in step 670, the field resolver 455 determines that all of the pixels four blocks intersected by the primitive have been shaded, then in step 675, the primitive processing is complete. In a pipelined system, one or more of the steps shown in the sixth diagram can be performed in parallel for different four squares.

The composite anti-stack control unit 500 can dynamically determine each based on the visualization state (eg, Alpha test enable/disable, pattern map content, user-provided quality/performance control, or the like) A composite anti-aliasing parameter for primitives (eg, the number of supersample clusters per pixel). Adjusting the anti-frequency stack based on the development state can improve efficiency because the cells benefiting from the high-quality anti-frequency stack use more samples to block the light, and other primitives use less samples to shield the light, and optimize Image quality and performance.

The invention has been described above with reference to specific embodiments. It will be appreciated by those skilled in the art that various modifications and changes can be made without departing from the spirit and scope of the invention. An embodiment of the invention may be implemented as a program product for use by a computer system. The program of the program product defines the functions of the specific embodiments (including the methods described herein) and can be included on a variety of computer readable storage media. Exemplary computer readable storage media include, but are not limited to: (i) non-writable storage media (eg, a read-only memory device in a computer, such as a CD-ROM disc that can be read by a CD-ROM, fast) Flash memory, ROM chip, or any kind of solid non-volatile semiconductor memory) on which information can be stored permanently; and (ii) writeable to storage media (eg floppy disk, hard disk in a disk drive) A machine, or any kind of solid state random access semiconductor memory, on which information that can be changed can be stored. Accordingly, the foregoing description and drawings are to be regarded as illustrative

100. . . Computing system

102. . . Central processing unit

103. . . Device driver

104. . . System memory

105. . . Memory bridge

106. . . Communication path

107. . . Input/output bridge

108. . . Input device

110. . . Display device

112. . . Parallel processing subsystem

113. . . Communication path

114. . . System dish

116. . . switch

118. . . Network adapter

120. . . Embedded card

121. . . Embedded card

202(0)~(1). . . Parallel processing unit

204(0)~(U-1). . . Parallel processing of memory

206. . . Master interface

208(0)~(C-1). . . core

210. . . Work distribution unit

212. . . Front end unit

214. . . Memory interface

302(0)~(P-1). . . Processing engine

304. . . Local register file

306. . . Shared memory

308. . . Parameter memory/cache

312. . . Command unit

400. . . Drawing processing pipeline

442. . . Data component

444. . . Vertex processing unit

446. . . Primitive combiner

448. . . Geometric processing unit

455. . . Field parser

460. . . Fragment processing unit

465. . . Field unit

500. . . Composite anti-frequency stack control unit

501. . . Pixel

502. . . Multiple samples

503. . . Supersample cluster

504. . . Multiple samples

505. . . Sample lookup table

509. . . Fragment

510. . . Sample interpolation unit

511. . . Supersample cluster

513. . . Multiple samples

515. . . Composite anti-frequency stack integrator unit

517. . . Centroid position

520. . . Shader

530. . . Coverage aggregator

535. . . Color buffer

550. . . Z/color compression unit

Therefore, a more specific description of the present invention may be made in the foregoing description of the preferred embodiments of the invention. It is to be understood, however, that the drawings are not intended to

The first figure is a block diagram of an operational system configured to implement one or more aspects of the present invention;

2 is a block diagram of a parallel processing subsystem of the computing system of the first diagram in accordance with one or more aspects of the present invention;

The third diagram is a block diagram of the core of the parallel computing subsystem of the second diagram in accordance with one or more aspects of the present invention;

The fourth figure is a conceptual diagram of a drawing processing pipeline in accordance with one or more aspects of the present invention;

Figure 5A is a supersample cluster and multiple sample locations within a pixel in accordance with one or more aspects of the present invention;

Figure 5B is a fragment and a centroid position within a multi-sample cluster in accordance with one or more aspects of the present invention;

Figure 5C is a block diagram of a portion of the drawing processing pipeline in accordance with one or more aspects of the present invention; and

Figure 6 is a flow diagram of the method steps for performing a composite anti-frequency stack in accordance with one or more aspects of the present invention.

455. . . Field parser

460. . . Fragment processing unit

465. . . Field unit

500. . . Composite anti-frequency stack control unit

505. . . Sample lookup table

510. . . Sample interpolation unit

515. . . Composite anti-frequency stack integrator unit

520. . . Shader

530. . . Coverage aggregator

535. . . Color buffer

550. . . Z/color compression unit

Claims (10)

An arithmetic device configured to use a composite anti-frequency stack to illuminate a drawing primitive, the computing device configured to receive a drawing primitive; and determine an ultra-overband for each pixel of the drawing primitive The number of sample clusters; the number of multipasses used when each pixel of the drawing primitive is intersected according to the determined number of supersample clusters; rasterizing the drawing primitive to intersect the drawing primitive a segment is generated for each pixel; and a segment processing unit in the computing device uses the determined number of multiple passes to block each segment to produce at least one composite frequency offset for the mapping primitive Stacked pixels, wherein for each pass of the segment processor, multiple geometric operations performed while rasterizing the drawing unit are not repeated. The computing device of claim 1, wherein the number of clusters of the super samples is determined based on a development state of the computing device. The computing device of claim 2, wherein the developing state comprises one or more high quality mode settings, a high performance setting, an Alf test setting, and a map with high frequency content. The computing device of claim 1, wherein the computing device is further configured to generate a back-end shutter coverage that represents which multiple samples of each of the super-sample clusters are covered by the drawing primitive. An arithmetic device according to claim 4, further comprising a field resolver operating unit configured to test each of the plurality of samples covered by a drawing primitive according to the back-end shutter coverage z-type test The drawing primitives are generated to produce a z-type test value. The computing device of claim 5, wherein the field resolver operating unit is further configured to compress a z-type test value of a portion of a z-type buffer that intersects each of the drawing primitives . An arithmetic device according to claim 1, wherein the number of supersample clusters for each pixel of the first mapping primitive for the anti-frequency overlap is different from that for the second mapping primitive for the anti-frequency overlapping cut The number of supersample clusters per pixel. The computing device of claim 1, wherein the number of multiple passes of each composite anti-aliasing pixel for generating a cross-cut primitive does not include by not having the drawing primitive covered Any supersample cluster of at least one multiple sample. The computing device of claim 1, wherein the computing device is further configured to: by calculating a shading value of only one of the plurality of samples in each of the supersample clusters, and copying the shading Other multiple samples within the same supersample cluster to shade the drawing primitive. The computing device of claim 1, wherein the computing device is further configured to calculate a shading value of the first supersample cluster of the supersample clusters by using: in the first supersample cluster The position of the first plurality of samples; using one of the geometric centroids of one of the plurality of samples within the first supersample cluster, the multiple samples being covered by the drawing primitive; or using an approximate centroid, It is a multiple sample within a first supersample cluster that is covered by a drawing primitive and that is closest to the geometric centroid of the first supersample cluster.