TWI425287B - Gate driving module used on liquid crystal display and liquid crystal display - Google Patents
Gate driving module used on liquid crystal display and liquid crystal display Download PDFInfo
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本發明係揭露一種用於液晶顯示器之閘極線驅動模組與相關之液晶顯示器，尤指一種以時脈訊號源來當作高準位閘極電源之閘極線驅動模組與液晶顯示器。 The invention discloses a gate line driving module for a liquid crystal display and a related liquid crystal display, in particular to a gate line driving module and a liquid crystal display which are used as a high level gate power source by a clock signal source.
請參閱第1圖，其為一般薄膜電晶體液晶顯示器100之示意圖。如第1圖所示，薄膜電晶體液晶顯示器100係包含一液晶面板110、一閘極線驅動電路(gate Line Driver)120、與複數資料線驅動電路(Data Line Driver)130、140、150。閘極線驅動電路120與資料線驅動電路130、140、150係用來驅動液晶面板110上對應的薄膜電晶體進行顯示。為了降低生產薄膜電晶體液晶顯示器的成本，將閘極線驅動電路與液晶面板在同一製程下製作於玻璃基板上是一種正在被考慮的設計方向；藉由這樣的設計，可以節省液晶顯示器另外設置閘極線驅動電路的積體電路成本與面積。 Please refer to FIG. 1 , which is a schematic diagram of a general thin film transistor liquid crystal display 100 . As shown in FIG. 1, the thin film transistor liquid crystal display 100 includes a liquid crystal panel 110, a gate line driver 120, and a plurality of data line drivers 130, 140, and 150. The gate line driving circuit 120 and the data line driving circuits 130, 140, and 150 are used to drive the corresponding thin film transistors on the liquid crystal panel 110 for display. In order to reduce the cost of producing a thin film transistor liquid crystal display, the gate line driving circuit and the liquid crystal panel are fabricated on the glass substrate in the same process, which is a design direction being considered; by such a design, the liquid crystal display can be saved separately. The cost and area of the integrated circuit of the gate line driver circuit.
然而，將閘極線驅動電路以非晶矽製程製作於玻璃基板上，會受到閘極線驅動電路僅能以N型薄膜電晶體(N-type Thin Film Transistor，NTFT)實施的限制。如此一來，必須使得閘極線驅動電路的高準位閘極電源持續被供應，方可正確的判斷出內部開關的開關狀態。然而，由於非晶矽本身的電子移動率(Mobility)偏低，閘極線驅動電路所使用之N型薄膜電晶體的W/L值(亦即寬度/長度之值)必須較高來彌補非晶矽的低電子移動率；但如此一來，閘極線驅動電路的內部寄生電容會加大，使得閘極線驅動電路的內部訊號之間極易因為加大的寄生電容而產生互耦現 象(Coupling)，並進而使得閘極線驅動電路的輸出訊號產生漣波反應(Ripple Effect)而影響液晶面板的顯示品質。再者，在閘極線驅動電路中，長期受到偏壓影響的N型薄膜電晶體會產生元件特性飄移的現象，而影響閘極線驅動電路的運作。 However, the gate line driving circuit is formed on the glass substrate by an amorphous germanium process, which is limited by the implementation of the gate line driving circuit only by an N-type thin film transistor (NTFT). In this way, the high-level gate power supply of the gate line driving circuit must be continuously supplied to correctly judge the switching state of the internal switch. However, since the electron mobility (Mobility) of the amorphous germanium itself is low, the W/L value (that is, the value of the width/length) of the N-type thin film transistor used in the gate line driving circuit must be high to compensate for the non- The low electron mobility of the wafer; however, the internal parasitic capacitance of the gate line driver circuit is increased, so that the internal signals of the gate line driver circuit are easily coupled to each other due to the increased parasitic capacitance. Coupling, and in turn, causes the output signal of the gate line driving circuit to generate a Ripple Effect, which affects the display quality of the liquid crystal panel. Furthermore, in the gate line driving circuit, the N-type thin film transistor which is affected by the bias voltage for a long period of time causes a phenomenon in which the element characteristics drift, and affects the operation of the gate line driving circuit.
為了解決上述一般薄膜電晶體液晶顯示器在將閘極線驅動電路與液晶面板在同一製程下整合於玻璃基板所面臨的各種缺點與困難，本發明係揭露一種閘極線驅動模組及使用該閘極線驅動模組之液晶顯示器。 In order to solve various shortcomings and difficulties faced by the above-mentioned general thin film transistor liquid crystal display in integrating the gate line driving circuit and the liquid crystal panel in the same process, the present invention discloses a gate line driving module and using the gate A liquid crystal display of a polar drive module.
本發明係揭露一種用於液晶顯示器之閘極線驅動模組。該閘極線驅動模組包含複數個奇畫素閘極線驅動電路、複數個偶畫素閘極線驅動電路、及一輔助閘極線驅動電路。一訊號輸入源係耦接於該複數個奇畫素閘極線驅動電路之一第一級奇畫素閘極線驅動電路之一訊號輸入端或該複數個偶畫素閘極線驅動電路之一第一級偶畫素閘極線驅動電路之一訊號輸入端，該訊號輸入源亦耦接於該輔助閘極線驅動電路之一訊號回授端。一第一時脈訊號源係耦接於該複數個奇畫素閘極線驅動電路之每一奇畫素閘極線驅動電路之一第一時脈輸入端、該複數個偶畫素閘極線驅動電路之每一偶畫素閘極線驅動電路之一第一時脈輸入端、及該輔助閘極線驅動電路之一第一時脈輸入端。一第二時脈訊號源係耦接於該複數個奇畫素閘極線驅動電路之每一奇畫素閘極線驅動電路之一第二時脈輸入端、該複數個偶畫素閘極線驅動電路之每一偶畫素閘極線驅動電路之一第二時脈輸入端、及該輔助閘極線驅動電路之一第二時脈輸入端。該第一時脈訊號源與該第二時脈訊號源係為彼此之反時脈。該第一時脈訊號源與該第二時脈訊號源係用 來當作該複數個奇畫素閘極線驅動電路、該複數個偶畫素閘極線驅動電路、或該輔助閘極線驅動電路之一高準位閘極電源。該複數個奇畫素閘極線驅動電路、該複數個偶畫素閘極線驅動電路、及該輔助閘極線驅動電路所使用之電晶體係皆為N型薄膜電晶體。該閘極線驅動模組係與一液晶顯示器所包含之一液晶面板在同一非晶矽製程下所製造。 The invention discloses a gate line driving module for a liquid crystal display. The gate line driving module comprises a plurality of odd pixel gate line driving circuits, a plurality of even pixel gate driving circuits, and an auxiliary gate line driving circuit. The signal input source is coupled to one of the plurality of odd pixel gate drive circuits, the first stage of the odd pixel gate drive circuit, or the plurality of even pixel gate drive circuits. A signal input terminal of the first-stage even-gate gate driving circuit is coupled to a signal feedback terminal of the auxiliary gate line driving circuit. a first clock signal source is coupled to one of the odd-numbered pixel gate driving circuits of the plurality of odd pixel gate driving circuits, and the first clock input terminal and the plurality of even pixel gates a first clock input terminal of each of the even pixel gate drive circuits of the line drive circuit, and a first clock input terminal of the auxiliary gate line drive circuit. a second clock signal source is coupled to one of the odd pixel gate drive circuits of the plurality of odd pixel gate drive circuits, a second clock input terminal, and the plurality of even pixel gates a second clock input terminal of each of the even pixel gate drive circuits of the line drive circuit and a second clock input terminal of the auxiliary gate line drive circuit. The first clock signal source and the second clock signal source are opposite clocks of each other. The first clock signal source and the second clock signal source are used The high-level gate power supply is used as the plurality of odd-gate gate line driving circuits, the plurality of even-pixel gate driving circuits, or the auxiliary gate line driving circuit. The plurality of odd pixel gate driving circuits, the plurality of even pixel gate driving circuits, and the auxiliary crystal line driving circuit are all N-type thin film transistors. The gate line driving module is manufactured in the same amorphous germanium process as one of the liquid crystal panels included in a liquid crystal display.
本發明係揭露一種液晶顯示器。該液晶顯示器包含複數個資料線驅動電路及一液晶面板模組。該液晶面板模組包含一液晶面板及一閘極線驅動模組。該閘極線驅動模組包含複數個奇畫素閘極線驅動電路、複數個偶畫素閘極線驅動電路、及一輔助閘極線驅動電路。該閘極線驅動模組與該複數個資料線驅動電路係用來驅動液晶面板上對應的薄膜電晶體進行顯示。一訊號輸入源係耦接於該複數個奇畫素閘極線驅動電路之一第一級奇畫素閘極線驅動電路之一訊號輸入端或該複數個偶畫素閘極線驅動電路之一第一級偶畫素閘極線驅動電路之一訊號輸入端。該訊號輸入源亦耦接於該輔助閘極線驅動電路之一訊號回授端。一第一時脈訊號源係耦接於該複數個奇畫素閘極線驅動電路之每一奇畫素閘極線驅動電路之一第一時脈輸入端、該複數個偶畫素閘極線驅動電路之每一偶畫素閘極線驅動電路之一第一時脈輸入端、及該輔助閘極線驅動電路之一第一時脈輸入端。一第二時脈訊號源係耦接於該複數個奇畫素閘極線驅動電路之每一奇畫素閘極線驅動電路之一第二時脈輸入端、該複數個偶畫素閘極線驅動電路之每一偶畫素閘極線驅動電路之一第二時脈輸入端、及該輔助閘極線驅動電路之一第二時脈輸入端。該第一時脈訊號源與該第二時脈訊號源係為彼此之反時脈。該第一時脈訊號源與該第二時脈訊號源係用來當作該複數個奇畫素閘極線驅動電路、該複數個偶畫素閘極線驅動電路、或該輔助閘極線驅動電路 之一高準位閘極電源。該複數個奇畫素閘極線驅動電路、該複數個偶畫素閘極線驅動電路、及該輔助閘極線驅動電路所使用之電晶體係皆為N型薄膜電晶體。該閘極線驅動模組係與一液晶顯示器所包含之一液晶面板在同一非晶矽製程下所製造。 The invention discloses a liquid crystal display. The liquid crystal display comprises a plurality of data line driving circuits and a liquid crystal panel module. The liquid crystal panel module comprises a liquid crystal panel and a gate line driving module. The gate line driving module comprises a plurality of odd pixel gate line driving circuits, a plurality of even pixel gate driving circuits, and an auxiliary gate line driving circuit. The gate line driving module and the plurality of data line driving circuits are used to drive a corresponding thin film transistor on the liquid crystal panel for display. The signal input source is coupled to one of the plurality of odd pixel gate drive circuits, the first stage of the odd pixel gate drive circuit, or the plurality of even pixel gate drive circuits. A signal input terminal of a first-stage even pixel gate drive circuit. The signal input source is also coupled to one of the signal lines of the auxiliary gate line driving circuit. a first clock signal source is coupled to one of the odd-numbered pixel gate driving circuits of the plurality of odd pixel gate driving circuits, and the first clock input terminal and the plurality of even pixel gates a first clock input terminal of each of the even pixel gate drive circuits of the line drive circuit, and a first clock input terminal of the auxiliary gate line drive circuit. a second clock signal source is coupled to one of the odd pixel gate drive circuits of the plurality of odd pixel gate drive circuits, a second clock input terminal, and the plurality of even pixel gates a second clock input terminal of each of the even pixel gate drive circuits of the line drive circuit and a second clock input terminal of the auxiliary gate line drive circuit. The first clock signal source and the second clock signal source are opposite clocks of each other. The first clock signal source and the second clock signal source are used as the plurality of odd pixel gate line driving circuits, the plurality of even pixel gate driving circuits, or the auxiliary gate line Drive circuit One of the high level gate power supplies. The plurality of odd pixel gate driving circuits, the plurality of even pixel gate driving circuits, and the auxiliary crystal line driving circuit are all N-type thin film transistors. The gate line driving module is manufactured in the same amorphous germanium process as one of the liquid crystal panels included in a liquid crystal display.
本發明所揭露之閘極線驅動模組可以與薄膜電晶體液晶顯示器所包含之液晶面板在同一非晶矽製程下製造以完成整合，且該閘極線驅動模組所需之高準位閘極電源係以時脈輸入源所取代，而不需如先前技術來使用持續供應之高準位閘極電源；再者，本發明所揭露之閘極線驅動模組中包含之各N型薄膜電晶體皆因使用時脈訊號源來代替高準位閘極電源而不會長期的處在偏壓狀態之下，因此亦可避免如先前技術中所述之產生元件特性漂移的問題。 The gate line driving module disclosed in the present invention can be fabricated in the same amorphous germanium process as the liquid crystal panel included in the thin film transistor liquid crystal display to complete integration, and the high level gate required for the gate line driving module The pole power source is replaced by a clock input source, and the high-level gate power source continuously supplied is not required as in the prior art; further, each of the N-type films included in the gate line driving module disclosed in the present invention The transistor uses the clock signal source instead of the high-level gate power supply and does not stay under the bias state for a long period of time, so that the problem of component characteristic drift as described in the prior art can also be avoided.
請參閱第2圖，其為使用本發明所揭露之閘極線驅動模組300之一薄膜電晶體液晶顯示器200的示意圖。如第2圖所示，薄膜電晶體液晶顯示器200係包含一液晶面板模組210、及複數個資料線驅動電路230、240、250。液晶面板模組210係包含一液晶面板220與本發明所揭露之一閘極線驅動電路300，且液晶面板模組210係在同一非晶矽製程中將液晶面板220與閘極線驅動電路300製造於其中。 Please refer to FIG. 2 , which is a schematic diagram of a thin film transistor liquid crystal display 200 using the gate line driving module 300 disclosed in the present invention. As shown in FIG. 2, the thin film transistor liquid crystal display 200 includes a liquid crystal panel module 210 and a plurality of data line driving circuits 230, 240, and 250. The liquid crystal panel module 210 includes a liquid crystal panel 220 and a gate line driving circuit 300 disclosed in the present invention, and the liquid crystal panel module 210 is used to connect the liquid crystal panel 220 and the gate line driving circuit 300 in the same amorphous germanium process. Made in it.
請參閱第3圖，其為本發明所揭露之閘極線驅動模組300之概略示意圖。如第3圖所示，閘極線驅動模組300係包含一第一級閘極線驅動電路C_1、一第二級閘極線驅動電路C_2、一第三級閘極線驅動電路C_3、...、一第二百三十九級閘極線驅動電路C_239、一第二百四十級閘極 線驅動電路C_240等共240個閘極線驅動電路、及一輔助閘極線驅動電路350，其中該240個閘極線驅動電路及該輔助閘極線驅動電路350之內部元件及實體接線狀態皆相同，差別僅在於所耦接之時脈輸入源或訊號輸入源的不同而已。在第3圖中，係假設第一級閘極線驅動電路C_1與第三級閘極線驅動電路C_3等奇數級閘極線驅動電路為奇畫素閘極線驅動電路，並假設第二級閘極線驅動電路C_2與第二百四十級閘極線驅動電路C_240等閘極線驅動電路係為偶畫素閘極線驅動電路；然而，在本發明之其他實施例中，第3圖所示之奇數級閘極線驅動電路亦可為偶畫素閘極線驅動電路，且第3圖所示之偶數級閘極線驅動電路亦可為奇畫素閘極線驅動電路；換言之，在本發明所揭露之閘極線驅動模組300中，除了輔助閘極線驅動電路350以外，相鄰二級之二閘極線驅動電路其中之一必為奇畫素閘極線驅動電路，且另外一個必為偶畫素閘極線驅動電路。 Please refer to FIG. 3 , which is a schematic diagram of a gate line driving module 300 according to the present invention. As shown in FIG. 3, the gate line driving module 300 includes a first level gate line driving circuit C_1, a second level gate line driving circuit C_2, and a third level gate line driving circuit C_3. .., a 239th gate drive circuit C_239, a 224th gate A total of 240 gate line driving circuits, such as a line driving circuit C_240, and an auxiliary gate line driving circuit 350, wherein the internal components and physical wiring states of the 240 gate line driving circuits and the auxiliary gate line driving circuit 350 are The same, the difference is only the different clock source or signal input source coupled. In FIG. 3, it is assumed that the odd-level gate line driving circuits such as the first-stage gate line driving circuit C_1 and the third-stage gate line driving circuit C_3 are odd-pixel gate line driving circuits, and the second stage is assumed. The gate line driving circuit such as the gate line driving circuit C_2 and the twentieth-fourth gate line driving circuit C_240 is an even pixel gate line driving circuit; however, in other embodiments of the present invention, FIG. The odd-numbered gate line driving circuit shown may also be an even pixel gate line driving circuit, and the even-numbered gate line driving circuit shown in FIG. 3 may also be an odd-pixel gate line driving circuit; in other words, In the gate line driving module 300 disclosed in the present invention, in addition to the auxiliary gate line driving circuit 350, one of the adjacent two-level gate line driving circuits must be an odd-pixel gate line driving circuit. And the other must be an even pixel gate drive circuit.
在第3圖所示之閘極線驅動模組300中，另使用四種不同的訊號源或電源，包含一輸入訊號源STV、一低準位閘極電源VGL、一正時脈訊號源CLK、及一負時脈訊號源CLKB。 In the gate line driving module 300 shown in FIG. 3, four different signal sources or power sources are used, including an input signal source STV, a low level gate power source VGL, and a positive clock signal source CLK. And a negative clock signal source CLKB.
輸入訊號源STV係為外部所輸入之一起始驅動訊號，並直接輸入於第一級閘極線驅動電路C_1之一訊號輸入端FA及輔助閘極線驅動電路350之一訊號回授端FB。 The input signal source STV is an input driving signal input from the external one, and is directly input to one of the signal input terminal FA of the first-level gate line driving circuit C_1 and the signal feedback terminal FB of the auxiliary gate line driving circuit 350.
正時脈訊號源CLK係耦接於奇畫素閘極線驅動電路C_1、C_3、...、C_239之一正時脈輸入端CLK’、偶畫素閘極線驅動電路C_2、C_4、...、C_240之一正時脈輸入端CLK’、及輔助閘極線驅動電路350之一正時脈輸入端CLK’。負時脈訊號源CLKB係耦接於奇畫素閘極線驅動電路C_1、C_3、...、C_239之一負時脈輸入端CLKB’、偶畫素閘極線驅動電路C_2、C_4、...、C_240之一負時脈輸入 端CLKB’、及輔助閘極線驅動電路350之一負時脈輸入端CLKB’。正時脈訊號源CLK與負時脈訊號源CLKB係為彼此之反時脈，亦即兩者之間的相位差係為180度。請注意，正時脈訊號源CLK與負時脈訊號源CKLB之高準位皆與先前技術中所使用之高準位閘極線電源之準位相近，故可作為啟動閘極線驅動模組300所包含之各閘極線驅動電路之用。 The positive clock signal source CLK is coupled to one of the odd pixel gate drive circuits C_1, C_3, ..., C_239, a positive clock input terminal CLK', and an even pixel gate drive circuit C_2, C_4, . .., one of the C_240 positive clock input terminals CLK', and one of the auxiliary gate line driving circuits 350 is a positive clock input terminal CLK'. The negative clock signal source CLKB is coupled to one of the odd pixel gate drive circuits C_1, C_3, ..., C_239, one of the negative clock input terminals CLKB', and the even pixel gate drive circuit C_2, C_4, . .., C_240 one negative clock input The terminal CLKB' and one of the auxiliary gate line driving circuits 350 have a negative clock input terminal CLKB'. The positive clock signal source CLK and the negative clock signal source CLKB are opposite clocks of each other, that is, the phase difference between the two is 180 degrees. Please note that the high level of the positive clock signal source CLK and the negative clock signal source CKLB are similar to those of the high-level gate line power source used in the prior art, so it can be used as the startup gate line driver module. 300 included in each gate line drive circuit.
低準位閘極電源VGL係耦接於奇畫素閘極線驅動電路C_1、C_3、...、C_239之一低準位閘極電源輸入端VGL’、偶畫素閘極線驅動電路C_2、C_4、...、C_240之一低準位閘極電源輸入端VGL’及輔助閘極線驅動電路350之一低準位閘極電源輸入端VGL’。 The low-level gate power supply VGL is coupled to one of the odd-gate gate drive circuits C_1, C_3, ..., C_239, a low-position gate power input terminal VGL', and an even-pixel gate drive circuit C_2. One of the low-level gate power input terminal VGL' and one of the auxiliary gate line driver circuit 350, C_4, ..., C_240, is a low-level gate power input terminal VGL'.
除此以外，閘極線驅動模組300所包含之各閘極線驅動電路之間係採用前饋與回授並用之訊號輸出入架構；除了第一級閘極線驅動電路C_1或輔助閘極線驅動電路350以外的每一級閘極線驅動電路之一訊號輸入端FA皆耦接於其上一級閘極線驅動電路之一訊號輸出端Output，且該每一級閘極線驅動電路之一訊號輸出端Output皆耦接於其前一級閘極線驅動電路之一訊號回授端FB，使得該每一級閘極線驅動電路可將其輸出訊號前饋至其下一級閘極線驅動電路並回授至其前一級閘極線驅動電路。然而，由於第一級閘極線驅動電路C_1並沒有上一級閘極線驅動電路，故第一級閘極線驅動電路C_1之輸出訊號並不需要回授給其不存在之上一級閘極線驅動電路，而僅將該輸出訊號需前饋給其下一級閘極線驅動電路C_2即可。 In addition, the gate line driving circuit included in the gate line driving module 300 adopts a signal input and output structure for feeding forward and feedback together; except for the first stage gate line driving circuit C_1 or the auxiliary gate One of the signal input terminals FA of each stage of the gate drive circuit other than the line drive circuit 350 is coupled to one of the signal output terminals of the upper gate drive circuit, and one of the gate drive circuits of each stage The output terminal is coupled to one of the signal driving circuits FB of the front-level gate driving circuit, so that each of the gate driving circuits can feed its output signal to its lower-level gate driving circuit and return Granted to its previous level gate drive circuit. However, since the first-stage gate line driving circuit C_1 does not have the upper-level gate line driving circuit, the output signal of the first-stage gate line driving circuit C_1 does not need to be fed back to the upper-level gate line. The driving circuit only needs to feed forward the output signal to the next-stage gate line driving circuit C_2.
請參閱第4圖，其為用來實施第3圖所示之每一奇畫素閘極線驅動電路之一奇畫素閘極線驅動電路C_Odd之示意圖，換言之，閘極線驅動電路C_Odd係可為第3圖所示之奇畫素閘極線驅動電路C_1、C_3、...、C_239之其中一 個。如第4圖所示，閘極線驅動電路C_Odd係包含一第一N型薄膜電晶體M1、一第二N型薄膜電晶體M2、一第三N型薄膜電晶體M3、一第四N型薄膜電晶體M4、一第五N型薄膜電晶體M5、一第六N型薄膜電晶體M6、一第七N型薄膜電晶體M7、一第八N型薄膜電晶體M8、及一電容C1。第一N型薄膜電晶體M1之閘極係耦接於第一N型薄膜電晶體M1之汲極。第二N型薄膜電晶體M2之汲極係耦接於第一N型薄膜電晶體M1之源極。第三N型薄膜電晶體M3之閘極係耦接於第三N型薄膜電晶體M3之汲極。第三N型薄膜電晶體M3之源極係耦接於第二N型薄膜電晶體M2之閘極。第四N型薄膜電晶體M4之汲極係耦接於第三N型薄膜電晶體M3之源極。第五N型薄膜電晶體M5之源極係耦接於第二N型薄膜電晶體M2之閘極。第六N型薄膜電晶體M6之閘極係耦接於第一N型薄膜電晶體M1之源極。第六N型薄膜電晶體M6之源極係耦接於第四N型薄膜電晶體M4之閘極。第七N型薄膜電晶體M7之閘極係耦接於第二N型薄膜電晶體M2之閘極。第七N型薄膜電晶體M7之汲極係耦接於第六N型薄膜電晶體M6之源極。第八N型薄膜電晶體M8之汲極係耦接於第六N型薄膜電晶體之源極M6。電容C1之一第一端係耦接於第六N型薄膜電晶體M6之閘極。電容C1之一第二端係耦接於第六N型薄膜電晶體M6之源極。 Please refer to FIG. 4, which is a schematic diagram of a odd-pixel gate line driving circuit C_Odd for implementing each odd-pixel gate driving circuit shown in FIG. 3, in other words, a gate line driving circuit C_Odd. It can be one of the odd pixel gate drive circuits C_1, C_3, ..., C_239 shown in Fig. 3. One. As shown in FIG. 4, the gate line driving circuit C_Odd includes a first N-type thin film transistor M1, a second N-type thin film transistor M2, a third N-type thin film transistor M3, and a fourth N-type. The thin film transistor M4, a fifth N-type thin film transistor M5, a sixth N-type thin film transistor M6, a seventh N-type thin film transistor M7, an eighth N-type thin film transistor M8, and a capacitor C1. The gate of the first N-type thin film transistor M1 is coupled to the drain of the first N-type thin film transistor M1. The drain of the second N-type thin film transistor M2 is coupled to the source of the first N-type thin film transistor M1. The gate of the third N-type thin film transistor M3 is coupled to the drain of the third N-type thin film transistor M3. The source of the third N-type thin film transistor M3 is coupled to the gate of the second N-type thin film transistor M2. The drain of the fourth N-type thin film transistor M4 is coupled to the source of the third N-type thin film transistor M3. The source of the fifth N-type thin film transistor M5 is coupled to the gate of the second N-type thin film transistor M2. The gate of the sixth N-type thin film transistor M6 is coupled to the source of the first N-type thin film transistor M1. The source of the sixth N-type thin film transistor M6 is coupled to the gate of the fourth N-type thin film transistor M4. The gate of the seventh N-type thin film transistor M7 is coupled to the gate of the second N-type thin film transistor M2. The drain of the seventh N-type thin film transistor M7 is coupled to the source of the sixth N-type thin film transistor M6. The drain of the eighth N-type thin film transistor M8 is coupled to the source M6 of the sixth N-type thin film transistor. The first end of the capacitor C1 is coupled to the gate of the sixth N-type thin film transistor M6. The second end of the capacitor C1 is coupled to the source of the sixth N-type thin film transistor M6.
當第4圖所示之奇畫素閘極線驅動電路C_Odd係為閘極線驅動電路C_1時，輸入訊號源STV係耦接於第一N型薄膜電晶體M1之汲極；但是當第4圖所示之電路係為第一級以外之其他級奇畫素閘極線驅動電路(例如C_3)時，耦接於第一N型薄膜電晶體M1之汲極的係為其上一級偶畫素閘極線驅動電路(例如C_2)之輸出訊號端Output；換言之，在每一奇畫素閘極線驅動電路中，第一N型薄膜電晶體M1之汲極係耦接於該奇畫素閘極線驅動電 路之訊號輸入端FA。 When the odd pixel gate driving circuit C_Odd shown in FIG. 4 is the gate line driving circuit C_1, the input signal source STV is coupled to the drain of the first N-type thin film transistor M1; When the circuit shown in the figure is a other level of odd-gate gate driving circuit (for example, C_3) other than the first stage, the system coupled to the first N-type thin film transistor M1 has its upper level evenly drawn. The output signal terminal of the prime gate drive circuit (for example, C_2); in other words, in each odd pixel gate drive circuit, the drain of the first N-type thin film transistor M1 is coupled to the odd pixel Gate line drive The signal input terminal of the road is FA.
在第4圖所示之奇畫素閘極線驅動電路C_Odd中，正時脈輸入端CLK’係耦接於第三N型薄膜電晶體M3之汲極及第六N型薄膜電晶體M6之汲極，且負時脈輸入端CLKB’係耦接於第五N型薄膜電晶體M5之閘極及第八N型薄膜電晶體M8之閘極。 In the odd-pixel gate driving circuit C_Odd shown in FIG. 4, the positive clock input terminal CLK' is coupled to the drain of the third N-type thin film transistor M3 and the sixth N-type thin film transistor M6. The drain and the negative clock input terminal CLKB' are coupled to the gate of the fifth N-type thin film transistor M5 and the gate of the eighth N-type thin film transistor M8.
在第4圖所示之奇畫素閘極線驅動電路C_Odd中，低準位閘極電源輸入端VGL’係耦接於第二N型薄膜電晶體M2之源極、第四N型薄膜電晶體M4之源極、第七N型薄膜電晶體M7之源極、及第八N型薄膜電晶體M8之源極。 In the odd-gate gate driving circuit C_Odd shown in FIG. 4, the low-level gate power input terminal VGL' is coupled to the source of the second N-type thin film transistor M2, and the fourth N-type thin film is electrically connected. The source of the crystal M4, the source of the seventh N-type thin film transistor M7, and the source of the eighth N-type thin film transistor M8.
在第4圖所示之奇畫素閘極線驅動電路C_Odd中，其訊號輸出端Output係耦接於第八N型薄膜電晶體M8之汲極，且其訊號回授端FB係耦接於第五N型薄膜電晶體M5之汲極。 In the odd-pixel gate driving circuit C_Odd shown in FIG. 4, the signal output terminal is coupled to the drain of the eighth N-type thin film transistor M8, and the signal feedback terminal FB is coupled to The drain of the fifth N-type thin film transistor M5.
請參閱第5圖，其為用來實施第3圖所示之每一偶畫素閘極線驅動電路之一偶畫素閘極線驅動電路C_Even之示意圖，換言之，閘極線驅動電路C_Even係可為第3圖所示之偶畫素閘極線驅動電路C_2、...、C_240之其中一個。如第5圖所示，閘極線驅動電路C_Even係包含一第九N型薄膜電晶體M9、一第十N型薄膜電晶體M10、一第十一N型薄膜電晶體M11、一第十二N型薄膜電晶體M12、一第十三N型薄膜電晶體M13、一第十四N型薄膜電晶體M14、一第十五N型薄膜電晶體M15、一第十六N型薄膜電晶體M16、及一電容C2。請注意，第九N型薄膜電晶體M9係對應於第一N型薄膜電晶體M1、第十N型薄膜電晶體M10係對應於第二N型薄膜電晶體M2、第十一N型薄膜電晶體M11係對應於第三N型薄膜電晶體 M3、第十二N型薄膜電晶體M12係對應於第四N型薄膜電晶體M4、第十三N型薄膜電晶體M13係對應於第五N型薄膜電晶體M5、第十四N型薄膜電晶體M14係對應於第六N型薄膜電晶體M6、第十五N型薄膜電晶體M15係對應於第七N型薄膜電晶體M7、第十六N型薄膜電晶體M16係對應於第八N型薄膜電晶體M8、且電容C2係對應於電容C1；第5圖所示各元件之間的耦接關係係對應於第4圖之各對映元件之間的耦接關係，故在此不再多加贅述。需注意的是偶畫素閘極線驅動電路C_Even與奇畫素閘極線驅動電路C_Odd不同處在於正時脈訊號端CLK’與負時脈訊號端CLKB’所耦接之位置正好相反；舉例來說，在第5圖中，正時脈訊號端CLK’係耦接於第十三N型薄膜電晶體M13之閘極及及第十六N型薄膜電晶體M16之閘極，而負時脈輸入端CLKB’係耦接於第十一N型薄膜電晶體M11之汲極及第十四N型薄膜電晶體M14之汲極。 Please refer to FIG. 5 , which is a schematic diagram of an even pixel gate drive circuit C_Even for implementing each of the even pixel gate drive circuits shown in FIG. 3 , in other words, the gate drive circuit C_Even It may be one of the even pixel gate drive circuits C_2, ..., C_240 shown in FIG. As shown in FIG. 5, the gate line driving circuit C_Even includes a ninth N-type thin film transistor M9, a tenth N-type thin film transistor M10, an eleventh N-type thin film transistor M11, and a twelfth N-type thin film transistor M12, a thirteenth N-type thin film transistor M13, a fourteenth N-type thin film transistor M14, a fifteenth N-type thin film transistor M15, and a sixteenth N-type thin film transistor M16 And a capacitor C2. Please note that the ninth N-type thin film transistor M9 corresponds to the first N-type thin film transistor M1 and the tenth N-type thin film transistor M10 corresponds to the second N-type thin film transistor M2 and the eleventh N-type thin film. Crystal M11 corresponds to the third N-type thin film transistor M3, the twelfth N-type thin film transistor M12 corresponds to the fourth N-type thin film transistor M4, and the thirteenth N-type thin film transistor M13 corresponds to the fifth N-type thin film transistor M5, the fourteenth N-type film The transistor M14 corresponds to the sixth N-type thin film transistor M6, the fifteenth N-type thin film transistor M15 corresponds to the seventh N-type thin film transistor M7, and the sixteenth N-type thin film transistor M16 corresponds to the eighth The N-type thin film transistor M8 and the capacitor C2 correspond to the capacitor C1; the coupling relationship between the components shown in FIG. 5 corresponds to the coupling relationship between the respective enantiomeric elements in FIG. 4, so here No more details. It should be noted that the odd-pixel gate drive circuit C_Even is different from the odd-gate gate drive circuit C_Odd in that the positive pulse signal terminal CLK' is coupled to the negative clock signal terminal CLKB'. In Fig. 5, the positive clock signal terminal CLK' is coupled to the gate of the thirteenth N-type thin film transistor M13 and the gate of the sixteenth N-type thin film transistor M16, and negative time The pulse input terminal CLKB' is coupled to the drain of the eleventh N-type thin film transistor M11 and the drain of the fourteenth N-type thin film transistor M14.
當第二百四十級閘極線驅動電路C_240係為一奇畫素閘極線驅動電路時，輔助閘極線驅動電路350之組成及訊號源耦接關係係與第5圖所示之偶畫素閘極線驅動電路C_Even相同；而當第二百四十級閘極線驅動電路C_240係為一偶畫素閘極線驅動電路時，輔助閘極線驅動電路350之組成及訊號源耦接關係係與第4圖所示之奇畫素閘極線驅動電路C_Odd相同；故此處不再對輔助閘極線驅動電路350之組成及訊號源耦接關係加以贅述。輔助閘極線驅動電路350的作用在於透過其訊號輸入端FA承接第二百四十級閘極線驅動電路C_240之輸出訊號、將其輸出訊號回授給第二百四十級閘極線驅動電路C_240、以及將其輸出訊號前饋給第一級閘極線驅動電路C_1；換言之，輔助閘極線驅動電路350的作用在於作為一個虛擬(Dummy)(亦即實質上並未用來驅動任何閘極線)的閘極線驅動電路，以維持閘極線驅動模組300的正常運作。 When the 224th gate drive circuit C_240 is a odd pixel gate drive circuit, the composition of the auxiliary gate drive circuit 350 and the signal source coupling relationship are similar to those shown in FIG. The pixel gate drive circuit C_Even is the same; and when the 224th gate drive circuit C_240 is an even pixel gate drive circuit, the composition of the auxiliary gate drive circuit 350 and the signal source coupling The connection relationship is the same as that of the odd-gate gate line driving circuit C_Odd shown in FIG. 4; therefore, the composition of the auxiliary gate line driving circuit 350 and the signal source coupling relationship are not described herein. The function of the auxiliary gate line driving circuit 350 is to receive the output signal of the 224th level gate line driving circuit C_240 through its signal input terminal FA, and return the output signal to the 224th level gate line driver. Circuit C_240, and its output signal is fed forward to the first stage gate line driving circuit C_1; in other words, the auxiliary gate line driving circuit 350 functions as a dummy (ie, substantially not used to drive any The gate line driving circuit of the gate line) maintains the normal operation of the gate line driving module 300.
請參閱第6圖，其為以第4圖所示之奇畫素閘極線驅動電路C_Odd實施之奇畫素閘極線驅動電路C_1所包含之各節點的波形示意圖。第4圖所示之奇畫素閘極線驅動電路C_Odd的運作方式係根據第6圖來描述如下。請注意，正時脈訊號端CLK’之準位係同步於正時脈訊號源CLK之準位，負時脈訊號端CLKB’之準位係同步於負時脈訊號源CLKB之準位；準位OutPut_C_1、Output_C_2、Output_C_3係各自對應於閘極線驅動電路C_1、C_2、C_3之訊號輸出端Output的準位。 Please refer to FIG. 6 , which is a waveform diagram of each node included in the odd pixel gate driving circuit C_1 implemented by the odd pixel gate driving circuit C_Odd shown in FIG. 4 . The operation mode of the odd-pixel gate line driving circuit C_Odd shown in Fig. 4 is described below based on Fig. 6. Please note that the level of the positive pulse signal terminal CLK' is synchronized with the level of the positive clock signal source CLK, and the level of the negative clock signal terminal CLKB' is synchronized with the level of the negative clock signal source CLKB; The bits OutPut_C_1, Output_C_2, and Output_C_3 correspond to the levels of the signal output terminals Output of the gate line driving circuits C_1, C_2, and C_3, respectively.
首先，用來啟始閘極線驅動模組300之訊號輸入源STV會因一開始被觸發而於第6圖所示之週期P1出現高電位，因此會開啟第一N型薄膜電晶體M1，並使第4圖所示之節點t11的電位如第6圖所示得到一定程度的提升，且節點t11在週期P1所提升之準位係接近於正時脈訊號源CLK或負時脈訊號源CLKB之高準位。接著，第六N型薄膜電晶體M6會被節點t11所帶之高準位而開啟，再加上因為第八N型薄膜電晶體M8被位於高準位的負時脈輸入端CLKB’所開啟，使得訊號輸出端Output之準位係接近於此時正時脈輸入端CLK’或低準位閘極電源VGL的低準位，而形成如第6圖所示準位Output_C_1在週期P1時的低準位。 First, the signal input source STV used to start the gate line driving module 300 will be triggered to be high at the period P1 shown in FIG. 6 due to the initial triggering, thereby turning on the first N-type thin film transistor M1. And the potential of the node t11 shown in FIG. 4 is improved to some extent as shown in FIG. 6, and the level of the node t11 raised in the period P1 is close to the positive clock signal source CLK or the negative clock signal source. The high level of CLKB. Then, the sixth N-type thin film transistor M6 is turned on by the high level of the node t11, and the eighth N-type thin film transistor M8 is turned on by the negative clock input terminal CLKB' at the high level. So that the level of the signal output terminal is close to the low level of the positive clock input terminal CLK' or the low-level gate power supply VGL at this time, and the level Output_C_1 as shown in FIG. 6 is formed at the period P1. Low level.
接下來，當進入週期P2，且輸入訊號源STV轉變為低準位時，正時脈訊號端CLK’會轉為高準位，且負時脈訊號端CLKB’會轉為低準位，使得第五及第八N型薄膜電晶體M5、M8被關閉，且第三N型薄膜電晶體M3被開啟。此時，由於電容C1會保存住第六N型薄膜電晶體M6閘極與源極之間的電位差，因此節點t11的準位會如第6圖中週期P2所示而再次提升，且提升後之節點t11的準位會約略等於正時脈訊號端CLK’或負時脈訊號端CLKB’之高準 位的二倍。由於正時脈訊號端CLK’轉為高電位且第六N型薄膜電晶體M6的持續開啟，訊號輸出端Output亦由低準位提升至高準位。為了不讓訊號輸出端Output的準位在週期P2內降低，第二及第七N型薄膜電晶體M2、M7此時需要被關閉，亦即節點t12需要保持在低準位狀態；然而由於此時第三N型薄膜電晶體M3會被處於高準位的正時脈訊號端CLK’所開啟，且第四N型薄膜電晶體M4會被處於高準位的訊號輸出端Output透過第四N型薄膜電晶體M4之閘極所開啟，因此第四N型薄膜電晶體M4此時需要較高的導通率以儘可能的拉低節點t12之準位；為了達成這個目的，在本發明之設計上，第四N型薄膜電晶體M4之W/L值會相對大於第三N型薄膜電晶體M3之W/L值，使得大量的電流會通過第四N型薄膜電晶體M4，並因此拉低節點t12的準位而使第二及第七N型薄膜電晶體M2、M7被關閉，進而封鎖輸出訊號端Output之準位被拉低的路徑。 Next, when the period P2 is entered and the input signal source STV transitions to the low level, the positive clock signal terminal CLK' will turn to the high level, and the negative clock signal terminal CLKB' will turn to the low level, so that The fifth and eighth N-type thin film transistors M5, M8 are turned off, and the third N-type thin film transistor M3 is turned on. At this time, since the capacitance C1 stores the potential difference between the gate and the source of the sixth N-type thin film transistor M6, the level of the node t11 is raised again as shown by the period P2 in FIG. 6, and after the lifting The level of node t11 will be approximately equal to the high level of the positive clock signal terminal CLK' or the negative clock signal terminal CLKB'. Double the bit. Since the positive clock signal terminal CLK' turns to a high potential and the sixth N-type thin film transistor M6 is continuously turned on, the signal output terminal Output is also raised from the low level to the high level. In order to prevent the level of the signal output terminal from being lowered in the period P2, the second and seventh N-type thin film transistors M2 and M7 need to be turned off at this time, that is, the node t12 needs to be kept at a low level; however, due to this The third N-type thin film transistor M3 is turned on by the positive timing signal terminal CLK' at the high level, and the fourth N-type thin film transistor M4 is turned through the fourth N by the signal output terminal at the high level. The gate of the thin film transistor M4 is turned on, so the fourth N-type thin film transistor M4 needs a higher conduction rate at this time to lower the level of the node t12 as much as possible; in order to achieve this, the design of the present invention The W/L value of the fourth N-type thin film transistor M4 is relatively larger than the W/L value of the third N-type thin film transistor M3, so that a large amount of current will pass through the fourth N-type thin film transistor M4, and thus The level of the low node t12 causes the second and seventh N-type thin film transistors M2 and M7 to be turned off, thereby blocking the path in which the level of the output signal terminal Output is pulled low.
當進入週期P3時，正時脈訊號端CLK’再次轉為低準位，且負時脈訊號端CLKB’再次轉為高準位，使得第五N型薄膜電晶體M5被開啟。此時，第八N型薄膜電晶體M8會被開啟而拉低訊號輸出端Output的準位，訊號回授端FB會收到後一級偶畫素閘極線驅動電路所傳來的高準位輸出訊號，並透過被開啟之第五N型薄膜電晶體M5而拉高節點t12的電位，使得第二及第七N型薄膜電晶體M2與M7被開啟，並同時拉低節點t11及輸出訊號端Output的電位而完成一次循環。由於第一N型薄膜電晶體M1不會再接收到由訊號輸入端FA所帶來之高準位訊號而開啟，因此訊號輸出端Output的準位不會再次回到週期P2時的高準位。 When the period P3 is entered, the positive pulse signal terminal CLK' turns to the low level again, and the negative clock signal terminal CLKB' turns to the high level again, so that the fifth N-type thin film transistor M5 is turned on. At this time, the eighth N-type thin film transistor M8 is turned on to pull down the level of the signal output terminal Output, and the signal feedback terminal FB receives the high level transmitted from the rear-stage even pixel gate drive circuit. Outputting a signal and pulling the potential of the node t12 through the fifth N-type thin film transistor M5 that is turned on, so that the second and seventh N-type thin film transistors M2 and M7 are turned on, and simultaneously lowering the node t11 and outputting the signal Complete the cycle by the potential of the terminal Output. Since the first N-type thin film transistor M1 is no longer received by the high-level signal brought by the signal input terminal FA, the level of the signal output terminal Output does not return to the high level at the time of the period P2. .
第5圖所示之偶畫素閘極線驅動電路C_Even與第4圖所示之奇畫素閘極線驅動電路C_Odd的運作方式完全相 同，兩者之差異僅在所輸入之正時脈訊號源CLK’與負時脈訊號源CLKB’連接位置正好相反而已，且在此僅簡述第5圖所示之偶畫素閘極線驅動電路C_Even的運作方式，而不就之前已敘述過之部分重複敘述。假設在第6圖所示之週期P2，訊號輸入端FA接收了從上一級奇畫素閘極線驅動電路所傳來的輸出訊號而開啟了第九N型薄膜電晶體M9，並使第5圖所示之節點t11的電位得到提升。接著，第十四N型薄膜電晶體M14會被節點t11所帶之高準位而開啟，再加上因為第十六N型薄膜電晶體M16被位於高準位的正時脈輸入端CLK’所開啟，使得訊號輸出端Output之準位係接近於此時負時脈輸入端CLKB’或低準位閘極電源VGL的低準位。 The even pixel gate drive circuit C_Even shown in Fig. 5 is completely identical to the odd pixel gate drive circuit C_Odd shown in Fig. 4. Similarly, the difference between the two is only opposite to the position where the input positive clock signal source CLK' is connected to the negative clock signal source CLKB', and only the even pixel gate line shown in FIG. 5 is briefly described here. The mode of operation of the drive circuit C_Even is not repeated as previously described. Assume that in the period P2 shown in FIG. 6, the signal input terminal FA receives the output signal from the upper-order odd-pixel gate driving circuit and turns on the ninth N-type thin film transistor M9, and turns on the fifth The potential of the node t11 shown in the figure is improved. Then, the fourteenth N-type thin film transistor M14 is turned on by the high level of the node t11, and the sixteenth N-type thin film transistor M16 is placed at the high level positive clock input terminal CLK'. When turned on, the level of the signal output terminal is close to the low level of the negative clock input terminal CLKB' or the low level gate power supply VGL.
接下來，當進入週期P3，且訊號輸入端FA轉變為低準位時，正時脈訊號端CLK’會轉為低準位，且負時脈訊號端CLKB’會轉為高準位，使得第十三及第十六N型薄膜電晶體M13、M16被關閉，且第十一N型薄膜電晶體M11被開啟。此時，由於電容C2會保存住第十四N型薄膜電晶體M14閘極與源極之間的電位差，因此節點t11的準位會再次提升，且提升後之節點t11的準位會同樣約略等於正時脈訊號端CLK’或負時脈訊號端CLKB’之高準位的二倍。由於負時脈訊號端CLKB’轉為高電位且第十四N型薄膜電晶體M14的持續開啟，訊號輸出端Output亦由低準位提升至高準位。為了不讓訊號輸出端Output的準位在週期P3內降低，第十及第十五N型薄膜電晶體M10、M15此時需要被關閉，亦即節點t12需要保持在低準位狀態；然而由於此時第十一N型薄膜電晶體M11會被處於高準位的負時脈訊號端CLKB’所開啟，且第十二N型薄膜電晶體M12會被處於高準位的訊號輸出端Output透過第十二N型薄膜電晶體M12之閘極所開啟，因此第十二N型薄膜電晶體M12此時需要較高的導通率以儘可能的拉低節點t12之準 位。同理，為了達成這個目的，第十二N型薄膜電晶體M12之W/L值會相對大於第十一N型薄膜電晶體M11之W/L值，使得大量的電流會通過第十二N型薄膜電晶體M12，並因此拉低節點t12的準位而使第十及第十五N型薄膜電晶體M10及M15被關閉，進而封鎖輸出訊號端Output之準位被拉低的路徑。 Next, when the period P3 is entered and the signal input terminal FA changes to the low level, the positive clock signal terminal CLK' will turn to the low level, and the negative clock signal terminal CLKB' will turn to the high level, so that The thirteenth and sixteenth N-type thin film transistors M13, M16 are turned off, and the eleventh N-type thin film transistor M11 is turned on. At this time, since the capacitor C2 stores the potential difference between the gate and the source of the fourteenth N-type thin film transistor M14, the level of the node t11 is raised again, and the level of the node t11 after the boost is similarly approximated. It is equal to twice the high level of the positive clock signal terminal CLK' or the negative clock signal terminal CLKB'. Since the negative clock signal terminal CLKB' turns to a high potential and the fourteenth N-type thin film transistor M14 is continuously turned on, the signal output terminal Output is also raised from the low level to the high level. In order to prevent the level of the signal output terminal from being lowered in the period P3, the tenth and fifteenth N-type thin film transistors M10 and M15 need to be turned off at this time, that is, the node t12 needs to be kept at a low level; however, At this time, the eleventh N-type thin film transistor M11 is turned on by the negative clock signal terminal CLKB' at the high level, and the twelfth N-type thin film transistor M12 is transmitted through the signal output terminal of the high level. The gate of the twelfth N-type thin film transistor M12 is turned on, so the twelfth N-type thin film transistor M12 needs a high conduction rate at this time to pull the node t12 as low as possible. Bit. Similarly, in order to achieve this, the W/L value of the twelfth N-type thin film transistor M12 is relatively larger than the W/L value of the eleventh N-type thin film transistor M11, so that a large amount of current will pass through the twelfth N. The thin film transistor M12, and thus the lower level of the node t12, causes the tenth and fifteenth N-type thin film transistors M10 and M15 to be turned off, thereby blocking the path in which the level of the output signal output is pulled low.
當進入週期P4時，正時脈訊號端CLK’再次轉為高準位，且負時脈訊號端CLKB’再次轉為低準位，使得第十三N型薄膜電晶體M13被開啟。此時，第十六N型薄膜電晶體M16會被開啟而拉低訊號輸出端Output的準位，訊號回授端FB會收到後一級奇畫素閘極線驅動電路所傳來的高準位輸出訊號，並透過被開啟之第十三N型薄膜電晶體M13而拉高節點t12的電位，使得第十及第十五N型薄膜電晶體M10與M15被開啟，並同時拉低節點t11及輸出訊號端Output的電位而完成一次循環。由於第九N型薄膜電晶體M9不會再接收到由訊號輸入端FA所帶來之高準位訊號而開啟，因此訊號輸出端Output的準位不會再次回到高準位。 When the period P4 is entered, the positive clock signal terminal CLK' turns to the high level again, and the negative clock signal terminal CLKB' turns to the low level again, so that the thirteenth N-type thin film transistor M13 is turned on. At this time, the sixteenth N-type thin film transistor M16 will be turned on to pull down the level of the signal output terminal Output, and the signal feedback terminal FB will receive the high-precision transmitted from the latter-stage odd-pixel gate drive circuit. And outputting the signal, and pulling the potential of the node t12 through the thirteenth N-type thin film transistor M13 that is turned on, so that the tenth and fifteenth N-type thin film transistors M10 and M15 are turned on, and simultaneously lowering the node t11 And output the signal terminal output potential to complete a cycle. Since the ninth N-type thin film transistor M9 is no longer received by the high level signal brought by the signal input terminal FA, the level of the signal output terminal Output does not return to the high level again.
上述第4圖及第6圖中所述之閘極線驅動電路的運作方式會繼續在閘極線驅動模組300中所包含之各奇畫素閘極線驅動電路及各偶畫素閘極線驅動電路繼續以遞移(Iterative)方式持續驅動各自對應之閘極線，直至所有閘極線驅動單元所對應之閘極線皆被驅動過一次為止。需要說明的是，當上述之遞移(Iteration)傳遞至輔助閘極線驅動電路350時，輔助閘極線驅動電路350會再次將其輸出訊號前饋給第一級閘極線驅動電路C_1之訊號輸入端FA，以重新啟始該循環。 The operation mode of the gate line driving circuit described in the above FIG. 4 and FIG. 6 will continue with the odd pixel gate line driving circuits and the even pixel gates included in the gate line driving module 300. The line driver circuit continues to drive the respective gate lines in an Iterative manner until the gate lines corresponding to all of the gate line driver units are driven once. It should be noted that when the above-mentioned iteration is transmitted to the auxiliary gate line driving circuit 350, the auxiliary gate line driving circuit 350 feeds forward its output signal to the first-stage gate line driving circuit C_1 again. The signal input terminal FA is used to restart the cycle.
觀察第6圖所示之波形示意圖可知，在閘極線驅動模組300所包含之任一奇畫素閘極線驅動電路C_Odd、任一 偶畫素閘極線驅動電路C_Even、或輔助閘極線驅動電路350中，沒有任何一個N型薄膜電晶體會持續處於被開啟的狀態，因此也不會產生如先前技術中所述因持續被偏壓影響而造成元件特性漂移的狀況，因而克服了該缺點。除此以外，先前技術在每一閘極線驅動電路元件中約略使用十三個以上之電晶體來當作元件，而本發明所揭露之每一閘極線驅動電路中僅使用了八個N型薄膜電晶體與一個電容，因此在液晶面板與閘極線驅動電路的整合上亦可有效達成縮小面積的效果。再者，由於本發明所揭露之閘極線驅動模組所包含之各閘極線驅動電路係以時脈訊號源來供給其電源，因此亦不需如先前技術般使用持續供應的高準位閘極線電源。 Observing the waveform diagram shown in FIG. 6, it can be seen that any odd pixel gate line driving circuit C_Odd included in the gate line driving module 300, In the even pixel gate driving circuit C_Even or the auxiliary gate line driving circuit 350, none of the N-type thin film transistors will continue to be in an open state, and thus will not be continuously sustained as described in the prior art. This disadvantage is overcome by the fact that the bias voltage affects the drift of the component characteristics. In addition, the prior art uses approximately thirteen or more transistors in each gate line driving circuit component as components, and only eight Ns are used in each gate line driving circuit disclosed in the present invention. The thin film transistor and a capacitor can effectively achieve the effect of reducing the area in the integration of the liquid crystal panel and the gate line driving circuit. Furthermore, since the gate line driving circuits included in the gate line driving module disclosed in the present invention supply the power source by the clock signal source, there is no need to use the high level of continuous supply as in the prior art. Gate line power supply.
綜上所述，本發明確已符合發明專利之要件，爰依法提出專利申請。惟，以上所述者僅為本發明之較佳實施方式，本發明之範圍並不以上述實施例為限，該舉凡熟悉本案技藝之人士援依本發明之精神所作之等效修飾或變化，皆應涵蓋於以下申請專利範圍內。 In summary, the present invention has indeed met the requirements of the invention patent, and has filed a patent application according to law. However, the above description is only the preferred embodiment of the present invention, and the scope of the present invention is not limited to the above-described embodiments, and those skilled in the art will be able to make equivalent modifications or variations in accordance with the spirit of the present invention. All should be covered by the following patent application.
100、200‧‧‧液晶顯示器 100, 200‧‧‧ liquid crystal display
110、220‧‧‧液晶面板 110, 220‧‧‧ LCD panel
120、300、C_1、C_2、C_3、...、C_239、C_240、C_Odd、C_Even‧‧‧閘極線驅動電路 120, 300, C_1, C_2, C_3, ..., C_239, C_240, C_Odd, C_Even‧‧‧ gate drive circuit
130、140、150、230、240、250‧‧‧資料線驅動電路 130, 140, 150, 230, 240, 250‧‧‧ data line drive circuit
210‧‧‧液晶面板模組 210‧‧‧LCD panel module
350‧‧‧輔助閘極線驅動電路 350‧‧‧Auxiliary gate line driver circuit
STV‧‧‧輸入訊號源 STV‧‧‧ input signal source
VGL‧‧‧低準位閘極電源 VGL‧‧‧ low level gate power supply
CLK‧‧‧正時脈訊號源 CLK‧‧‧ positive clock signal source
CLKB‧‧‧負時脈訊號源 CLKB‧‧‧ negative clock signal source
VGL’‧‧‧低準位閘極電源輸入端 VGL’‧‧‧ low-level gate power input
CLK’‧‧‧正時脈訊號端 CLK’‧‧‧ positive clock signal end
CLKB’‧‧‧負時脈訊號端 CLKB’‧‧‧n negative clock signal end
FA‧‧‧訊號輸入端 FA‧‧‧ signal input
FB‧‧‧訊號回授端 FB‧‧‧ signal feedback end
Output‧‧‧訊號輸出端 Output‧‧‧ signal output
Output_C_1、Output_C_2、Output_C_3、...、Output_C_239、Output_C_240‧‧‧輸出訊號 Output_C_1, Output_C_2, Output_C_3, ..., Output_C_239, Output_C_240‧‧‧ Output signals
M1-M16‧‧‧N型薄膜電晶體 M1-M16‧‧‧N type thin film transistor
t11、t12‧‧‧節點 T11, t12‧‧‧ nodes
C1、C2‧‧‧電容 C1, C2‧‧‧ capacitor
P1、P2、P3、P4‧‧‧週期 P1, P2, P3, P4‧‧ cycle
第1圖為一般薄膜電晶體液晶顯示器之示意圖。 Figure 1 is a schematic view of a general thin film transistor liquid crystal display.
第2圖為使用本發明所揭露之閘極線驅動模組之一薄膜電晶體液晶顯示器的示意圖。 FIG. 2 is a schematic diagram of a thin film transistor liquid crystal display using one of the gate line driving modules disclosed in the present invention.
第3圖為本發明所揭露之閘極線驅動模組之概略示意圖。 FIG. 3 is a schematic diagram of the gate line driving module disclosed in the present invention.
第4圖為用來實施第3圖所示之每一奇畫素閘極線驅動電路之一奇畫素閘極線驅動電路之示意圖。 Fig. 4 is a schematic view showing an odd pixel gate line driving circuit for implementing each of the odd pixel gate line driving circuits shown in Fig. 3.
第5圖為用來實施第3圖所示之每一偶畫素閘極線驅動電路之一偶畫素閘極線驅動電路之示意圖。 FIG. 5 is a schematic diagram of an even pixel gate drive circuit for implementing each of the even pixel gate drive circuits shown in FIG. 3.
第6圖為以第4圖所示之奇畫素閘極線驅動電路實施之奇畫素閘極線驅動電路所包含之各節點的波形示意圖。 Fig. 6 is a waveform diagram showing the nodes included in the odd-pixel gate driving circuit implemented by the odd-pixel gate driving circuit shown in Fig. 4.
300、C_1、C_2、C_3、...、C_239、C_240、C_Odd、C_Even‧‧‧閘極線驅動電路 300, C_1, C_2, C_3, ..., C_239, C_240, C_Odd, C_Even‧‧‧ gate drive circuit
300、C_1、C_2、C_3、...、C_239、C_240、C_Odd、C_Even‧‧‧閘極線驅動電路 300, C_1, C_2, C_3, ..., C_239, C_240, C_Odd, C_Even‧‧‧ gate drive circuit
130、140、150、230、240、250‧‧‧資料線驅動電路 130, 140, 150, 230, 240, 250‧‧‧ data line drive circuit
350‧‧‧輔助閘極線驅動電路 350‧‧‧Auxiliary gate line driver circuit
STV‧‧‧輸入訊號源 STV‧‧‧ input signal source
VGL‧‧‧低準位閘極電源 VGL‧‧‧ low level gate power supply
CLK‧‧‧正時脈訊號源 CLK‧‧‧ positive clock signal source
CLKB‧‧‧負時脈訊號源 CLKB‧‧‧ negative clock signal source
VGL’‧‧‧低準位閘極電源輸入端 VGL’‧‧‧ low-level gate power input
CLK’‧‧‧正時脈訊號端 CLK’‧‧‧ positive clock signal end
CLKB’‧‧‧負時脈訊號端 CLKB’‧‧‧n negative clock signal end
FA‧‧‧訊號輸入端 FA‧‧‧ signal input
FB‧‧‧訊號回授端 FB‧‧‧ signal feedback end
Output‧‧‧訊號輸出端 Output‧‧‧ signal output
Output_C_1、Output_C_2、Output_C_3、...、Output_C_239、Output_C_240‧‧‧輸出訊號 Output_C_1, Output_C_2, Output_C_3, ..., Output_C_239, Output_C_240‧‧‧ Output signals
Claims (22)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW98125039A TWI425287B (en) | 2009-07-24 | 2009-07-24 | Gate driving module used on liquid crystal display and liquid crystal display |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW98125039A TWI425287B (en) | 2009-07-24 | 2009-07-24 | Gate driving module used on liquid crystal display and liquid crystal display |
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| Publication Number | Publication Date |
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| TW201104327A TW201104327A (en) | 2011-02-01 |
| TWI425287B true TWI425287B (en) | 2014-02-01 |
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| TW98125039A TWI425287B (en) | 2009-07-24 | 2009-07-24 | Gate driving module used on liquid crystal display and liquid crystal display |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1526141A (en) * | 2001-02-13 | 2004-09-01 | 三星电子株式会社 | Shift register and liquid crystal display using the same |
| TW200625261A (en) * | 2004-10-01 | 2006-07-16 | Samsung Electronics Co Ltd | Shift register, gate driving circuit and display panel having the same, and method thereof |
| US7106292B2 (en) * | 2002-06-10 | 2006-09-12 | Samsung Electronics Co., Ltd. | Shift register, liquid crystal display device having the shift register and method of driving scan lines using the same |
| TW200802270A (en) * | 2006-05-25 | 2008-01-01 | Mitsubishi Electric Corp | Shift register circuit and image display apparatus equipped with the same |
| TW200915290A (en) * | 2007-07-24 | 2009-04-01 | Koninkl Philips Electronics Nv | A shift register circuit |
-
2009
- 2009-07-24 TW TW98125039A patent/TWI425287B/en not_active IP Right Cessation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1526141A (en) * | 2001-02-13 | 2004-09-01 | 三星电子株式会社 | Shift register and liquid crystal display using the same |
| US7106292B2 (en) * | 2002-06-10 | 2006-09-12 | Samsung Electronics Co., Ltd. | Shift register, liquid crystal display device having the shift register and method of driving scan lines using the same |
| TW200625261A (en) * | 2004-10-01 | 2006-07-16 | Samsung Electronics Co Ltd | Shift register, gate driving circuit and display panel having the same, and method thereof |
| TW200802270A (en) * | 2006-05-25 | 2008-01-01 | Mitsubishi Electric Corp | Shift register circuit and image display apparatus equipped with the same |
| TW200915290A (en) * | 2007-07-24 | 2009-04-01 | Koninkl Philips Electronics Nv | A shift register circuit |
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| TW201104327A (en) | 2011-02-01 |
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