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TWI421993B - 四方扁平無導腳之半導體封裝件及其製法及用於製造該半導體封裝件之金屬板 - Google Patents

四方扁平無導腳之半導體封裝件及其製法及用於製造該半導體封裝件之金屬板 Download PDF

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TWI421993B
TWI421993B TW099113219A TW99113219A TWI421993B TW I421993 B TWI421993 B TW I421993B TW 099113219 A TW099113219 A TW 099113219A TW 99113219 A TW99113219 A TW 99113219A TW I421993 B TWI421993 B TW I421993B
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Taiwan
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pad
crystal
bump
sectional area
cross
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TW099113219A
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TW201138038A (en
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En Min Jow
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Aptos Technology Inc
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Priority to TW099113219A priority Critical patent/TWI421993B/zh
Priority to JP2011099932A priority patent/JP5824236B2/ja
Priority to US13/095,843 priority patent/US9171740B2/en
Publication of TW201138038A publication Critical patent/TW201138038A/zh
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Publication of TWI421993B publication Critical patent/TWI421993B/zh
Priority to US14/863,436 priority patent/US9659842B2/en

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Description

四方扁平無導腳之半導體封裝件及其製法及用於製造該半導體封裝件之金屬板
本發明係有關於一種封裝結構及其製法，尤指一種四方扁平無導腳之半導體封裝件(Quad Flat Non Leaded Package,QFN)及其製法。
傳統晶片係以導線架(Lead Frame)作為晶片承載件以形成一半導體封裝件，而該導線架主要包括一晶片座及形成於該晶片座周圍之複數導腳，於該晶片座上黏接晶片，並以銲線電性連接該晶片與導腳後，再將封裝樹脂包覆該晶片、晶片座、銲線以及導腳之內段而形成該具導線架之半導體封裝件。
就積體電路技術發展而言，在半導體製程上不斷朝向積集度更高的製程演進，且高密度的構裝結構係為業者追求的目標。而晶片尺寸構裝所採用之承載器(carrier)包括：導線架(lead frame)、軟質基板(flexible substrate)或硬質基板(rigid substrate)等，由於導線架具有成本低，加工容易等特性，為電子產品常用之晶片尺寸構裝類型；其中之四方扁平無接腳構裝(QFN)為以導線架為構裝基材之晶片尺寸構裝(lead frame based CSP)，其特徵在於未設置有外導腳，即未形成有用以與外界電性連接之外導腳，而能縮小整體尺寸。
請參閱第4A圖，係美國專利第6,143,981、6,130,115、及6,198,171號所揭示之以導線架作為晶片承載件之四方扁平無導腳構裝(QFN)之剖視圖；如圖所示，係於具有引腳41之導線架40上固設晶片42，且該晶片42並藉由銲線43電性連接至該引腳41，形成封裝材44以包覆該導線架40、晶片42、及銲線43，並使該導線架40之引腳41的底面外露於該封裝材44表面，使該QFN半導體封裝結構得藉由該外露之引腳41外露表面以直接透過銲錫材料(未以圖式表示)而與外界裝置如印刷電路板(printed circuit board)之外部裝置電性連接。
惟，上述之習知導線架式結構，所能提供之輸入/輸出數量較少，無法滿足高階產品，且在切單製程後，該引腳有脫落之風險。再者，由於該外露之引腳41與封裝材44表面齊平，當該外露之引腳41上形成銲球46以與外部裝置之印刷電路板電性連接時，如第4B圖所示，該銲球46容易產生橋接(solder bridge)，而導致該引腳41之間產生橋接或短路，而造成電性連接不良的情況。
為獲得更多之輸入/輸出數量，亦有在銅箔基板上藉由蝕刻方式形成導線架，以得到更多引腳，然而，蝕刻製程步驟繁多且耗時，且不論是前述第4A圖之封裝件或以蝕刻方式得到的導線架，在填入封裝膠體時都存在溢膠之問題，導致無法佈植銲球及影響銲球與引腳之電性連接。此外，蝕刻方式形成之導線架，其結構係分離而不完整，於超音波銲接時常有脫銲的狀況。
因此，鑒於上述之問題，如何以簡化之製程提供更多的輸入/輸出數量，且避免習知之半導體封裝件之引腳脫落及封裝膠體溢膠等問題，實已成為目前亟欲解決之課題。
鑑於上述習知技術之種種缺失，本發明提供一種四方扁平無導腳之半導體封裝件，係包括：置晶墊，其中，在該置晶墊之厚度範圍內，該置晶墊之至少一橫截面面積大於其下方另一橫截面面積；複數凸銲墊，係設於該置晶墊週圍，其中，在該凸銲墊之厚度範圍內，該凸銲墊之至少一橫截面面積大於其下方另一橫截面面積，且該凸銲墊之頂面高於置晶墊之頂面；設置於該置晶墊上之晶片；銲線，電性連接該晶片及各該凸銲墊；以及封裝膠體，係包覆該置晶墊、凸銲墊、晶片及銲線，使該置晶墊及凸銲墊嵌卡於該封裝膠體中並外露出該些凸銲墊及置晶墊之底面。
為得到本發明之半導體封裝件，本發明復提供一種四方扁平無導腳之半導體封裝件之製法，係包括：準備一定義有複數置晶區之金屬板；以模具沖壓該金屬板，以於金屬板上之各該置晶區形成置晶墊，並於該置晶區外圍形成複數凸銲墊，其中，在該置晶墊及凸銲墊之厚度範圍內，該凸銲墊之至少一橫截面面積大於其下方另一橫截面面積，以及該置晶墊之至少一橫截面面積大於其下方另一橫截面面積，且該凸銲墊之底面高於置晶墊之底面；於各該置晶墊上接置晶片；以銲線電性連接該晶片與凸銲墊；於該金屬板、晶片及銲線上覆蓋封裝膠體，使該凸銲墊嵌卡於該封裝膠體中；移除該金屬板底部，使該置晶墊及各該凸銲墊彼此間隔分佈；以及切割該封裝膠體，以形成複數半導體封裝件。
於前述之製法中，該模具可包括公模、母模及複數插入件，且該母模具有複數陣列式排列之凹穴以及溝槽，係用以連通位於同一列上之凹穴，其中，該溝槽係供插入件滑設其中，使該凹穴開口面積小於凹穴底面積。
於另一實施方式中，該沖壓形成該置晶墊及凸銲墊之步驟包括以模具沖壓該金屬板以形成複數置晶墊及凸銲墊；以及壓制該置晶墊及凸銲墊頂面，俾使在該置晶墊及凸銲墊之厚度範圍內，該凸銲墊之至少一橫截面面積大於其下方另一橫截面面積，以及該置晶墊之至少一橫截面面積大於其下方另一橫截面面積。
另一方面，本發明復提供一種用於製造四方扁平無導腳之半導體封裝件之金屬板，係包括：複數凸銲墊，係一體成形於該金屬板上，且該些凸銲墊圍設出置晶區，其中，在該凸銲墊之厚度範圍內，該凸銲墊之至少一橫截面面積大於其下方另一橫截面面積；置晶墊，係位於置晶區，其中，在該置晶墊之厚度範圍內，該置晶墊之至少一橫截面面積大於其下方另一橫截面面積；以及複數孔穴，係對應形成於各該凸銲墊底面。
由上可知，本發明之半導體封裝件及其製法，係先於金屬板上沖壓出凸銲墊，接置放並電性連接晶片以及形成封裝膠體，之後才進行切單作業，可避免習知技術灌注封裝膠體時之溢膠問題，此外，本發明金屬板上之凸銲墊具有嵌卡之功能，可避免於形成封裝膠體後，凸銲墊自封裝膠體內脫落。又，凸銲墊之頂面高於置晶墊之頂面，可降低打線的高度，縮小整體封裝件之體積。本發明之半導體封裝件及製法，不僅防止溢膠及凸銲墊脫落，更具有簡化製程，提供更多的輸入/輸出數量之優點。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
並須說明的是，本說明書中所敘述之“頂面”與“底面”並非絕對之空間概念，而係隨構成要件之空間關係而變化，亦即，倒置本案圖式中所示之半導體封裝件時，“頂面”即成“底面”而“底面”即成“頂面”。故該等“頂面”、“底面”名詞之使用，係用以說明本發明所揭示之半導體封裝件中構成要件間之連結關係，使本發明所揭示之半導體封裝件在等效之範圍內具有合理之變化與替換，而非用以限定本發明之可實施範圍於一特定之態樣(Embodiment)。
第一實施例
請參閱第1A至1E”圖，係說明本發明四方扁平無導腳之半導體封裝件之製法。
如第1A圖所示，準備一定義有複數置晶區11之金屬板10，該金屬板可為銅，此外，該金屬板10上下表面可藉由電鍍形成有金屬層，其可包括選自金、鈀、銀、銅及鎳所組成群組的一種或多種材質，例如，金/鈀/鎳/鈀層依序組成或金/鎳/銅/鎳/銀、金/鎳/銅/銀、鈀/鎳/鈀、金/鎳/金或鈀/鎳/金之多層金屬其中一者所構成。
如第1B及1B’圖所示，以模具12沖壓該金屬板10，以於金屬板10上之各該置晶區11形成置晶墊19，並於該置晶區11外圍形成複數凸銲墊13，其中，在該置晶墊19及凸銲墊13之厚度h、h’範圍內，該凸銲墊13之至少一橫截面面積大於其下方另一橫截面面積，以及該置晶墊19之至少一橫截面面積大於其下方另一橫截面面積，且該凸銲墊13之底面高於置晶墊19之底面。該凸銲墊13可為鳩尾形或半鳩尾形，如第1B圖所示，該凸銲墊13為鳩尾形，在該凸銲墊13之厚度h範圍內的任意兩個橫截面，上方橫截面之面積大於下方另一橫截面之面積。又，復可包括於沖壓該金屬板之後，形成金屬層於該金屬板上下表面(未圖示)。
在實施上，該模具12包括公模121、母模122及複數插入件123，且如第1B’圖所示之母模122底視圖，該母模122具有複數陣列式排列之凹穴1221以及溝槽1222，係用以連通位於同一列上之凹穴1221，其中，該溝槽1222係供插入件123滑設其中，使該凹穴1221開口面積小於凹穴1221底面積，從而於沖壓後得到鳩尾形之凸銲墊13。
如第1C圖所示，於各該置晶墊19上接置晶片14，接著以銲線15電性連接該晶片14與凸銲墊13；之後再於該金屬板10、晶片14及銲線15上覆蓋封裝膠體16，由於鳩尾形凸銲墊13之任一橫截面之面積皆大於下方另一橫截面之面積(在本發明中，凸銲墊13內之孔穴131橫截面亦計算於凸銲墊13的橫截面)，例如頂面面積大於底面面積，俾使該凸銲墊13嵌卡於該封裝膠體16中，此外，因該凸銲墊13之底面高於置晶墊19之底面，以及凸銲墊13之頂面高於置晶墊19之頂面，可降低打線的高度，縮小整體封裝件之體積，再者，因金屬板為連續結構，可減少超音波銲接時脫銲的缺陷。又因為形成封裝膠體時，該金屬板仍為連續結構，更可防止溢膠的問題。
如第1D圖所示，以銑刀或蝕刻等方式移除該金屬板10底部，使各該該置晶墊19及凸銲墊13彼此間隔分佈。復參閱第1D’圖，不同於第1D圖中該置晶墊19及凸銲墊13底部與封裝膠體底部齊平，在移除該金屬板10底部時，由於沖壓時可設定沖壓深度，得以於移除金屬板10視需要令得到的置晶墊及凸銲墊13底面對應形成孔穴131，如第1E圖所示，該孔穴可供銲球17佈設其中，在銲球17與凸銲墊之間提供較佳的接合強度，最後切割該封裝膠體16，以形成複數半導體封裝件1。另一方面，當相鄰兩封裝單元具有共用之凸銲墊時，於執行切割步驟，可如第1E’圖所示，切割封裝膠體16及相鄰兩半導體封裝件共用的凸銲墊13，以令所得之半導體封裝件之最外圍凸銲墊13側邊外露，並與封裝膠體16側邊齊平。當然亦可如第1E圖所示，相鄰兩封裝單元不具有共用之凸銲墊13，封裝膠體16則包覆住凸銲墊13側邊。
此外，如第1E”圖所示，復可包括於移除該金屬板10後，於該封裝膠體16底面上形成防銲層18，且令該防銲層18具有複數供對應露出各該置晶墊19及凸銲墊13的防銲層開孔181。本實例中，雖以具有孔穴131之凸銲墊13做說明，但不以此態樣為限。
第二實施例
本實施例與前述製法大致相同，其差異在於不同的沖壓方式。如第2A至2C圖所示之沖壓形成該置晶墊及凸銲墊之步驟，包括先以包括上模221及下模222之模具22沖壓該金屬板20以形成複數置晶墊29及凸銲墊23；以及再次，壓制該置晶墊29及凸銲墊23頂面，俾使在該置晶墊29及凸銲墊23之厚度範圍內，即便凸銲墊23頂面並非最大的面積，仍存在至少一橫截面面積大於其下方另一橫截面面積之關係，以於形成封裝膠體後，令凸銲墊23嵌卡於於封裝膠體中，同樣地，使該置晶墊29之至少一橫截面面積大於其下方另一橫截面面積。具體而言，如第2B圖所示，係可利用另一上模221’再次壓制該置晶墊29及凸銲墊23頂面，最後脫模即可得到具有凸銲墊23之金屬板20。
第三實施例
本實施例與前述製法大致相同，其差異在於置晶墊外形。如第3A圖所示，沖壓該金屬板30之步驟復包含以模具32沖壓置晶區31形成置晶墊38，該置晶墊38由複數個凸墊381所構成，其外形可與凸銲墊33相同。同樣地，在該置晶墊38之厚度範圍內，該置晶墊38之至少一橫截面面積大於其下方另一橫截面面積。
根據前述之製法，本發明提供一種四方扁平無導腳之半導體封裝件1、3，如第1E及3C圖所示，該半導體封裝件1、3係包括：置晶墊19、38，其中，在該置晶墊19、38之厚度範圍內，該置晶墊之至少一橫截面面積大於其下方另一橫截面面積；複數凸銲墊13、33，係設於該置晶墊19、38週圍，其中，在該凸銲墊13、33之厚度範圍內，該凸銲墊13、33之至少一橫截面面積大於其下方另一橫截面面積，且該凸銲墊13、33之頂面高於置晶墊19、38之頂面；晶片14、34，係設置於該置晶墊19、38上；銲線15、35，電性連接該晶片14、34及各該凸銲墊13、33；以及封裝膠體16、36，係包覆該置晶墊19、38、凸銲墊13、33、晶片14、34及銲線15、35，使該置晶墊19、38及凸銲墊13、33嵌卡於該封裝膠體16、36中並外露出該些凸銲墊13、33及置晶墊19、38之底面。此外，該凸銲墊13、33及置晶墊19、38底面可接置有銲球17、37。
在本發明之半導體封裝件中，該凸銲墊13及置晶墊19可為如第1E圖所示之鳩尾形，或者可為半鳩尾形或其他形狀。
如第1E’圖所示，該半導體封裝件復可包括防銲層18，係形成於該封裝膠體16底面上，且該防銲層18具有複數供對應露出各該置晶墊19及凸銲墊13的防銲層開孔181。
另一方面，根據前述之製法，本發明提供一種用於製造四方扁平無導腳之半導體封裝件之金屬板，如第1C圖所示，該金屬板10係包括：複數凸銲墊13，係一體成形於該金屬板10上，且該些凸銲墊13圍設出置晶區11，其中，在該凸銲墊13之厚度範圍內，該凸銲墊13之至少一橫截面面積大於其下方另一橫截面面積；置晶墊19，係位於置晶區11，其中，在該置晶墊19之厚度範圍內，該置晶墊19之至少一橫截面面積大於其下方另一橫截面面積；以及複數孔穴131，係對應形成於各該凸銲墊13底面。
本發明之半導體封裝件及其製法，係先於金屬板上沖壓出凸銲墊，接置放並電性連接晶片以及形成封裝膠體，之後才進行切單作業，可避免習知技術灌注封裝膠體時之溢膠問題，此外，本發明金屬板上之置晶墊及凸銲墊具有嵌卡之功能，可避免於形成封裝膠體後，凸銲墊自封裝膠體內脫落，而提升可靠度。又較佳地，沖壓之方式亦可使該置晶墊高度低於凸銲墊，有利於降低封裝件之高度，縮小體積提升導熱性能，本發明之半導體封裝件及製法，不僅防止溢膠及凸銲墊脫落，更具有簡化製程，提供更多的輸入/輸出數量之優點。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
1、3．．．半導體封裝件
10、20、30．．．金屬板
11、31．．．置晶區
12、22、32．．．模具
121．．．公模
122．．．母模
123．．．插入件
1221．．．凹穴
1222．．．溝槽
13、23、33．．．凸銲墊
131．．．孔穴
14、34、42．．．晶片
15、35、43．．．銲線
16、36．．．封裝膠體
17、37、46．．．銲球
18．．．防銲層
181．．．開孔
221、221’．．．上模
222．．．下模
19、29、38．．．置晶墊
381．．．凸墊
40．．．導線架
41．．．引腳
44．．．封裝材
第1A至1E”圖係為本發明四方扁平無導腳之半導體封裝件之製法示意圖，其中，第1B’圖為第1B圖之母模的底視圖；第1D’圖為具有孔穴之半導體封裝件示意圖，第1E圖為凸銲墊與封裝膠體側邊齊平之半導體封裝件示意圖；以及第1E’圖為具有防銲層之半導體封裝件示意圖；
第2A至2C圖係為本發明形成凸銲墊之另一製法示意圖；
第3A至3C圖係為本發明另一沖壓形成置晶墊之製法示意圖，其中，第3C圖係具有置晶墊之半導體封裝件示意圖；以及
第4A及4B圖係習知以導線架作為晶片承載件之四方扁平無接腳構裝(QFN)之剖視圖。
1．．．半導體封裝件
11．．．置晶區
13．．．凸銲墊
14．．．晶片
15．．．銲線
16．．．封裝膠體

Claims (12)

  1. 一種四方扁平無導腳之半導體封裝件，係包括：置晶墊，其中，在該置晶墊之厚度範圍內，該置晶墊之至少一橫截面面積大於其下方另一橫截面面積；複數凸銲墊，係設於該置晶墊週圍，其中，在該凸銲墊之厚度範圍內，該凸銲墊之至少一橫截面面積大於其下方另一橫截面面積，且該凸銲墊之頂面高於置晶墊之頂面；晶片，係設置於該置晶墊上；銲線，電性連接該晶片及各該凸銲墊；以及封裝膠體，係包覆該置晶墊、凸銲墊、晶片及銲線，使該置晶墊及凸銲墊嵌卡於該封裝膠體中並外露出該些凸銲墊及置晶墊之底面。
  2. 如申請專利範圍第1項所述之半導體封裝件，其中，該凸銲墊為鳩尾形或半鳩尾形。
  3. 如申請專利範圍第1項所述之半導體封裝件，其中，該置晶墊為鳩尾形或半鳩尾形。
  4. 如申請專利範圍第1項所述之半導體封裝件，復包括防銲層，係形成於該封裝膠體底面上，且該防銲層具有複數供對應露出各該置晶墊及凸銲墊的防銲層開孔。
  5. 一種四方扁平無導腳之半導體封裝件之製法，係包括：準備一定義有複數置晶區之金屬板；以模具沖壓該金屬板，以於金屬板上之各該置晶區形成置晶墊，並於該置晶區外圍形成複數凸銲墊，其 中，在該置晶墊及凸銲墊之厚度範圍內，該凸銲墊之至少一橫截面面積大於其下方另一橫截面面積，以及該置晶墊之至少一橫截面面積大於其下方另一橫截面面積，且該凸銲墊之底面高於置晶墊之底面；於各該置晶墊上接置晶片；以銲線電性連接該晶片與凸銲墊；於該金屬板、晶片及銲線上覆蓋封裝膠體，使該凸銲墊嵌卡於該封裝膠體中；移除該金屬板底部，使該置晶墊及各該凸銲墊彼此間隔分佈；以及切割該封裝膠體，以形成複數半導體封裝件。
  6. 如申請專利範圍第5項所述之半導體封裝件之製法，其中，該模具包括公模、母模及複數插入件，且該母模具有複數陣列式排列之凹穴以及溝槽，係用以連通位於同一列上之凹穴，其中，該溝槽係供插入件滑設其中，使該凹穴開口面積小於凹穴底面積。
  7. 如申請專利範圍第5項所述之半導體封裝件之製法，其中，沖壓形成該置晶墊及凸銲墊之步驟包括以模具沖壓該金屬板以形成複數置晶墊及凸銲墊；以及壓制該置晶墊及凸銲墊頂面，俾使在該置晶墊及凸銲墊之厚度範圍內，該凸銲墊之至少一橫截面面積大於其下方另一橫截面面積，以及該置晶墊之至少一橫截面面積大於其下方另一橫截面面積。
  8. 如申請專利範圍第5項所述之半導體封裝件之製法，其 中，該凸銲墊之頂面高於置晶墊之頂面。
  9. 如申請專利範圍第5項所述之半導體封裝件之製法，復包括於沖壓該金屬板之前或之後，形成金屬層於該金屬板上下表面。
  10. 如申請專利範圍第6項所述之半導體封裝件之製法，其中，該凸銲墊為鳩尾形或半鳩尾形。
  11. 如申請專利範圍第5項所述之半導體封裝件之製法，復包括於移除該金屬板後，於該封裝膠體底面上形成防銲層，且令該防銲層具有複數供對應露出各該置晶墊及凸銲墊的防銲層開孔。
  12. 一種用於製造四方扁平無導腳之半導體封裝件之金屬板，係不具有貫穿之孔洞，且包括：複數凸銲墊，係一體成形於該金屬板上，且該些凸銲墊圍設出置晶區，其中，在該凸銲墊之厚度範圍內，該凸銲墊之至少一橫截面面積大於其下方另一橫截面面積；置晶墊，係位於置晶區，其中，在該置晶墊之厚度範圍內，該置晶墊之至少一橫截面面積大於其下方另一橫截面面積；以及複數孔穴，係對應形成於各該凸銲墊底面。
TW099113219A 2010-04-27 2010-04-27 四方扁平無導腳之半導體封裝件及其製法及用於製造該半導體封裝件之金屬板 TWI421993B (zh)

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JP2011099932A JP5824236B2 (ja) 2010-04-27 2011-04-27 ＱＦＮ（ＱｕａｄＦｌａｔＮｏｎＬｅａｄｅｄＳｅｍｉｃｏｎｄｕｃｔｏｒＰａｃｋａｇｅ）半導体パッケージ及びその製造方法、並びに該半導体パッケージの製造に用いられる金属板
US13/095,843 US9171740B2 (en) 2010-04-27 2011-04-27 Quad flat non-leaded semiconductor package and fabrication method thereof
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