TWI420823B - High - speed dual - mode remover - Google Patents

Description

High speed dual mode pre-discharger

The present invention relates to a pre-discharger, and more particularly to a high-number dual-mode pre-discharger for use in a frequency synthesizer in the field of wireless communication systems.

In the wireless communication system, the Prescaler is a necessary component for logically achieving the frequency planning of the system, especially in the high frequency module, how to reduce the use volume of the circuit and reduce the power consumption and achieve the pre-emption of the high-speed module. The demand for the device is really the goal that the developers have hoped for.

Among the frequency synthesizers designed with phase-locked loops, the high-speed dual-mode prescaler is one of the most important core circuits. The main reason for this is that the circuit must operate at very high frequencies and therefore consume the most power.

In the prior art, a D-type flip-flop (D Flip-Flop) is used together with an inverting or gate (NOR) and a reverse phase (NAND) to form a pre-discharger. A conventional D-type flip-flop such as Yuan J. and Svensson, C. In the circuit disclosed in "High-speed CMOS circuit technique," IEEE J. Solid-State Circuit, Vol. 24, pp. 62-70, Feb. 1989, see Figure 1. It uses nine transistors to achieve True Single Phase Clock D Flip-Flop (TSPC D Flip-Flop), although the D-type flip-flop can Used in high-speed circuits, but the number of transistors is too large, and it is successful. The problem of rate loss cannot be solved.

And J. Navarro and W. Van Noije, in "A 1.6-GHz dual modulus prescaler using the Extended True-Single-Phase-Clock CMOS circuit technique (E-TSPC)," IEEE J. Solid-State Circuits, vol. 34 , pp.97-102, Jan. 1999. Reveals an extended true single phase clock circuit D-type flip-flop (Extended TSPC D Flip-Flop, referred to as E-TSPC D Flip-Flop), see Figure 2, which reduces the number of transistors used in the circuit, can achieve the functions in the TSPC circuit by using six transistors, and effectively reduces the power consumption. Therefore, it has been successfully applied in many low-power mobile communication chips. However, when the pulse signal clk input is 1 and the data signal D is 0, the N-type transistor (M1) and the P-type transistor (M2) are simultaneously turned on, causing a DC/Short Current Power Problem.

In the pre-discharger, if high-speed frequency division is to be performed and the power consumption is reduced, the signal is usually subjected to a fast frequency division (for example, the signal is divided by 4), and then the fast-divided signal is subjected to high-frequency division (for example, it will be fast). The pre-divided signal is divided by 32), thereby achieving a dual-mode prescaler with a frequency division of 128, which has the advantages of reducing power consumption and speeding up the processing speed of the pre-processor, and if The divider, the reverse or the gate are separated from the inverting and the gate, and the number of transistors is large, which is not an ideal circuit design. Therefore, S. Pellerano, S. Levantino, C. Samori, and ALLacaita, in "A 13.5-mW 5-GHz frequency synthesizer with dynamic-logic frequency divider," IEEE J. Solid-State Circuits, vol. 39, no .2, pp. 378-383, Feb. 2004. A pre-remover for reducing the number of transistors is disclosed. As shown in FIG. 3, it utilizes an OR gate transistor Mor and a first D-type flip-flop 1 a first N-type electron crystal The body n1 is arranged in parallel to form a gate circuit, and a gate circuit is formed by using a gate transistor Mad and a fourth P-type transistor p4 in a second D-type flip-flop 2 to form a gate circuit. Using an inverter 3 for inverting processing, a total of sixteen transistors are used to achieve a divide-by-two or three-divider pre-distributor function, and the parallel gate transistor Mor and the first N-type transistor n1 are used in parallel. And the manner of the gate transistor Mad and the fourth P-type transistor p4 avoids the problem that the circuit is charged and discharged in series in a slow manner.

In this case, the operation of dividing by two or three is performed by the inverter 3 turning on or off the second D-type flip-flop 2, and when the output of the inverter 3 is 1, the fourth P-type transistor p4 Not turning on, thereby turning off the second D-type flip-flop 2, using only the first D-type flip-flop 1 as a pre-divider that divides the frequency by two, and when the output of the inverter 3 is 0, the The four P-type transistor p4 is turned on, and the first D-type flip-flop 1 is connected to the second D-type flip-flop 2, which is a pre-divider capable of dividing the frequency by three.

The case uses the output signal of the inverter 3 to control whether the second D-type flip-flop 2 is turned on or not. However, when the OR gate transistor Mor is turned on and the input signal in is 0, the AND gate is A first P-type transistor p1 electrically connected to the transistor Mor is also turned on, so that the power source is directly grounded via the first P-type transistor p1 and the gate transistor Mor, and there is still a current short circuit problem (DC Current Power Problem ), thus increasing the power consumption.

The main object of the present invention is to solve the power consumption caused by the DC Current Power Problem in the prior art and to save power.

In order to achieve the above object, the present invention provides a high speed dual mode pre-processor for use in a moment Pulse signal input, the high speed dual mode pre-receiver includes a first D-type flip-flop, a second D-type flip-flop and a main control transistor, the first D-type flip-flop includes a first output a first clock input end, the clock signal is input to the first D-type flip-flop by the first clock input end; the second D-type flip-flop includes a second data input end and a first The clock signal is input to the second D-type flip-flop by the second clock input end; and the main control transistor has a drain, a source and a gate. The drain is connected to the first output, and the source is connected to the second data input.

It can be seen from the above description that the D-type flip-flop and the second D-type flip-flop are connected to each other by the main control transistor, and the main control transistor has an OR gate state and a gate state. When the gate state is in the state of the gate, the main control transistor and the circuit in the first D-type flip-flop form a gate circuit instead of the gate transistor in the prior art, and when located in the gate state, the The main control transistor and the circuit in the second D-type flip-flop form a gate circuit instead of the gate circuit in the prior art, thereby reducing the number of transistors in the pre-processor.

Conventional technology

Clk‧‧‧clock signal

D‧‧‧Information signal

M1‧‧‧N type transistor

M2‧‧‧P type transistor

1‧‧‧First D-type flip-flop

2‧‧‧Second D-type flip-flop

3‧‧‧Inverter

N1‧‧‧First N-type transistor

P1‧‧‧First P-type transistor

P4‧‧‧4th P-type transistor

Mor‧‧‧ or gate transistor

Mad‧‧‧ and gate transistor

In‧‧‧Input signal

this invention

10‧‧‧First D-type flip-flop

Mn1‧‧‧First N-type transistor

Mn2‧‧‧Second N-type transistor

Mn3‧‧‧3rd N-type transistor

Mp1‧‧‧First P-type transistor

Mp2‧‧‧Second P-type transistor

Mp3‧‧‧ Third P-type transistor

Out‧‧‧first output

20‧‧‧Second D-type flip-flop

Mn4‧‧‧4th N-type transistor

Mn5‧‧‧ fifth N-type transistor

Mn6‧‧‧ sixth N-type transistor

Mp4‧‧‧4th P-type transistor

Mp5‧‧‧ fifth P-type transistor

Mp6‧‧‧6th P-type transistor

In‧‧‧Second data input

Mj‧‧‧main control transistor

Mc‧‧‧modal control signal

Clk1‧‧‧first clock input

Clk2‧‧‧second clock input

30‧‧‧Mode 2 of the invention

31‧‧‧Mode 3 of the invention

40‧‧‧The modality of the prior art

41‧‧‧Mental Technology Modal Three

Figure 1 is a schematic diagram of a D-type flip-flop of a TSPC of the prior art.

Figure 2 is a schematic diagram of a D-type flip-flop of the E-TSPC of the prior art.

Figure 3 is a schematic diagram of a prior art pre-processor circuit.

4 is a circuit diagram of a preferred embodiment of the present invention.

Figure 5 is a schematic diagram showing the results of circuit waveform simulations in accordance with a preferred embodiment of the present invention.

Figure 6 is a graph comparing the power consumption of the simulation results of the present invention with the prior art.

Figure 7 is a comparison of power delay products of the simulation results of the present invention and the prior art.

The detailed description and technical content of the present invention will now be described with reference to the following drawings: Referring to FIG. 4, it is a schematic diagram of a circuit according to a preferred embodiment of the present invention. As shown in the figure, the present invention is a high-speed dual mode. a pre-discharger for inputting a clock signal, the high-speed dual-mode pre-disconnector including a first D-type flip-flop 10, a second D-type flip-flop 20 and a main control transistor Mj, the first a D-type flip-flop 10 includes a first output terminal out, a first clock input terminal clk1, the clock signal is input to the first D-type flip-flop 10 by the first clock input terminal clk1; The second D-type flip-flop 20 includes a second data input terminal in and a second clock input terminal clk2. The clock signal is also input to the second D-type forward and reverse by the second clock input terminal clk2. The main control transistor Mj has a drain, a source and a gate, the drain is connected to the first output terminal outlet, and the source is connected to the second data input terminal in, wherein In this embodiment, the main control transistor Mj is a P-type transistor, and the gate of the main control transistor Mj is used for a modal control. No. mc input, the main control transistor Mj controls the conduction of the first D-type flip-flop 10 and the second D-type flip-flop 20 by the modal control signal mc to change the mode, and In this embodiment, the modality of the present invention has a modality 2 and a modality 3, wherein the modality 2 divides the frequency of the clock signal by two, and the modality 3 divides the frequency of the clock signal. three.

To further illustrate, the first D-type flip-flop 10 includes a first N-type transistor Mn1, a second N-type transistor Mn2, a third N-type transistor Mn3, and a first P-type transistor Mp1. a second P-type transistor Mp2 and a third P-type transistor Mp3, each of the N-type transistor and the P-type transistor having a drain, a source and a gate, the first P-type The source of the crystal Mp1 is connected to the drain of the first N-type transistor Mn1 to form the first The output terminal out, the source of the second P-type transistor Mp2 is connected to the drain of the second N-type transistor Mn2, the source of the third P-type transistor Mp3 and the third N-type transistor Mn3 a drain connection, wherein the second N-type transistor Mn2, the third N-type transistor Mn3, and the gate of the first P-type transistor Mp1 are the first clock input terminal clk1 for the clock signal Input.

The second D-type flip-flop 20 includes a fourth N-type transistor Mn4, a fifth N-type transistor Mn5, a sixth N-type transistor Mn6, a fourth P-type transistor Mp4, and a fifth. a P-type transistor Mp5 and a sixth P-type transistor Mp6, each of the N-type transistor and the P-type transistor has a drain, a source and a gate, and the source of the fourth P-type transistor Mp4 The pole is connected to the drain of the fourth N-type transistor Mn4 to form the second data input terminal in, and the source of the fifth P-type transistor Mp5 is connected to the drain of the fifth N-type transistor Mn5. a source of the sixth P-type transistor Mp6 is connected to a drain of the sixth N-type transistor Mn6, wherein the fourth N-type transistor Mn4, the fifth N-type transistor Mn5, and the sixth P-type transistor Mp6 The gates are all the second clock input terminal clk2 for inputting the clock signal.

The main control transistor Mj has an OR gate state and a gate state. When in the OR gate state, the main control transistor Mj forms an OR gate circuit in parallel with the first N-type transistor Mn1. In the gate state, the main control transistor Mj and the fourth P-type transistor Mp4 are connected in parallel to form a gate circuit, and the gate of the main control transistor Mj is connected with a control signal for controlling the first D. The state in which the type flip-flop 10 is connected to the second D-type flip-flop 20.

In addition, when the first P-type transistor Mp1 is turned on because the clock signal is 0, and the main control transistor Mj is also turned on, the fourth N-type transistor Mn4 is not turned on because the clock signal is 0. Does not cause a current short circuit problem.

Please refer to FIG. 5 , which is a schematic diagram of circuit waveform simulation results according to a preferred embodiment of the present invention. The top horizontal bar diagram is a waveform diagram of a clock signal, and the middle horizontal bar diagram is a mode of dividing the frequency by three in the present invention. The third schematic diagram, the lower horizontal bar diagram is a schematic diagram of the second mode after dividing the frequency by two, as shown in the figure, the present invention can surely divide the frequency of the input clock signal by two or three, and maintain A fixed voltage value.

Please refer to Table 1, which compares the results of the present invention with the conventional technology in TSMC 0.18 micron process:

It should be noted that the prior art is S. Pellerano, S. Levantino, C. Samori, and ALLacaita, in IEEE J. Solid-State Circuits, vol. 39, no. 2, pp. 378-383, According to the technique of "A 13.5-mW 5-GHz frequency synthesizer with dynamic-logic frequency divider," published by Feb. 2004., it can be known from Table 1 that a total of 16 transistors must be used in the prior art, of which 12 are two. The number of transistors that must be used for a D-type flip-flop, therefore, the number of additional used transistors is four; compared to the prior art, the invention only needs to use 13 transistors in total, and the additional use of electricity There is only one crystal. In the maximum frequency comparison that can be used, 497MHz and 445MHz are the maximum frequencies of the conventional technology mode 2 and mode 3, respectively. In a preferred embodiment of the present invention, the maximum frequencies of the modal two and the modal three are 502 MHz and 497 MHz, respectively. In terms of power consumption, the mode 2 and mode 3 of the conventional technique at the maximum frequency are 6.38 uW and 5.97 uW, respectively; and in a preferred embodiment of the invention, the mode 2 and the mode 3 are at the maximum. The power consumption of the frequency is 5.24uW and 5.27uW, respectively. Compared with the prior art, the present invention can save a power ratio of 23% and 27% respectively in the modal second and the modal three.

Please refer to FIG. 6, which is a comparison diagram of the power consumption of the simulation results of the present invention and the prior art. As shown in the figure, the mode two 30 of the present invention and the mode three 31 of the present invention are at the same supply voltage. The power consumption is smaller than the modality 40 of the prior art and the modality 41 of the prior art. Referring again to FIG. 7, which is a power-delay-product comparison diagram of the simulation results of the present invention and the prior art, as shown in the figure, we can more clearly understand the modality 30 of the present invention. Or the modality 31 of the present invention is superior to the prior art in terms of high frequency, low frequency, and power consumption.

In summary, the present invention has the following features as compared with the prior art:

(1) The first D-type flip-flop 10 and the second D-type flip-flop 20 are connected to each other by the main control transistor Mj, and the gate of the main control transistor Mj is connected with a control signal for Switching the first D-type flip-flop 10 to the second D-type flip-flop 20 or disconnecting it, instead of turning off the fourth P-type transistor Mp4 by an inverter to turn off the first The D-type flip-flop 10 is connected to the second D-type flip-flop 20.

(2) The main control transistor Mj has a gate state and a gate state, and the gate state and the gate state replace the gate transistor and the gate transistor in the prior art to reduce electricity. The number of crystals reduces the power consumption.

(3). The current in the conventional circuit is also solved by the setting of the main control transistor Mi. Road problem.

Therefore, the present invention is highly progressive and conforms to the requirements of the invention patent application, and the application is filed according to law, and the praying office grants the patent as soon as possible.

The present invention has been described in detail above, but the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the scope of the invention. That is, the equivalent changes and modifications made by the scope of the present application should remain within the scope of the patent of the present invention.

10‧‧‧First D-type flip-flop

Mn1‧‧‧First N-type transistor

Mn2‧‧‧Second N-type transistor

Mn3‧‧‧3rd N-type transistor

Mp1‧‧‧First P-type transistor

Mp2‧‧‧Second P-type transistor

Mp3‧‧‧ Third P-type transistor

Out‧‧‧first output

20‧‧‧Second D-type flip-flop

Mn4‧‧‧4th N-type transistor

Mn5‧‧‧ fifth N-type transistor

Mn6‧‧‧ sixth N-type transistor

Mp4‧‧‧4th P-type transistor

Mp5‧‧‧ fifth P-type transistor

Mp6‧‧‧6th P-type transistor

In‧‧‧Second data input

Mj‧‧‧main control transistor

Mc‧‧‧modal control signal

Clk1‧‧‧first clock input

Clk2‧‧‧second clock input

Claims (4)

A high-speed dual-mode pre-discharger for inputting a clock signal, comprising: a first D-type flip-flop comprising a first N-type transistor, a second N-type transistor, and a third An N-type transistor, a first P-type transistor, a second P-type transistor, a third P-type transistor, a first output terminal and a first clock input terminal, each N-type transistor and Each of the P-type transistors has a drain, a source and a gate, and a source of the first P-type transistor is connected to a drain of the first N-type transistor and serves as the first output terminal. a source of the second P-type transistor is connected to a drain of the second N-type transistor, and a source of the third P-type transistor is connected to a drain of the third N-type transistor, and the clock signal is borrowed The first clock input terminal is input to the first D-type flip-flop; the second D-type flip-flop includes a second data input terminal and a second clock input terminal, and the clock signal is borrowed Inputting from the second clock input terminal to the second D-type flip-flop; and a main control transistor having a drain, a source and a gate, the drain being connected to the first output The source electrode connected to the second data input terminal. The high-speed dual-mode pre-processor according to claim 1, wherein the second D-type flip-flop comprises a fourth N-type transistor, a fifth N-type transistor, and a sixth N-type transistor. a fourth P-type transistor, a fifth P-type transistor, and a sixth P-type transistor, each of the N-type transistor and the P-type transistor having a drain, a source, and a gate. a source of the fourth P-type transistor is connected to a drain of the fourth N-type transistor, and a source of the fifth P-type transistor is connected to a drain of the fifth N-type transistor, the sixth P The source of the type transistor is connected to the drain of the sixth N-type transistor. The high-speed dual-mode pre-discharge device according to claim 2, wherein a position at which a source of the fourth P-type transistor is connected to a drain of the fourth N-type transistor is the second data input end. The high speed dual mode pre-disconnector of claim 1, wherein the main control transistor is a P-type transistor.