TWI419630B - Embedded printed circuit board and method of manufacturing the same - Google Patents

Description

Embedded printed circuit board and manufacturing method thereof

The present invention claims priority to the Korean Patent Application No. 10-2010-0013439, filed on Feb. 12, 2010, which is hereby incorporated by reference.

The present invention relates to a method of fabricating an embedded printed circuit board and obtaining an embedded printed circuit board structure by the manufacturing method, and more particularly to a technique capable of forming an electronic device wafer and a printed circuit board. The effective electrical connection structure can be widely applied.

With the development of semiconductors and electronic devices, printed circuit boards have become an important electronic component and are widely used as circuit components constituting electrical and electronic devices, covering a wide range of electrical and electronic products, such as radio, television, and computer computing. Memory, and high-tech electronics. Recent advances in electrical and electronic devices have required a high quality printed circuit board, so the circuit density of printed circuit boards is rapidly increasing. In the case of an embedded printed circuit board, the component will be fixed with a metal such as gold (Au) by using a dry film photoresist mask process and a plating area process to achieve high quality and high circuit density.

The most important part of embedded printed circuit board technology is whether its embedded components handle high input/output numbers properly. This can be expressed as a fine pitch grade. Most of the technology for manufacturing embedded printed circuit boards uses micropatterned circuit technology, such as via/land, bump/land or solder/pad structures. A bonding process for connecting an electronic device wafer to a circuit.

1 shows a conventional method of manufacturing an embedded printed circuit board in which an electronic device wafer 5 is attached to a circuit board by using a solder/pad structure.

Referring to Fig. 1, in order to fix an electronic device wafer 5 to an internal circuit board, the internal circuit board is composed of an insulating layer 1, an outer metal layer 2, 2', and a circuit pattern 3. A solder ball 7 is formed on a solder ball pad 6 and is indirectly connected to a portion of the circuit pattern 3. Then, an insulating layer 8 is formed on the circuit board including the electronic device wafer 5, and the circuit board is turned over. Next, an external circuit pattern 10 is formed, or a plated through hole 11 is formed, and plating is performed, and the circuit is completed.

However, when using an via/land, bump/land or solder/pad structure to connect an embedded component to a printed circuit board, it is embedded A reduction in the electrode spacing of the components will cause a limitation. The actual spacing of most of the component electrodes is 200 μm, and the bareness can be reduced to 130 μm. Therefore, in terms of mass manufacturing, an active device requires a wafer-level package having a re-distributed layer structure, and the redistribution layer can be connected to a printed circuit board and a wafer, and a passive layer is required. Electrode spacing greater than 200 μm for a reliable connection.

The invention provides a method for manufacturing an embedded printed circuit board and an embedded printed circuit board structure, wherein the embedded component is directly connected to the printed circuit board without using additional structures, such as via/land, metal Bump/land, solder/pad or paste/pad, which achieve fine-pitch input and output connections, ensuring the convenience and comfort of electronic components The freedom of design of printed circuit boards is maximized.

According to an aspect of the present invention, a method for manufacturing an embedded printed circuit board includes the first step of forming an internal circuit pattern that exposes a wafer contact embedded in an electronic device wafer in an insulating layer; The second step: forming a first circuit pattern directly connected to the wafer contacts and the internal circuit pattern.

The first step includes: a step a1: forming the internal circuit pattern on a metal seed layer; and a step a2: fixing an electronic device wafer on a fixed area spaced from the internal circuit pattern; a step a3 Forming an external circuit pattern layer including the insulating layer, wherein the electronic device wafer and the wafer contact are embedded in the insulating layer; and a step a4: exposing the wafer contact of the electronic device wafer.

In steps a1, a2, a3 and a4, the metal seed layer is formed on a carrier. That is, the step a1 includes: forming the internal circuit pattern on the metal seed layer above the carrier, and the step a4 includes: removing the carrier to expose the wafer contact of the electronic device chip .

The step a1 comprises: forming a dry film photoresist pattern on the metal seed layer, followed by electroplating.

The step a2 includes: bonding an active device or a passive device to the fixed region, and exposing the metal seed layer by using a non-conductive glue.

The step a3 includes: aligning at least one first insulating film with a second insulating film, wherein the first insulating film is formed to surround the electronic device wafer, and the second insulating film covers a top surface of the first insulating film; An external circuit layer is formed on the second insulating film; and heated and pressed to form the external circuit layer. Alternatively, the step a3 includes: aligning at least one first insulating film and a second insulating film with an external circuit layer, wherein the first insulating film is formed to surround the electronic device wafer, and the second insulating film covers the first a top surface of the insulating film, and the external circuit layer includes a circuit pattern disposed between the first insulating film and the second insulating film.

The step a4 includes removing the carrier and the metal seed layer by a half etching process. After the half etching process, a dry etching step is further performed on the half etching surface.

The second step includes: forming the first circuit pattern including a connection region, wherein the wafer contacts of the electronic device wafer and the internal circuit pattern are directly connected to each other.

The second step includes: applying a dry film photoresist to the top or bottom surface of the internal circuit pattern, and patterning the dry film photoresist; plating the patterned region to form the first circuit pattern; The dry film photoresist is removed. Alternatively, the second step includes: forming a metal film on a top surface or a bottom surface of the internal circuit pattern; patterning the metal film by photolithography to form the first circuit pattern; and forming the external circuit The layers are patterned to form an external circuit pattern.

The manufacturing method further includes: a third step of: forming an insulating layer and an external circuit layer on both sides of the printed circuit board including the first circuit pattern; and a fourth step: forming a through hole, the electrical property thereof Connecting to at least one region of the first circuit pattern and the internal circuit pattern; a fifth step of: patterning the external circuit layer to form a second circuit pattern; and a sixth step: forming a solder resist layer on a predetermined area of the second circuit pattern; and a seventh step of performing a surface treatment on a region of the second circuit pattern that does not form the solder resist layer.

An embedded printed circuit board manufactured by the above manufacturing method, comprising: an electronic device chip comprising an external wafer contact; a first circuit pattern comprising a connection region directly connected to the wafer connection of the electronic device chip One end of the dot; an insulating layer, the electronic device chip and the first circuit pattern are embedded in the insulating layer; and a second circuit pattern electrically connected to the first circuit pattern.

The connection region may be formed by directly connecting the first circuit pattern to the wafer contact and an internal circuit pattern formed under the first circuit pattern.

The connection region may be formed by a predetermined portion of the first circuit pattern covering a top surface or a portion of a side of the wafer contact.

The top surface height line of the first circuit pattern may be equal to or higher than the top surface height line of the end of the wafer contact.

The top surface height line of the internal circuit pattern may be equal to or lower than the bottom surface height line of the end of the wafer contact.

The electronic device chip can be an active device or a passive device.

According to the present invention, the embedded component can be directly connected to the printed circuit board without using additional structures such as via/land, bump/land, solder/pad (solder/ Pad) or conductive paste/pad (paste/pad), which can achieve fine pitch input and output connections, ensure the convenience and comfort of electronic components, and achieve maximum freedom of design of printed circuit boards.

Preferred embodiments of the present invention will now be described in detail in conjunction with the drawings. The embodiments described below are used as examples to convey their spirit to those of ordinary skill in the art. Accordingly, the embodiments are embodied in different shapes and are not limited to the embodiments described herein. Moreover, the size and thickness of the device can be exaggerated for convenience of the drawings. The same reference numbers are used in the present disclosure and the drawings.

The invention provides a method for manufacturing an embedded printed circuit board, which exposes an input/output terminal of an embedded component to a printed circuit board, and directly connects an input/output contact to the printed circuit by electroplating Board circuit pattern, instead of using via/land, bump/land, solder/pad or paste/pad And the printed circuit board structure completed by the manufacturing method.

In order to achieve the object, the manufacturing method comprises the first step of: forming an internal circuit pattern exposing a contact embedded in an electronic device wafer in an insulating layer; and second step: forming a first circuit pattern directly Connected to contacts and internal circuit patterns.

The printed circuit board completed by the manufacturing method comprises an electronic device chip, a first circuit pattern, an insulating layer and a second circuit pattern, the electronic device chip has an external wafer contact, and the first circuit pattern has a connection region, the connection The area is directly connected to the wafer having one end connected to the contact of the electronic device chip, the electronic device chip and the first circuit pattern are embedded in the insulating layer, and the second circuit pattern is electrically connected to the first circuit pattern.

A method of manufacturing an embedded printed circuit board according to an embodiment of the present invention will now be described in detail with reference to Figs. 2, 3 and 4.

A method of fabricating an embedded printed circuit board according to an embodiment of the present invention includes a first step of forming an internal circuit pattern layer exposing a contact embedded in an electronic device wafer in an insulating layer; Step: Form a first circuit pattern directly connected to the contact and the internal circuit pattern layer. In particular, the first step may form an internal circuit pattern layer, in which an isolation circuit pattern is formed on a metal seed layer, or a circuit pattern is formed on a metal seed layer above a carrier board. on. In an embodiment of the invention, a metal seed layer is formed on the carrier. The process of forming the circuit pattern on the metal seed layer above the carrier and the process of forming the circuit pattern on the metal seed layer without the carrier can be distinguished only by the carrier removal step.

Referring to FIG. 2, in step S1, a carrier and a metal seed layer formed thereon are provided. In step S2, an internal circuit pattern layer corresponding to an isolation circuit pattern is formed on the metal seed layer, and an electronic device The wafer is attached thereto. Then, in step S3, an insulating layer is formed on the inner circuit pattern layer and the electronic device wafer, and in steps S4 and S5, one of the connection pads of the electronic device wafer (hereinafter referred to as a wafer contact) is exposed, and In step S6, the wafer contacts are directly connected to the circuit pattern by electroplating.

1. The bare process of the embedded process of the electronic device chip and the wafer contact of the electronic device chip.

The foregoing manufacturing method will now be described in detail with reference to FIG. 3.

In step S1, a predetermined internal circuit pattern 130 is formed over a 110, and a metal seed layer 120 is formed on the carrier 110. Here, the internal circuit pattern 130 is formed by applying a dry film photoresist to the metal seed layer 120 and patterning and plating the metal seed layer 120 including the dry film photoresist pattern.

In step S2, the electronic device wafer 150 is fixed to a portion of the metal seed layer 120, which is not formed with any internal circuit pattern 130. The electronic device chip 150 includes an active device and a passive device. In FIG. 3, an active device 153 has a wafer contact 152 formed on the bottom surface of the active device 153. A passive device 151 has a wafer contact 152 that surrounds the side of the passive device 151. The above description is shown on the electronic device wafer 150. The fixing process can be performed by applying the non-conductive paste 140 on the metal seed layer 120, and the electronic device wafer 150 is bonded to the non-conductive paste 140.

In step S3, an insulating layer 160 and an external circuit layer 170 are formed to surround the electronic device wafer 150. The insulating layer 160 may be formed in a multilayer structure. In particular, at least one first insulating film 161 is formed to surround the electronic device wafer 150, a second insulating film 162 covers the top surface of the first insulating film 161, and the second insulating film 162 is aligned with the first insulating film 161 to externally The circuit layer 170 is formed on the second insulating film 162, heated and pressed to form an external circuit layer. Here, in step S31, the first insulating film 161 and the second insulating film 162 may be stacked. Further, any of the first insulating film 161 and the second insulating film 162 may be composed of a plurality of layers. An epoxy resin, a phenolic resin, a prepreg, a polyimide film or an ABF (ajinomoto build-up film) film can be used as the material of the first insulating film 161 and the second insulating film 162. .

At the same time, in step S32, at least one of the first insulating films 161 may form a structure (third insulating film), the structure includes a plurality of circuit patterns 164 and conductive vias 165, and the circuit patterns 164 are respectively formed on The conductive vias 165 electrically connect the circuit patterns 164 to each other on both sides of an insulating layer 163.

In step S4, after the external circuit layer 170 is formed, the carrier 110 is removed. The following steps will illustrate the assumption that the carrier has been removed from the structure and flipped the structure so that the wafer contacts of the electronic device are up.

In step S5, after the carrier is removed, the wafer contacts (connection contacts of the electronic device wafer) are exposed. Specifically, in steps S51 and S52, the metal seed layer 120 is removed by a half etching process. Then, in step S53, dry etching may be performed on the half-etched surface, thereby more effectively exposing the wafer contacts.

2. The process of directly connecting the wafer contacts of the electronic device chip and the circuit pattern (Fig. 4).

After performing the foregoing process of the first step, in step S6, a second step of forming a first circuit pattern directly connected to the wafer contacts of the electronic device chip and the internal circuit pattern is performed.

Specifically, a photosensitive material 155 (eg, a dry film photoresist) is coated and patterned on a printed circuit board including wafer contacts 152, 154, and then a printed circuit board including the dry film photoresist 155 is plated. To form a first circuit pattern 180. For example, the dry film photoresist 155 is coated and patterned on the top or bottom surface of the internal circuit pattern 130, and the first circuit pattern 180 is formed in the patterned region by electroplating. Then, the external circuit layer 170 is patterned, and the dry film photoresist is removed, as shown in steps S61, S62, and S63.

Alternatively, a metal film can be used to form the first circuit pattern. In particular, a metal thin film can be formed by electroplating, and photolithography is used to form a first circuit pattern. The external circuit layer is then patterned and the dry film photoresist is removed.

In particular, in step S6, the first circuit pattern includes connection regions 181a, 181b, 181c, and 181d in which the wafer contacts of the electronic device wafer and the internal circuit patterns are directly connected to each other. Here, the wafer contacts of the electronic device chip are directly connected to the circuit pattern without additional use of via/land, bump/land, solder/pad. Or conductive paste / pad (paste / pad).

Thus, a metal (e.g., copper) can be used to form a first circuit pattern on bare wafer contacts corresponding to an input/output contact without the need to form vias/vias. In addition, the first circuit pattern may be formed in various shapes, such as a line shape, a circle shape, and a polygon shape, and connected to the wafer contacts, and the position of the first circuit pattern may be freely changed according to the circuit arrangement. Moreover, due to the absence of solder pads, the input/output contact pitch of the electronic device chip can be in accordance with the distance between the printed circuit board circuits (currently the minimum line spacing L/S is 15/15 μm, and the pitch is 30 μm).

In other words, when the foregoing techniques are used, the components can be effectively embedded to achieve a high integrated printed circuit board, and even under the condition of reducing the input/output contact pitch, the number of input/output contact pads will be Reduce the high integration of semiconductor devices. Furthermore, the physical form of the embedded component, such as bumping, electronic materials, etc., will not be limited, so the component can be widely applied and the design freedom of the printed circuit board can be improved.

3. Manufacture of high integrated printed circuit boards (completely stacked).

After the circuit contacts are directly connected to the circuit patterns by the foregoing process, a highly integrated printed circuit board is fabricated.

Referring to FIG. 5, in steps S7 and S8, an external circuit layer including an insulating layer is formed on both sides of the printed circuit board, and then in step S9, a through hole is formed and filled with the plating material, in steps S10 and S11. A second circuit pattern is formed, and in steps S12 and S13, a solder resist layer or a surface treatment may be additionally applied.

Specifically, referring to FIG. 6, after the foregoing step S6, in steps S7 and S8, an insulating layer 210 and an external circuit layer 220 are successively formed on both sides of the printed circuit board, and the wafer contacts and the first circuit pattern are in contact with each other. connection. Then, in step S9, a through hole H is formed to electrically connect at least one region of the first circuit pattern and the internal circuit pattern. In step S10, the via hole H is formed by a process (for example, laser processing), and the via hole H is filled with a metal 230. Metal 230 can be one of copper, silver, tin, gold, nickel, and lead. The via hole H may be filled with a metal by using electroless plating, electroplating, screen printing, sputtering, evaporation, inkjet, dispensing, or a combination thereof.

The outer circuit layer 220 is patterned to form a second circuit pattern 221. Then, a solder resist layer 240 is formed on a predetermined portion of the second circuit pattern 221, and a surface treatment is performed on a portion where the second circuit pattern 221 of the solder resist layer 240 is not formed.

The surface treatment is performed by plating the surface of the second circuit pattern 221 with a plating layer 250 such as copper, nickel, lead, gold, tin, silver, cobalt or a single layer formed of a binary alloy or a ternary alloy of the foregoing metal. Plating or multi-layer plating.

In other words, according to the manufacturing method of the present invention, which comprises a first step and a second step for product integration of products, a recess can be formed in a copper compound layer by using a printed circuit board and The electronic device wafer is mainly embedded, and a fully stacked type high-integral printed circuit board is manufactured. To achieve this goal, a physical method (such as surface grinding) is usually not used, thus ensuring the stability of the embedded components of the printed circuit board.

Figure 7 is a cross-sectional view of an embedded printed circuit board completed by a method of fabricating an embedded printed circuit board in accordance with the present invention. In particular, an enlarged view of an area of the electronic device wafer contacts is directly connected to the circuit pattern.

The printed circuit board according to the present invention comprises an electronic device wafer 150, circuit patterns 130, 180, an insulating layer 160 and a second circuit pattern 221, the electronic device wafer 150 has external wafer contacts 152, and the circuit patterns 130, 180 have a connection region 180d The connection area 180d is directly connected to one end of the wafer contact 152, the electronic device wafer 150 and the circuit patterns 130 and 180 are embedded in the insulating layer 160, and the second circuit pattern 221 is electrically connected to the first circuit pattern 180.

The connection region 180d may be composed of a first circuit pattern 180 directly connected to the wafer contact 152 and an internal circuit pattern 130 formed under the first circuit pattern 180. In particular, a region of the first circuit pattern 180 may cover the top or side of the wafer contacts 152.

In the connection region, the wafer contacts 152 and the first circuit pattern 180 may be configured and connected, whereby the top surface height line X of the first circuit pattern 180 is equal to or higher than the top surface height line Y1 of one end of the wafer contact 152. .

Alternatively, the connection region may be formed such that the top surface height line Z of the internal circuit pattern 130 is equal to or lower than the bottom surface height line Y2 at one end of the wafer contact 152.

Although FIG. 6 shows only one passive device as the electronic device wafer 150, the present invention can be configured with a contact of the active device, which is identical to the arrangement of the passive device shown in FIG.

The present invention has been disclosed in the foregoing embodiments, and is not intended to limit the present invention. Any of the ordinary skill in the art to which the invention pertains can be modified and modified without departing from the spirit and scope of the invention. . Therefore, the scope of the invention is defined by the scope of the appended claims.

1. . . Insulation

2. . . Metal layer

2'. . . Metal layer

3. . . Circuit pattern

6. . . Solder ball pad

7. . . Solder ball

8. . . Insulation

10. . . External circuit pattern

110. . . Carrier board

120. . . Metal seed layer

130. . . Internal circuit pattern

140. . . Non-conductive glue

150. . . Electronic device chip

151. . . Passive device

152. . . Wafer contact

153. . . Active device

152. . . Wafer contact

155. . . Dry film photoresist

160. . . Insulation

161. . . Insulating film

162. . . Insulating film

163. . . Insulation

164. . . Circuit pattern

165. . . Conductive through hole

170. . . External circuit layer

180. . . First circuit pattern

180d. . . Connection area

181a. . . Connection area

181b. . . Connection area

181c. . . Connection area

181d. . . Connection area

210. . . Insulation

220. . . External circuit layer

221. . . Second circuit pattern

230. . . metal

240. . . Solder mask

250. . . Plating

H. . . Through hole

S1~S13. . . step

S31~S32. . . step

S51~S53. . . step

S61~S63. . . step

X. . . Height line

Y1. . . Height line

Y2. . . Height line

Z. . . Height line

1 shows a conventional method of fixing an electronic device wafer to a circuit board in an embedded structure;

2 is a flow chart showing a method of manufacturing an embedded printed circuit board according to the present invention;

3 and 4, showing a method of fabricating an embedded printed circuit board according to the present invention;

5 is a flow chart showing a method of manufacturing the embedded printed circuit board according to the present invention after the manufacturing method of FIG. 3;

Figure 6, showing the manufacturing method of Figure 4;

Figure 7 is an enlarged view of a connection area showing an electronic device wafer contact and a circuit pattern connected to each other in accordance with the printed circuit board structure of the present invention.

S1~S6. . . step

Claims (19)

A method of manufacturing an embedded printed circuit board, comprising: forming an internal circuit pattern exposing a wafer contact embedded in an electronic device wafer in an insulating layer; and forming a first circuit pattern directly connected to The wafer contact and the internal circuit pattern, wherein the first circuit pattern covers at least a portion of a side of the wafer contact. The manufacturing method of claim 1, wherein the step of forming an internal circuit pattern comprises: forming the internal circuit pattern on a metal seed layer; and fixing the electronic device wafer to the internal circuit pattern Forming an outer circuit pattern layer including one of the insulating layers, wherein the electronic device wafer and the wafer contact are embedded in the insulating layer; and the wafer contacts of the electronic device wafer are exposed. The manufacturing method of claim 2, wherein the step of forming the internal circuit pattern on a metal seed layer comprises: forming the internal circuit pattern on a metal seed layer above a carrier, and The step of exposing the wafer contacts includes removing the carrier to expose the wafer contacts of the electronic device wafer. The manufacturing method of claim 2, wherein the step of forming the internal circuit pattern on a metal seed layer comprises: forming a dry film photoresist pattern on the metal seed layer, and then performing electroplating. The manufacturing method of claim 4, wherein the step of fixing the electronic chip device comprises: bonding an active device or a passive device to the bare metal seed layer by using a non-conductive adhesive; On the fixed area. The manufacturing method of claim 4, wherein the step of forming an external circuit pattern layer comprises: aligning at least one first insulating film with a second insulating film, wherein the first insulating film is formed to surround The electronic device wafer, the second insulating film covers a top surface of the first insulating film; an external circuit layer is formed on the second insulating film; and is heated and pressed to form the external circuit layer. The manufacturing method of claim 4, wherein the step of forming an external circuit pattern layer comprises: aligning at least one first insulating film and a second insulating film with an external circuit layer, wherein the first insulation a film is formed to surround the electronic device wafer, the second insulating film covers a top surface of the first insulating film, and the external circuit layer having a third insulating film includes a circuit pattern. The case is disposed between the first insulating film and the second insulating film. The manufacturing method of claim 4, wherein the step of exposing the wafer contact comprises: removing the metal seed layer by a half etching process. The manufacturing method of claim 8, further comprising performing a dry etching step on the half etching surface after the half etching process. The manufacturing method of claim 8, wherein the forming the first circuit pattern comprises: forming the first circuit pattern, wherein the wafer contacts of the electronic device wafer and the internal circuit pattern are directly connected to each other . The manufacturing method of claim 10, wherein the step of forming a first circuit pattern comprises: applying a dry film photoresist to a top surface or a bottom surface of the internal circuit pattern, and the dry film photoresist Patterning; plating the patterned region to form the first circuit pattern; patterning the external circuit layer to form an external circuit pattern; and removing the dry film photoresist. The manufacturing method of claim 10, wherein the step of forming a first circuit pattern comprises: Forming a metal film on a top surface or a bottom surface of the internal circuit pattern; patterning the metal film by photolithography to form the first circuit pattern; patterning the external circuit layer to form an external circuit a pattern; and removing the dry film photoresist. . The manufacturing method of claim 8, further comprising: forming an insulating layer and an external circuit layer on both sides of the printed circuit board including the first circuit pattern; forming a through hole, the electrical property thereof Connecting at least one region of the first circuit pattern and the internal circuit pattern; patterning the external circuit layer to form a second circuit pattern; forming a solder resist layer on a predetermined region of the second circuit pattern; And performing a surface treatment on a region of the second circuit pattern where the solder resist layer is not formed. An embedded printed circuit board comprising: an electronic device chip including an external wafer contact; a first circuit pattern directly connected to the electronic device chip One end of the wafer contact; an insulating layer, wherein the electronic device chip and the first circuit pattern are embedded in the insulating layer; and a second circuit pattern electrically connected to the first circuit pattern, wherein the first circuit The pattern covers at least a portion of one side of the wafer contact. The embedded printed circuit board of claim 14, further comprising an internal circuit pattern formed under the first circuit pattern. The embedded printed circuit board of claim 15, wherein the first circuit pattern further covers a portion of a top surface of the wafer contact. The embedded printed circuit board of claim 15, wherein a height line of a bottom surface of the first circuit pattern is equal to or higher than a top line height of the end of the wafer contact in the connection region. The embedded printed circuit board of claim 16, wherein a top surface height line of the internal circuit pattern is equal to or lower than a bottom height line of the end of the wafer contact in the connection region. The embedded printed circuit board of claim 14, wherein the electronic device wafer is an active device or a passive device.