TWI419462B - Class d amplifier - Google Patents

Description

Class D amplifier circuit

The invention relates to a class D amplifier circuit, in particular to a class D amplifier circuit whose internal circuit can adjust the circulating current to reduce signal distortion.

The carrier frequency of a class D amplifier, that is, the duty cycle of the pulse width modulation signal generator, is generally between 200 kHz and 2 MHz. At the highest output power, the signal is high in the whole cycle; at the highest output power of 50%, the signal has a half-cycle time as the high level, and the level is linearly decreasing with the required audio level. Since the output power is proportional to the output pulse width, the degree of distortion of the signal is also proportional to the error of the effective pulse width compared to the desired pulse width. In the case of a large signal, although the error is small, the error is large when the signal is input small. For a conventional CMOS process used in a Class D amplifier, a minimum pulse width of about 50 ± 10 nanoseconds can be output.

In addition, because the human ear has a considerable dynamic range, if you want to hear the undistorted output signal, the total error signal ratio (the so-called Total Harmonic Distortion Plus Noise (THD+N)) needs to be reached. About -60dB. The maximum pulse width and the minimum pulse width of the pulse width modulation system need to have a linear ratio of 1000:1 or more to achieve the above performance. For example, when the former is 2 microseconds, the latter needs to be as small as 2 nanoseconds. However, as mentioned earlier, the current process capability provides only a minimum pulse width of about 50 nanoseconds, which obviously does not meet the undistorted standard for human hearing. In a typical Class D amplifier, the uncorrected large signal distortion is between -35dB and -45dB, but the distortion rate increases rapidly as the signal level decreases. Several techniques have been developed to attempt to linearize the output stage circuitry to reduce distortion and improve the performance of small signals. The three main error correction techniques are as follows: (a) feedback techniques from the D-type output stage to the input integrator; (b) dummy correction pulses (eg, output of 51 nanoseconds of positive pulse) 50 nanoseconds of negative pulse to produce an effective output pulse of 1 nanosecond); and (c) Sigma-Delta noise shaping technique with feedback.

When the output stage is shaped by noise so that a wider pulse is used, the error component in the signal can be moved to above the audible frequency band by the noise shaping technique. The noise reforming technique generally produces an improvement of about 20 dB over the linear range of the signal, which is better than the improvement achieved by the pulse width modulation system alone, and the distortion component of the large signal can be adjusted to be between - 50dB to -60dB.

In the pulse width modulation system disclosed in U.S. Patent No. 6,211,728, when the system is in the third and fourth state of operation, the pulse width of the on period is proportional to the signal strength, and the off period is closed. (Off period) The current induced by the conduction pulse in the filter inductor can be cycled in one of the NMOS or PMOS components of the H-bridge circuit, that is, the conventional low-side or high-side cycle (Low /High side circulation).

The main object of the present invention is to provide a class D amplifier circuit.

The invention discloses a class D amplifier circuit comprising first and second control circuits, a load and first to sixth switching elements. The first to sixth switching elements are coupled to the load. The first and second control circuits are respectively configured to provide first and second pulse width modulation signals. The first and second switching elements each have a first end coupled to the first voltage level, a second end coupled to the load, and a control end coupled to the first control circuit. The third and fourth switching elements each have a first end coupled to the second voltage level, a second end coupled to the load, and a control end coupled to the first control circuit. The fifth and sixth switching elements each have a first end coupled to the reference voltage level, a second end coupled to the load, and a control end coupled to the second control circuit.

Certain terms are used throughout the description and following claims to refer to particular elements. Those of ordinary skill in the art should understand that a hardware manufacturer may refer to the same component by a different noun. The scope of this specification and the subsequent patent application do not use the difference of the names as the means for distinguishing the elements, but the difference in function of the elements as the criterion for distinguishing. The term "including" as used throughout the specification and subsequent claims is an open term and should be interpreted as "including but not limited to". In addition, the term "coupled" is used herein to include any direct and indirect electrical connection. Therefore, if a first device is coupled to a second device, it means that the first device can be directly electrically connected to the second device or indirectly electrically connected to the second device through other devices or connection means.

The error correction technique of the present invention is applicable to high side or low side cycle designs. For convenience of description, in the following two embodiments, the application is applied to the low-side cycle design as an example.

First embodiment

Please refer to FIG. 1, which is a schematic diagram of a class D amplifier circuit 100 according to a first embodiment of the present invention. The class D amplifier circuit 100 includes a class D amplifier 110 and a modulation circuit 120 coupled to each other. The first control circuit 112 of the class D amplifier 110 is configured to provide a first pulse width modulation (PWM) signal to the four switching elements of the class D amplifier 110, that is, four transistors MP1, MP2, MN1, MN2 to control the switching action of these switching elements. In this embodiment, the transistors MP1 and MP2 are all PMOS, and the transistors MN1 and MN2 are all NMOS. The class D amplifier 110 further includes a load 115, such as an inductor.

As shown in FIG. 1 , the source of the transistors MP1 and MP2 is coupled to a first voltage level Vcc, the drain is coupled to the load 115, and the gate is coupled to the first control circuit 112. On the other hand, the source of the transistors MN1, MN2 is coupled to a second voltage level (eg, ground level), the drain is also coupled to the load 115, and the gate is coupled to the first control circuit 112. A current is induced on the load 115, and when the class D amplifier 110 is in the off period, the current is in a circulating state, which can be modulated by changing the effective size of the modulation circuit 120 composed of the NMOS transistor. This current.

The modulation circuit 120 includes a second control circuit 122 and two switching elements, namely transistors MN3, MN4. In this embodiment, the transistors MN3, MN4 are all NMOS. In addition, as shown in FIG. 1 , the sources of the transistors MN3 and MN4 are coupled to a second voltage level (eg, a ground level), the drain is coupled to the load 115, and the gate is coupled to the second control circuit 122. Using the function of the modulation structure, the modulation circuit 120 can generate a signal between -30 dB and -70 dB. However, this range corresponds to the first order error component of a general PWM system. Therefore, the second PWM signal generated by the second control circuit 122 directly corrects the error in the first PWM signal generated by the first control circuit 112, and thus reduces the forward channel error of the entire class D amplifier circuit 100.

Traditionally, negative feedback designs have been used to further reduce the signal distortion of Class D amplifiers. However, when combined with a high-gain noise shaping modulator and its large output error, the negative feedback design is prone to oscillation of the modulator when processing small input signals, and this oscillation is often mixed with the carrier frequency to form glitch noise ( Spurs) or audio noise (tones). Because audio noise is quite easy to hear, especially the audio noise caused by small input signals or zero input signals (that is, no other mask signals exist), it is a noise that the audio amplifier is extremely avoiding. However, if the overall forward channel error can be reduced, the feedback error associated with the input signal is also reduced, which in turn reduces the oscillation tendency of the feedback loop. The oscillation trend of the feedback loop is often criticized by the sharp sounds that most Class D amplifiers can handle, especially when the input low level signal has a high level transient (such as a gunshot in a movie or The buzz in music). Therefore, the class D amplifier circuit 100 of the first embodiment of the present invention can reapply a negative feedback design without the above problems.

Second embodiment

Please refer to FIG. 2, which is a schematic diagram of a class D amplifier circuit 200 according to a second embodiment of the present invention. The difference from the first embodiment is that the modulation circuit 130 of the class D amplifier circuit 200 uses two transistors MP3, MP4, which are PMOS, as the switching elements. In addition, as shown in FIG. 2, the source of the transistors MP3 and MP4 is coupled to the first voltage level Vcc instead of the second voltage level, the drain is coupled to the load 115, and the gate is coupled to the second control circuit 132. . With the function of the modulation circuit 130, the class D amplifier circuit 200 can also improve the conventional problems and apply a design such as negative feedback.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100, 200. . . Class D amplifier circuit

110. . . Class D amplifier

112. . . First control circuit

115. . . load

120, 130. . . Modulation circuit

122, 132. . . Second control circuit

MN1~MN4, MP1~MP4. . . Transistor

1 is a schematic diagram of a class D amplifier circuit 100 of a first embodiment of the present invention.

2 is a schematic diagram of a class D amplifier circuit 200 of a second embodiment of the present invention.

100. . . Class D amplifier circuit

110. . . Class D amplifier

112. . . First control circuit

115. . . load

120. . . Modulation circuit

122. . . Second control circuit

MN1~MN4, MP1~MP2. . . Transistor

Claims (6)

A class D amplifier circuit includes: a first control circuit for providing a first pulse width modulation (PWM) signal; a load; a first switching element having a first end, a second end and a control end, the first end is coupled to a first voltage level, the second end is coupled to the load, the control end is coupled to the first control circuit and receives the first PWM signal; The second switching element has a first end, a second end, and a control end, the first end is coupled to the first voltage level, the second end is coupled to the load, and the control end is coupled to the first The control circuit receives the first PWM signal; a third switching element has a first end, a second end, and a control end, the first end is coupled to a second voltage level, and the second end is coupled The first control circuit is coupled to the first control circuit and receives the first PWM signal. The fourth switching element has a first end, a second end, and a control end. The first end is coupled to the first end. a second voltage level, the second end is coupled to the load, the control end is coupled to the first control circuit and receives the a second control circuit for providing a second PWM signal; a fifth switching element having a first end, a second end, and a control end, the first end coupled to a reference voltage a second end coupled to the load, the control end coupled to the second control circuit and receiving the second PWM signal; and a sixth switching element having a first end, a second end, and a control end The first end is coupled to the reference voltage level, and the second end is coupled to the negative The control terminal is coupled to the second control circuit and receives the second PWM signal. The class D amplifier circuit of claim 1, wherein the first and second switching elements are PMOS transistors, and the first ends of the first and second switching elements are sources, The second ends of the first and second switching elements are drains, and the control terminals of the first and second switching elements are gates. The class D amplifier circuit of claim 1, wherein the third and fourth switching elements are NMOS transistors, and the first ends of the third and fourth switching elements are sources, The second ends of the third and fourth switching elements are drains, and the control terminals of the third and fourth switching elements are gates. The class D amplifier circuit of claim 1, wherein the reference voltage level is the second voltage level, the fifth and sixth switching elements are NMOS transistors, and the fifth and sixth switches The first ends of the components are sources, and the second ends of the fifth and sixth switching elements are drains, and the control terminals of the fifth and sixth switching components are gates. The class D amplifier circuit of claim 1, wherein the load is an inductive component. For example, the class D amplifier circuit described in claim 1 is Wherein the reference voltage level is the first voltage level, the fifth and sixth switching elements are PMOS transistors, and the first ends of the fifth and sixth switching elements are sources, and the fifth The second ends of the sixth switching element are drain electrodes, and the control terminals of the fifth and sixth switching elements are gates.