TWI498980B - Semiconductor wafer and method of forming sacrificial bump pad for wafer probing during wafer sort test - Google Patents

Description

Semiconductor wafer and method of forming sacrificial bump pads for wafer probing during wafer sorting testing

The present invention relates to a semiconductor device.

Semiconductor devices are commonly found in modern electronic products. The number and density of electrical components of a semiconductor device can vary. Discrete semiconductor devices typically contain one type of electrical component, such as a light emitting diode (LED), a small signal transistor, a resistor, a capacitor, an inductor, and a power metal oxide semiconductor field effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, charge coupled devices (CCDs), solar cells, and digital micromirror devices (DMDs).

Semiconductor devices perform many functions, such as high speed computing, transceiving electromagnetic signals, controlling electronics, converting daylight into electricity, and establishing a video projection of a television display. Semiconductor devices are found in the fields of entertainment, communications, power conversion, networking, computers, and consumer products. Semiconductor devices are also found in military applications, aerospace, automotive, industrial controllers and office equipment.

Semiconductor devices utilize the electrical properties of semiconductor materials. The atomic structure of the semiconductor material allows its conductivity to be manipulated by applying an electric field or via a doping process. The doping introduces impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor device.

Semiconductor devices contain active and passive electrical structures. Active structures (including bipolar transistors and field effect transistors) control current flow. The transistor promotes or limits current flow by varying the degree of doping and applying an electric or base current. Passive structures (including resistors, capacitors, and inductors) establish a relationship between voltage and current that is necessary to perform a variety of electrical functions. The passive structure is electrically coupled to the active structure to form a circuit, thereby enabling the semiconductor device to perform high speed calculations and other useful functions.

Semiconductor devices are typically fabricated using two complex manufacturing processes (i.e., front end manufacturing and back end manufacturing), each of which potentially includes hundreds of steps. Front end fabrication involves forming a plurality of dies on the surface of a semiconductor wafer. Each die is typically identical and contains circuitry formed by electrically connecting the active component to the passive component. Back end manufacturing involves cutting a finished wafer into individual dies and encapsulating the dies to provide structural support and environmental isolation.

One of the goals of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, are more efficient, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is required for smaller end products. Smaller grain sizes can be achieved by improved front-end processes, resulting in die with smaller, higher density active and passive components. The backend process can produce a semiconductor device package with a small footprint by modifying electrical interconnects and packaging materials.

FIG. 1 illustrates a conventional semiconductor wafer 10 containing a plurality of semiconductor dies 12. Wafer 10 can be made of a semiconductor substrate such as tantalum, niobium, gallium arsenide, indium phosphide or tantalum carbide. Each of the semiconductor dies 12 has active and passive devices, conductive layers, and dielectric layers formed in accordance with the electrical design of the dies in its active surface. In one embodiment, the semiconductor die contains a fundamental frequency analog circuit or a digital circuit such as a digital signal processor (DSP), memory or other signal processing circuit. Semiconductor die 12 may also contain integrated passive devices (IPD) for radio frequency (RF) signal processing, such as inductors, capacitors, and resistors.

The semiconductor die 12 has a flip chip type semiconductor device in which a bump pad 14 is formed on an active surface. The bump pads 14 provide electrical interconnections between the conductive layers in the semiconductor die 12 and the active and passive circuit components. Solder bumps are typically formed on the bump pads 14 to electrically interconnect the semiconductor die 12 with printed circuit boards (PCBs) and other electrical devices after the wafer is single cut.

Wafer testing is an important part of the manufacturing process to confirm the continuity, electrical parameters, and functional operation of the semiconductor die 12. This failure is more costly when identifying bad grains at the wafer level and removing them from the manufacturing process to avoid failures in higher-level systems, such as multi-die packages and PCBs.

2 shows a conventional wafer probe test configuration for semiconductor wafer 10. Wafer 10 is affixed to wafer handler 16 which provides movement of the wafer in the x, y, and z directions for testing purposes. The wafer 10 is manipulated such that the test probe 18 with the finger or stylus 20 electrically contacts the bump pad 14. The computer test system 22 transmits and receives electrical signals to the bump pads 14 via the test probes 18 and the fingers 20. Computer test system 22 tests the continuity, electrical parameters, and functional operation of semiconductor die 12 via bump pads 14. If the computer test system 22 detects a test failure, it is identified as a defective semiconductor die and subsequently removed from the manufacturing process.

The bump pad 14 has a small area and is about 50-500 micrometers (μm) in diameter. The finger 20 typically has a pointed tip to enable reliable electrical connection to the bump pad 14. During wafer probe testing, the finger 20 is known to penetrate the surface and damage the bump pads 14. In practice, the wafer probe test can include pulling the finger 20 across the bump pad 14, resulting in scratches on the surface of the bump pad. The wafer probe test leaves a finger mark in the bump pad, resulting in subsequent solder bump formation. To avoid damage to the bump pads 14, wafer probe testing has been performed after the solder bumps 24 are formed, as shown in FIG.

In most commercial contracts, the wafer foundry is held by its consumers to remain responsible for the wafer until the wafer classification test is completed to ensure adequate yield. Due to the potential for bump pad damage, many foundries perform wafer probing after solder bumps are formed on the bump pads. Wafers can be sold or wafer transferred after wafer sorting and testing, and wafer sorting tests can be performed until the bumps are formed. However, wafer inspection is required to limit the competition of third-party bump formation service providers after bump formation. If wafer probing can occur prior to bump formation without damaging the bump pads, the foundry can sell bumpless wafers and other companies can participate in providing bump forming services.

Wafer probe testing needs to be performed prior to bump formation without damaging the interconnect bump pads. Accordingly, in one embodiment, the present invention is a method of fabricating a semiconductor device comprising the steps of: providing a semiconductor wafer comprising a plurality of semiconductor dies, forming a plurality of interconnecting bump pads on the semiconductor die, Forming a plurality of sacrificial bump pads adjacent to the interconnect bump pads, forming a conductive link between each interconnect bump pad and the adjacent sacrificial bump pads, and electrically forming the bumps on the interconnect bump pads Contact the sacrificial bump pad for wafer probing.

In another embodiment, the present invention is a method of fabricating a semiconductor device comprising the steps of: providing a semiconductor wafer comprising a plurality of semiconductor dies and simultaneously forming a plurality of interconnect bump pads on the semiconductor dies , a plurality of sacrificial bump pads and a conductive link. The sacrificial bump pads are disposed adjacent to the interconnect bump pads. A conductive link electrically connects each of the interconnect bump pads to the adjacent sacrificial bump pads. The method further includes the step of wafer probing by electrically contacting the sacrificial bump pads.

In another embodiment, the present invention is a method of fabricating a semiconductor device, comprising the steps of: providing a semiconductor wafer comprising a plurality of semiconductor dies, forming a pattern in a bump pad array on the semiconductor die Interconnecting bump pads, forming a sacrificial bump pad in the bump pad array, forming a conductive link between the interconnect bump pad and the sacrificial bump pad, and electrically contacting the sacrificial bump pad Perform wafer inspection.

In another embodiment, the invention is a semiconductor wafer comprising a plurality of semiconductor dies, the dies comprising an interconnecting bump pads formed on the semiconductor dies in an array of bump pads. A sacrificial bump pad is formed in the bump pad array. A conductive link is formed between the interconnect bump pad and the sacrificial bump pad.

The invention is described in the following description with reference to the drawings, in which FIG. Although the present invention has been described in terms of the best mode of the present invention, it is understood that the invention is intended to cover alternatives and modifications as may be included in the spirit and scope of the invention as defined by the appended claims. And equivalents and equivalents thereof as supported by the following disclosure and drawings.

Semiconductor devices are typically fabricated using two complex manufacturing processes: front end manufacturing and back end manufacturing. Front end fabrication involves forming a plurality of dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components such as transistors and diodes have the ability to control the flow of current. Passive electrical components such as capacitors, inductors, resistors, and transformers establish a relationship between voltage and current that is necessary to perform circuit functions.

The passive and active components are formed on the surface of the semiconductor wafer by a series of processing steps including doping, deposition, photolithography, etching, and planarization. Doping introduces impurities into the semiconductor material by techniques such as ion implantation or thermal diffusion. The doping process changes the conductivity of the semiconductor material in the active device, thereby converting the semiconductor material into an insulator, a conductor, or dynamically changing the conductivity of the semiconductor material in response to an electric field or base current. The transistor contains regions of varying doping type and extent that are configured as needed to enable the transistor to promote or limit current flow when an electric or base current is applied.

Active and passive components are formed from layers of material having different electrical properties. The layers can be formed by a variety of deposition techniques (partly determined by the type of material being deposited). For example, thin film deposition may include chemical vapor deposition (CVD), physical vapor deposition (PVD), electrolytic plating, and electroless plating processes. The layers are typically patterned to form active components, passive components, or portions of electrical connections between the components.

The layer can be patterned using photolithography, including depositing a photosensitive material, such as a photoresist, onto the layer to be patterned. The pattern is transferred from the photomask to the photoresist using light. The portion of the exposed photoresist pattern is removed using a solvent to expose portions of the layer to be patterned. The rest of the photoresist is removed to obtain a patterned layer thereunder. Alternatively, some types of materials are patterned using techniques such as electroless plating and electrolytic plating by depositing materials directly into regions or voids formed by previous deposition/etch processes.

Depositing a thin film of material on an existing pattern magnifies the underlying pattern and creates a non-uniform flat surface. The production of smaller and densely packed active and passive components requires a uniform flat surface. Flattening can be used to remove material from the wafer surface and create a uniform flat surface. Flattening involves polishing the wafer surface with a polishing pad. Abrasive materials and corrosive chemicals are added to the wafer surface during polishing. The abrasive mechanical action in combination with chemical corrosive action removes any irregular surface configuration resulting in a uniform flat surface.

Back end manufacturing refers to cutting or simply cutting a finished wafer into individual dies and then encapsulating the dies for structural support and environmental isolation. This results in a single-cut grain that scratches and cuts the wafer along a non-functional area of the wafer (called a scribe line or scribe line). Use a laser cutting tool or saw blade to cut the wafer. After a single cut, the individual die are mounted on a package substrate that includes pins or contact pads for interconnection with other system components. The contact pads formed on the semiconductor die are then bonded to contact pads in the package. The electrical connection may be formed by solder bumps, stud bumps, conductive paste or wire bonds. A sealant or other forming material is deposited on the package to provide physical support and electrical insulation. The finished package is then inserted into an electrical system and the functionality of the semiconductor device is available to other system components.

4 illustrates an electronic device 50 having a plurality of wafer carrier substrates or PCBs 52 adhered to a semiconductor package on its surface. Depending on the application, electronic device 50 can have one type of semiconductor package or multiple types of semiconductor packages. Different types of semiconductor packages are shown in Figure 4 for illustrative purposes.

Electronic device 50 can be a separate system that performs one or more electrical functions using a semiconductor package. Alternatively, electronic device 50 can be a sub-assembly of a larger system. For example, the electronic device 50 can be a graphics card, a network interface card, or other signal processing card that can be inserted into a computer. Semiconductor packages may include microprocessors, memories, special application integrated circuits (ASICs), logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor die or electrical components.

In FIG. 4, PCB 52 provides an electrical interconnection for a structurally supported general purpose substrate and a semiconductor package secured to the PCB. Conductive signal traces 54 are formed on or in one of the surfaces of PCB 52 using evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition process. Signal traces 54 provide electrical communication between each of the semiconductor package, the fixed components, and other external system components. Trace 54 also provides power and ground to each semiconductor package.

In some embodiments, a semiconductor device has a two-stage package. The first stage of packaging is a technique for mechanically attaching and electrically attaching semiconductor dies to an intermediate carrier. The second level package includes mechanically attaching and electrically attaching the intermediate carrier to the PCB. In other embodiments, a semiconductor device may only have a first level package in which the die is directly mechanically bonded and electrically bonded to the PCB.

For purposes of illustration, several types of first level packages, including wire bond packages 56 and flip chips 58, are shown on PCB 52. In addition, several types of second level packages, such as a ball grid array (BGA) 60, a bump wafer carrier (BCC) 62, a dual row package (DIP) 64, and a platform grid, are shown that are fixed to the PCB 52. Array (LGA) 66, multi-chip module (MCM) 68, quad flat no-lead package (QFN) 70, and quad flat pack 72. Depending on system requirements, any combination of semiconductor packages, any combination of first and second level package types, and configurations of other electronic components can be coupled to PCB 52. In some embodiments, electronic device 50 includes a single attached semiconductor package; while other embodiments require multiple interconnect packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate prefabricated components into electronic devices and systems. Since semiconductor packages include complex functions, electronic devices can be fabricated using less expensive components and streamlined manufacturing processes. The resulting device is less likely to fail and is less expensive to manufacture, thereby reducing consumer costs.

Figures 5a-5c show an exemplary semiconductor package. Figure 5a illustrates in further detail the DIP 64 that is attached to the PCB 52. The semiconductor die 74 includes an active region including an analog circuit or a digital circuit formed in the die to perform as an active device, a passive device, a conductive layer, and a dielectric layer, and is designed according to the electric power of the die. And electrical interconnection. For example, the circuit can include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit components formed within the active region of the semiconductor die 74. The contact pad 76 is one or more layers of a conductive material such as aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), or silver (Ag), and is electrically connected to the semiconductor crystal. Circuit elements formed within the particles 74. During assembly of the DIP 64, the semiconductor die 74 is secured to the intermediate carrier 78 using a gold-germanium eutectic layer or a bonding material such as a thermal epoxy. The package body includes an insulating encapsulation material such as a polymer or ceramic. Conductor 80 and bond wire 82 provide electrical interconnection between semiconductor die 74 and PCB 52. Encapsulant 84 is deposited on the package to prevent ambient moisture and particles from entering the package and contaminating die 74 or bond wire 82.

Figure 5b illustrates in further detail the BCC 62 that is attached to the PCB 52. The semiconductor die 88 is secured to the carrier 90 using a primer or epoxy bonding material 92. Wire bond 94 provides a first level package interconnect between contact pads 96 and 98. A molding compound or encapsulant 100 is deposited over the semiconductor die 88 and bond wires 94 to provide physical support and electrical isolation to the device. Contact pads 102 are formed on one surface of PCB 52 using a suitable metal deposition method such as electrolytic plating or electroless plating to prevent oxidation. Contact pad 102 is electrically coupled to one or more conductive signal traces 54 in PCB 52. Bumps 104 are formed between contact pads 98 of BCC 62 and contact pads 102 of PCB 52.

In FIG. 5c, the semiconductor die 58 is fixed to the intermediate carrier 106 face down in a planar first-level package. The active region 108 of the semiconductor die 58 contains an analog circuit or a digital circuit that is implemented in the form of an active device, a passive device, a conductive layer, and a dielectric layer formed in accordance with the electrical design of the die. For example, the circuit can include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit components within active region 108. Semiconductor die 58 is electrically and mechanically coupled to carrier 106 via bumps 110.

The BGA 60 is electrically and mechanically connected to the PCB 52 using bumps 112 in a BGA type second level package. Semiconductor die 58 is electrically coupled to conductive signal traces 54 in PCB 52 via bumps 110, signal lines 114, and bumps 112. A molding compound or encapsulant 116 is deposited over the semiconductor die 58 and carrier 106 to provide physical support and electrical isolation to the device. The flip chip semiconductor device provides a short conductive path from the active device on the semiconductor die 58 to the conductive traces on the PCB 52 to reduce signal propagation distance, reduce capacitance, and improve overall circuit performance. In another embodiment, the semiconductor die 58 can be directly mechanically and electrically connected to the PCB 52 using a flip-chip first level package without the intermediate carrier 106.

FIG. 6 illustrates a semiconductor wafer 150 having a plurality of semiconductor dies 152. Wafer 150 may be fabricated from a semiconductor substrate having a diameter in the range of 150-300 millimeters (mm), such as germanium, antimony, gallium arsenide, indium phosphide or tantalum carbide. Each semiconductor die 152 has active and passive devices, conductive layers, and dielectric layers formed in the active surface 154 in accordance with the electrical design of the die. In one embodiment, semiconductor die 152 includes a baseband analog circuit or a digital circuit, such as a digital signal processor (DSP), ASIC, memory, or other signal processing circuit. Semiconductor die 152 may also contain IPDs for RF signal processing, such as inductors, capacitors, and resistors.

In one embodiment, semiconductor die 152 is a flip chip type semiconductor device having interconnecting bump pads 160 formed on active surface 154. The bump pads 160 are patterned and deposited using PVD, CVD, sputtering, electrolytic plating, electroless plating processes, or other suitable metal deposition processes. The bump pads 160 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive material. Bump pads 160 are disposed within bump pad array 162 to provide electrical interconnections to the conductive layers within the semiconductor die 152 as well as the active and passive circuit components. The bump pad 160 is small in area and has a diameter of about 50 to 500 micrometers (μm).

A plurality of sacrificial bump pads 164 are formed on the active surface 154. The bump pads 164 are patterned and deposited using PVD, CVD, sputtering, electrolytic plating, electroless plating processes, or other suitable metal deposition processes. The bump pads 164 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive material. The sacrificial bump pads 164 can have an area that is less than or greater than the interconnect bump pads 160. In general, the sacrificial bump pads 164 are approximately the diameter of the interconnect bump pads 160 or the diameter of the wafer probe test.

7a-7b illustrate top and cross-sectional views of a portion of a semiconductor wafer 150 showing the bump pad array 162 of the semiconductor die 152 in further detail. The sacrificial bump pads 164 are disposed in a gap with the array of interconnect bump pads 160. There is one sacrificial bump pad 164 for each interconnect bump pad 160. Each sacrificial bump pad 164 is positioned adjacent to the respective interconnect bump pad 160. In one embodiment, the sacrificial bump pads 164 are disposed at a diagonal offset relative to the respective interconnect bump pads 160, such as a bump pad diameter above and to the right, as shown in FIG.

Conductive link 166 is formed on active surface 154 between PV bump pad 160 and sacrificial bump pad 164 using PVD, CVD, sputtering, electrolytic plating, electroless plating processes, or other suitable metal deposition process patterning. . Conductive link 166 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive link 166 electrically interconnects interconnect bump pads 160 with sacrificial bump pads 164. Sacrificial bump pads 164 and conductive links 166 may be formed simultaneously with interconnect bump pads 160 or during bump formation, thereby avoiding separate processing steps and simplifying fabrication.

FIG. 8 shows a wafer level probe test configuration for semiconductor wafer 150. The semiconductor die 152 is in the form of a wafer during probe testing, that is, prior to single cut. Wafer level testing confirms the continuity, electrical parameters, and functionality of individual semiconductor dies. Each semiconductor die 152 that is probed by the wafer is classified as a good bare die (KGD). Wafer probing can also perform trimming operations based on test results to adjust component values, such as resistor trimming. The defective semiconductor die identified by the wafer probe test can be removed from the fabrication process prior to assembly at a higher level (eg, multi-die package and PCB).

The semiconductor wafer 150 is affixed to the wafer handler 170 under vacuum pressure. Wafer manipulator 170 provides wafer movement in the x, y, and z directions for testing purposes. In one embodiment, wafer classification is used to organize and manipulate the wafer for testing. A plurality of semiconductor wafers 150 are placed on a wafer for efficient disposal.

Test probe 172 includes a PCB having a plurality of fingers or styli 174 extending radially inward from the PCB to match the tight geometry of bump pad array 162. The fingers 174 are typically made of tungsten and other metals having good electrical and mechanical properties. The fingers 174 have a pitch of 20-30 μm. Each finger 174 is directed toward the distal end to provide a reliable electrical connection with the associated sacrificial bump pad 164 on the bump pad array 162. The PCB of test probe 172 includes an electrical trace that is connected to finger 174, which in turn is coupled to computer test system 176. Computer test system 176 generates and receives test signals for semiconductor die 152 to confirm its continuity, electrical parameters, and electrical functionality. Test probe 172 can contact one or more semiconductor dies 152 on wafer 150. In one embodiment, test probe 172 contacts a semiconductor die 152 and then moves to the next die. Alternatively, test probe 172 can contact all of semiconductor die 152 to test the integrity of wafer 150. Computer test system 176 also controls the movement of wafer handler 170. During wafer sorting, wafers 150 are loaded and unloaded from the wafer and compared using automated pattern recognition for testing.

For wafer sorting testing, the wafer handler 170 is manipulated by the computer test system 176 to force the fingers 174 into compression engagement with the sacrificial bump pads 164. An electrical test signal is generated by computer test system 176 that is sent to sacrificial bump pad 164 via test probe 172 and contact fingers 174. The electrical test signal is also sent by conductive link 166 to interconnect bump pad 160. Depending on the tests performed, the semiconductor die 152 processes the electrical test signal over an operating temperature range. The test result signal is returned to computer test system 176 via interconnect bump pad 160, conductive link 166, sacrificial bump pad 164, finger 174, and test probe 172. Depending on the test results, each semiconductor die 152 is classified as KGD or identified as defective. If the computer test system 176 detects a test failure, the defective semiconductor die is identified by ink dots or recorded in a computer test system for subsequent removal from the manufacturing process.

The finger 174 typically has a pointed tip to enable reliable electrical connection to the bump pad 164. During wafer probe testing, the fingers 174 are known to penetrate the surface and may damage the bump pads. In effect, the wafer probe test can include pulling the finger 174 across the bump pad 164, resulting in scratches on the surface of the bump pad. However, since the wafer probing is performed on the sacrificial bump pads 164, the interconnect bump pads 160 remain in an undamaged initial state for subsequent bump formation.

In FIG. 9, one portion of the sacrificial bump pads 164 and conductive links 166 are optionally removed by a wet etch or dry etch process. In an embodiment, the sacrificial bump pads 164 and the portion of the conductive links 166 are removed during an etch step that forms part of the interconnect bump pads 160. The interconnected bump pads 160 and the residual truncated portions of the conductive links 166 can be utilized by the bump process. Since wafer probing has not been performed on the interconnect bump pads 160, the bump pads are in an initial state for forming bumps. Wafer foundries can perform wafer sorting tests on bumpless wafers and sell or otherwise transfer responsibility for KGD-free bump-free wafers. Any third party bump forming service provider can then form bumps on bumpless wafers having KGD identified by wafer sorting testing.

The conductive material is deposited on the interconnect bump pads 160 using evaporation, electrolytic plating, electroless plating, ball drop or screen printing processes. The conductive material may be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, optionally containing a fluxing material. For example, the conductive material can be eutectic Sn/Pb, high lead solder, or lead free solder. The electrically conductive material is soldered to the interconnect bump pads 160 using a suitable attachment or soldering process. In one embodiment, the material is reflowed by heating the conductive material above its melting point to form a spherical sphere or bump 180. In some applications, the bumps 180 are secondarily reflowed to improve electrical contact with the interconnect bump pads 160. The bumps may also be compression welded to the interconnect bump pads 160. Bumps 180 represent one type of interconnect structure that can be formed on interconnect bump pads 160. The interconnect structure can also use bond wires, conductive pastes, stud bumps, microbumps, or other electrical interconnects.

10a-10b illustrate top and cross-sectional views of semiconductor die 152 with bumps 180 formed on interconnect bump pads 160. The residual truncated portion of the conductive link 166 has no electrical effect on the bump 180 or the interconnect bump pad 160.

Although one or more embodiments of the present invention have been described in detail, it will be understood by those skilled in the art that the embodiments may be modified and modified without departing from the scope of the invention as set forth in the following claims Transformation.

10. . . Semiconductor wafer

12. . . Semiconductor grain

14. . . Bump pad

16. . . Wafer controller

18. . . Test probe

20. . . Finger or stylus

twenty two. . . Computer test system

twenty four. . . Solder bump

50. . . Electronic device

52. . . PCB

54. . . Trace

56. . . Wire bond package

58. . . Flip chip

60. . . Spherical grid array

62. . . Bump wafer carrier

64. . . Double row package

66. . . Platform grid array

68. . . Multi-chip module

70. . . Quad flat no-lead package

72. . . Quad flat package

74. . . Semiconductor grain

76. . . Contact pad

78. . . Intermediate carrier

80. . . wire

82. . . Welding wire

84. . . Sealants

88. . . Semiconductor grain

90. . . Carrier

92. . . Primer or epoxy bonding material

94. . . Welding wire

96. . . Contact pad

98. . . Contact pad

100. . . Molding compound or sealant

102. . . Contact pad

104. . . Bump

106. . . Carrier

108‧‧‧active area

110‧‧‧Bumps

112‧‧‧Bumps

114‧‧‧ signal line

116‧‧‧Forming compounds or sealants

150‧‧‧Semiconductor Wafer

152‧‧‧Semiconductor grains

154‧‧‧Active surface

160‧‧‧Bump pad

162‧‧‧Bump pad array

164‧‧‧Bump pad

166‧‧‧conductive links

170‧‧‧Wafer Manipulator

172‧‧‧Test probe

174‧‧‧ finger

176‧‧‧Computer Test System

180‧‧‧Spherical spheres or bumps

Figure 1 illustrates a conventional semiconductor wafer having a plurality of dies containing bump pads;

2 is a conventional wafer probing test configuration on a bump pad;

Figure 3 is a conventional wafer probing test configuration on a solder bump;

Figure 4 illustrates a PCB in which different types of packages are adhered to their surface;

Figures 5a-5c illustrate in further detail a representative semiconductor package adhered to a PCB;

6 illustrates a semiconductor wafer having a plurality of dies having interconnected bump pads and sacrificial bump pads interconnected via conductive links;

Figures 7a-7b further illustrate interconnecting bump pads and sacrificial bump pads interconnected via conductive links;

8 is a wafer probing test configuration of a semiconductor die having a sacrificial bump pad;

Figure 9 illustrates the wafer after removal of the sacrificial bump pads; and

10a-10b illustrate wafers with bumps formed on interconnect bump pads after the sacrificial bump pads are removed.

150. . . Semiconductor wafer

152. . . Semiconductor grain

154. . . Active surface

160. . . Bump pad

162. . . Bump pad array

164. . . Bump pad

166. . . Conductive link

Claims (14)

A method of fabricating a semiconductor device, comprising: providing a semiconductor wafer including a plurality of semiconductor dies; forming a plurality of interconnect bump pads on the semiconductor die; on an active surface of the semiconductor die and at the Forming a plurality of sacrificial bump pads adjacent to the interconnect bump pads; forming a conductive link between each interconnect bump pad and the adjacent sacrificial bump pads; borrowing before forming the bumps on the interconnect bump pads Wafer detection is performed by electrically contacting the sacrificial bump pads; and after wafer inspection, the semiconductor wafer is transferred to a third party without bumps. The method of claim 1, further comprising forming the sacrificial bump pads diagonally offset relative to the interconnecting bump pads. The method of claim 1, further comprising simultaneously forming the sacrificial bump pads, the interconnect bump pads, and the conductive links. The method of claim 1, further comprising removing the sacrificial bump pads and a portion of the conductive links after wafer inspection. The method of claim 1, wherein the sacrificial bump pads have a different diameter than the interconnecting bump pads. A method of fabricating a semiconductor device, comprising: providing a semiconductor wafer including a plurality of semiconductor dies; forming an interconnect bump pad on the semiconductor die in an array of bump pads; Forming a sacrificial bump pad in the bump pad array and electrically connecting to the interconnect bump pad; performing wafer detection by electrically contacting the sacrificial bump pad not in contact with the interconnect bump pad; The sacrificial bump pads are removed from the semiconductor die by an etch process. The method of claim 6, further comprising removing the sacrificial bump pad after wafer inspection. The method of claim 6, further comprising simultaneously forming the sacrificial bump pad and the interconnect bump pad. The method of claim 6, further comprising positioning the sacrificial bump pad at a position that is diagonally offset relative to the interconnecting bump pad. The method of claim 6, further comprising transferring the semiconductor wafer to a third party after detecting the wafer without bumps. A semiconductor device comprising: a semiconductor die; an interconnect bump pad formed on the semiconductor die; a sacrificial bump pad formed on a surface of the semiconductor die and electrically connected to the Interconnecting the bump pads and diagonally offset from the interconnect bump pads; and a wafer probing electrically contacting the sacrificial bump pads that are not in contact with the interconnect bump pads. The semiconductor device of claim 11, further comprising a bump formed on the interconnect bump pad. Such as the patent device of claim 11 of the semiconductor device, wherein the sacrifice The bump pads and the interconnect bump pads are formed simultaneously. The semiconductor device of claim 11, further comprising a conductive link formed between the interconnect bump pad and the sacrificial bump pad.