TWI494756B - Method for giving read commands, flash memory controller and flash memory storage system using the same - Google Patents

Description

Method for issuing read commands, flash memory controller and flash memory storage system

The present invention relates to a method of issuing a read command to a flash memory and a flash memory controller and a flash memory storage system using the same.

Because Flash Memory has the characteristics of non-volatile data, power saving, small size and no mechanical structure, it is most suitable for battery-operated portable electronic products. For example, a solid state hard disk is a storage device that uses NAND flash memory as a storage medium, and has been widely deployed in notebook computers as a main storage device.

1 is a schematic block diagram showing a general flash memory storage device. Generally, when the host system 110 is coupled to the flash memory storage device 120 through the connector 122 and wants to read the data stored in the flash memory storage device 120, the host system 110 is from the flash memory storage device. The program for reading data in the flash memory chip 126 of 120 can be divided into data upload (load), internal data transfer (transfer) and external data transmission. Specifically, when the host system 110 wants When the data is read from the flash memory storage device 120, the flash memory controller 124 issues a general read command to the flash memory chip 126, at which time the flash memory chip 126 will be in accordance with the normal read command. The data is transferred from the memory cell (i.e., storage area) 134 to the buffer 132 within the flash memory chip 126. This process is referred to as data upload. For example, when the flash memory controller 124 receives a host read command from the host system 110, the flash memory controller 124 issues a command to the flash memory chip 126 by "command C1", "physical address" and A general read command consisting of a string such as "instruction C2", wherein "instruction C1" is used to indicate that the flash memory chip is ready to execute a read program, and "physical address" is used to indicate that the flash memory chip is to be read. The address "Command C2" is used to instruct the flash memory chip to move data from the memory cell 134 to the buffer 132. At this time, the flash memory chip 126 moves the data from the memory cell 134 to the buffer 132 in accordance with the "physical address" in the general read command.

After the data upload is completed, the data temporarily stored in the buffer 132 is transferred to the flash memory controller 124 (for example, the buffer memory disposed in the flash memory controller 124). This process is called Internal data transfer.

Finally, the flash memory controller 124 transmits the received data to the host system 110 through the connector 122. This process is referred to as external data transmission. In particular, during data uploading and internal data transfer, the flash memory controller 124 is in a busy state after the general read command is issued, and when the flash memory is flashed. The flash memory controller 124 is unable to issue any instructions to the flash memory controller 124 while it is busy. That is, the flash memory controller 124 must complete the data from the flash memory chip 126. After the internal data transfer to the flash memory controller 124 is transmitted, the flash memory controller 124 can again issue the next instruction to the flash memory chip 126. For example, the flash memory controller 124 must first access the flash memory chip when reading data from two consecutive logical addresses (ie, two pages) in response to a host read command from the host system 110. 126 releases the first general read command consisting of a string of "command C1", "physical address" and "command C2" to upload the data of the first page, and then performs internal data transfer to The read data of the first page is transferred to the flash memory controller 124, and then the second word "instruction C1", "physical address" and "command C2" are issued to the flash memory chip 126. The general read command consisting of the strings is used to upload the data of the second page, and finally the internal data transfer is performed to transfer the data of the read second page to the flash memory controller 124. In other words, even if the data to be read is stored in consecutive logical addresses, the flash memory controller 124 must also repeat the strings of "instruction C1", "physical address" and "command C2". The general read command is composed to read data from the flash memory chip.

With the development of transmission technology, the transmission speed of connectors has been greatly improved. For example, Serial Advanced Technology Attachment (SATA) connectors can reach Gigabit (Gb) per second, even per second. 30Gb. However, in the above data uploading and internal data transmission speed is lower than the speed of the connector, the overall storage performance can not be effectively improved, so how to shorten the execution time of the host read command is a goal of the technicians in this field.

The present invention provides a method of issuing a read command that can effectively shorten the time for executing a host read command.

The present invention provides a flash memory controller capable of effectively shortening the time for executing a host read command.

The present invention provides a flash memory storage system capable of effectively shortening the time for executing a host read command.

The present invention provides a data reading method capable of effectively shortening the time for executing a host read command.

An exemplary embodiment of the present invention provides a method for issuing a read command for reading data to be accessed by a host system from a flash memory chip. The method of presenting the read command includes providing a flash memory controller and receiving a host command from the host system, wherein the host command is a host read command and the host command includes a first start logical address. The method for issuing the read command further includes: the flash memory controller issues a general read command and at least one cache read command to the flash memory chip according to the host command to perform the mapping from the flash memory chip. The physical address of the first starting logical address begins to sequentially read the first data of the corresponding host instruction, and the flash memory controller issues at least one cache read command to the flash memory chip to be at the first The second data that is not requested by the host command is read from the flash memory chip during at least a portion of the data is transferred to the flash memory controller, wherein the physical address of the second data stored in the memory chip is continued The physical address where the first data is stored. The method of releasing the read command also includes receiving the next one from the host system. A host instruction, wherein the next host instruction includes a second starting logical address. The method for issuing the read command further includes determining whether the next host command is a host read command and whether the next host command is connected to the host command, and when the next host command is a host read command and the next host command In order to continue the above host command, the flash memory controller directly issues at least one cache read command to the flash memory chip according to the next host command.

In an embodiment of the present invention, when the next host command is a host read command and the next host command is not connected to the host command, the flash memory controller issues a flash memory chip to the flash memory chip. Resetting the instruction, and then issuing a general read command and at least one cache read command to the flash memory chip to start from the physical address of the second start logical address in the flash memory chip The third data corresponding to the next host command is read sequentially.

In an embodiment of the invention, when the next host command is not a host read command, a flash command is issued by the flash memory controller to the flash memory chip.

In an embodiment of the present invention, the step of determining whether the next host command is connected to the host command comprises: determining whether the second start logical address is connected to a physical address storing the first data The logical address is mapped, and when the second starting logical address is connected to the logical address mapped by the physical address storing the first data, it is determined that the next host command is connected to the host command.

In an embodiment of the present invention, the step of determining whether the next host command is connected to the host command comprises: determining a second start logic bit Whether the address is the same as the logical address mapped by the physical address storing the second data, and when the second starting logical address is the same as the logical address mapped by the physical address storing the second data, The next host command is connected to the host command.

In an embodiment of the invention, the method for subscribing to the read command further includes determining a logic corresponding to the first start logical address before reading the second data of the non-host instruction request from the flash memory chip. Whether the block is in a state of opening the mother and child block, wherein the non-host command request is read from the flash memory chip only when the logical block corresponding to the first start logical address is not in the state of the open parent block Two materials.

An exemplary embodiment of the present invention provides a flash memory controller for reading data to be accessed by a host system from a flash memory chip. The flash memory controller includes a microprocessor unit, a flash memory interface unit, a host interface unit, a buffer memory and a memory management unit. The flash memory interface unit is coupled to the microprocessor unit and is configured to connect to the flash memory chip. The host interface unit is coupled to the microprocessor unit and is configured to connect to the host system. The buffer memory is coupled to the microprocessor unit and is used to temporarily store data. The memory management unit is coupled to the microprocessor unit and configured to receive a host command from the host system through the host interface unit, wherein the host command is a host read command and the host command includes a first start logical address. In addition, the memory management unit issues a general read command and at least one cache read command to the flash memory chip through the flash memory interface unit according to the host command to start from the first in the flash memory chip. The physical address of the starting logical address begins to sequentially read a first resource corresponding to the above host instruction And the memory management unit issues at least one cache read command to the flash memory chip to read non-above host instructions from the flash memory chip during at least a portion of the first data being transferred to the buffer memory The requested second data, wherein the physical address of the second data stored in the memory chip is a physical address subsequent to storing the first data. In addition, the memory management unit receives the next host command from the host system through the host interface unit, wherein the next host command includes a second start logical address. Furthermore, the memory management unit determines whether the next host command is a host read command and whether the next host command is connected to the host command, and when the next host command is a host read command and the next one When the host command is connected to the host command, the memory management unit directly sends at least one cache read command to the flash memory chip according to the next host command through the flash memory interface unit.

In an embodiment of the present invention, when the next host command is a host read command and the next host command is not connected to the host command, the memory management unit issues a reset to the flash memory chip. Directing, and again, issuing a general read command and at least one cache read command to the flash memory chip to sequentially sequence from the physical address of the second start logical address in the flash memory chip The third data corresponding to the next host command is read.

In an embodiment of the invention, when the next host command is not a host read command, the memory management unit issues a reset command to the flash memory chip.

In an embodiment of the present invention, the foregoing memory management unit determines that Whether the second starting logical address is connected to the logical address mapped by the physical address storing the first data, wherein the second starting logical address is connected to the logical bit mapped by the physical address storing the first data At the address, the memory management unit determines that the next host command is connected to the host command.

In an embodiment of the present invention, the memory management unit determines whether the second start logical address is the same as the logical address mapped by the physical address storing the second data, where the second start logic When the address is the same as the logical address mapped by the physical address storing the second data, the memory management unit determines that the next host command is connected to the host command.

In an embodiment of the present invention, before the second data that is not the host instruction request is read from the flash memory chip, the memory management unit further determines whether a logical block corresponding to the first start logical address is in the When the parent and child block states are turned on, the memory management unit reads the non-the above host command request from the flash memory chip only when the logical block corresponding to the first start logical address is not in the open parent and child block state. The second information.

An exemplary embodiment of the present invention provides a flash memory storage system. The flash memory storage system includes a connector, a flash memory chip, and a flash memory controller. The connector is used to couple the host system. The flash memory controller is coupled to the connector and the flash memory chip, and configured to receive a host command from the host system through the connector, wherein the host command is a host read command and the host command includes a A starting logical address. In addition, the flash memory controller issues a general read command and at least one fast to the flash memory chip according to the host command. Taking a read command to sequentially read the first data corresponding to the host instruction from the physical address of the first starting logical address in the flash memory chip, and the flash memory controller flashes to the flash The memory chip issues at least one cache read command to read a second data other than the host command request from the flash memory chip during at least a portion of the first data being transferred to the flash memory controller, wherein The physical address of the second data stored in the flash memory chip is the physical address of the first data stored. Additionally, the flash memory controller receives a next host command from the host system via the connector, wherein the next host command includes a second start logical address. Furthermore, the flash memory controller determines whether the next host command is a host read command and whether the next host command is connected to the host command, and when the next host command is a host read command and the When a host command is connected to the host command, the flash memory controller directly sends at least one cache read command to the flash memory chip according to the next host command through the flash memory interface unit.

In an embodiment of the present invention, when the next host command is a host read command and the next host command is not connected to the host command, the flash memory controller issues a flash memory chip to the flash memory chip. Resetting the instruction, and then issuing a general read command and at least one cache read command to the flash memory chip to start from the physical address of the second start logical address in the flash memory chip The third data corresponding to the next host instruction is read sequentially.

In an embodiment of the present invention, when the next host command is not a host read command, the flash memory controller issues a weight to the flash memory chip. Set the instruction.

In an embodiment of the present invention, the flash memory controller determines whether the second start logical address is connected to a logical address mapped by the physical address storing the first data, wherein the second start When the logical address is connected to the logical address mapped by the physical address storing the first data, the flash memory controller determines that the next host command is connected to the host command.

In an embodiment of the present invention, the flash memory controller determines whether the second start logical address is the same as the logical address mapped by the physical address storing the second data, where the second start When the logical address is the same as the logical address mapped by the physical address storing the second data, the flash memory controller determines that the next host command is connected to the host command.

In an embodiment of the present invention, the flash memory controller further determines whether a logical block corresponding to the first start logical address is before reading the second data that is not the host instruction request from the flash memory chip. In a state in which the parent and child blocks are turned on, the flash memory controller reads the non-the above host from the flash memory chip only when the logical block corresponding to the first start logical address is not in the state of the open parent block. The second information of the instruction request.

An exemplary embodiment of the present invention provides a data reading method for reading data to be accessed by a host system from a flash memory chip. The data reading method includes providing a flash memory controller and receiving a host command from the host system, wherein the host command is a host read command and the host command includes a first start logical address. The data reading method is also included by the flash memory controller according to the above The host instruction sequentially reads the first data corresponding to the host instruction from the physical address of the first starting logical address in the flash memory chip, and the first data of the flash memory controller Reading at least a portion of the second data that is not requested by the host command from the flash memory chip during transmission to the flash memory controller, wherein the physical address of the second data stored in the flash memory chip is continued The physical address where the first data is stored. The data reading method further includes receiving a host instruction from the host system, wherein the next host instruction includes a second starting logical address. The data reading method further comprises determining whether the next host command is a host read command and whether the next host command is connected to the host command, and when the next host command is a host read command and the next host When the command is connected to the host command, the second data is transmitted to the host system by the flash memory controller.

An exemplary embodiment of the present invention provides a flash memory controller for reading data to be accessed by a host system from a flash memory chip. The flash memory controller includes a microprocessor unit, a flash memory interface unit, a host interface unit, a buffer memory and a memory management unit. The flash memory interface unit is coupled to the microprocessor unit and is configured to connect to the flash memory chip. The host interface unit is coupled to the microprocessor unit and is configured to connect to the host system. The buffer memory is coupled to the microprocessor unit and is used to temporarily store data. The memory management unit is coupled to the microprocessor unit and configured to receive a host command from the host system through the host interface unit, wherein the host command is a host read command and the host command includes a first start logical address. In addition, the memory management unit is responsive to the flash memory interface unit. According to the host command, the first data corresponding to the host instruction is sequentially read from the physical address of the first starting logical address in the flash memory chip, and the memory management unit is at least the first data. Reading a second data that is not requested by the host command from the flash memory chip during a portion of being transferred to the buffer memory, wherein the physical address of the second data stored in the flash memory chip is connected to the first data stored The physical address. In addition, the memory management unit receives a host command from the host system through the host interface unit, wherein the next host command includes a second start logical address. Furthermore, the memory management unit determines whether the next host command is a host read command and whether the next host command is connected to the host command, and when the next host command is a host read command and the next host When the command is continued from the host command, the memory management unit transmits the second data to the host system through the flash memory interface unit.

An exemplary embodiment of the present invention provides a flash memory storage system. The flash memory storage system includes a connector, a flash memory chip, and a flash memory controller. The connector is used to couple the host system. The flash memory controller is coupled to the connector and the flash memory chip, and configured to receive a host command from the host system through the connector, wherein the host command is a host read command and the host command includes a first start Logical address. In addition, the flash memory controller sequentially reads the first data corresponding to the host instruction from the physical address of the first starting logical address in the flash memory chip according to the host command, and flashes The memory controller reads the second data that is not requested by the host instruction from the flash memory chip during at least a portion of the first data being transferred to the flash memory controller, wherein The physical address of the second data stored in the flash memory chip is the physical address of the first data stored. Additionally, the flash memory controller receives a host command from the host system via the connector, wherein the next host command includes a second start logical address. Furthermore, the flash memory controller determines whether the next host command is a host read command and whether the next host command is connected to the host command, and when the next host command is a host read command and the When a host command is connected to the host command, the flash memory controller transmits the second data to the host system through the flash memory interface unit.

Based on the above, the method for releasing the read command, the flash memory controller and the flash memory storage system according to the exemplary embodiments of the present invention can effectively shorten the time required to execute the host read command, thereby improving the flash memory. The performance of the storage system.

The above described features and advantages of the present invention will be more apparent from the following description.

110‧‧‧Host system

120‧‧‧Flash memory storage device

122‧‧‧Connector

124‧‧‧Flash Memory Controller

126‧‧‧Flash Memory Module

132‧‧‧ buffer zone

134‧‧‧ memory cells

200‧‧‧Flash memory storage device

202‧‧‧Connector

204‧‧‧Flash Memory Controller

206‧‧‧Microprocessor unit

208‧‧‧Memory Management Unit

210‧‧‧Host interface unit

212‧‧‧Flash Memory Interface Unit

214‧‧‧ buffer memory

220‧‧‧Flash memory chip

290‧‧‧Host system

295‧‧ ‧ busbar

402‧‧‧ Storage area

404‧‧‧First buffer zone

406‧‧‧second buffer zone

602‧‧‧USB flash drive

604‧‧‧Digital camera

604a‧‧‧SD card

604b‧‧MMC card

604c‧‧‧CF card

604d‧‧‧Memory Stick

606‧‧‧ Solid State Drive

1102‧‧‧Microprocessor

1104‧‧‧ Random access memory

1106‧‧‧Input/output devices

1108‧‧‧System Bus

1110‧‧‧Data transmission interface

C1, C2, C3‧‧‧ directives

D1, D2, D3, D4‧‧‧ data

ADD‧‧‧ physical address

CM1, CM2, CM3, CM4, CM5, CM6, CM7‧‧‧ instructions

T1, T2, T3, T4‧‧‧ internal data transmission

B1, B2, B3, B4, B5‧‧‧ busy time

S501, S503, S505, S507, S509, S511, S513, S515, S517‧‧‧ steps to read the command

1 is a schematic block diagram showing a general flash memory storage device.

2A is a diagram showing a host system using a flash memory storage device in accordance with an embodiment of the present invention.

FIG. 2B is a schematic block diagram of a flash memory storage device according to an exemplary embodiment of the invention.

FIG. 3 is a diagram of a flash memory controller according to an exemplary embodiment of the invention. A schematic diagram of a sample read command.

4 is a timing chart showing the operation of the flash memory chip according to the instructions of FIG.

FIG. 5 is a flow chart of a read command issued according to an exemplary embodiment of the present invention.

FIG. 6 is a schematic diagram showing a method for obtaining a read command and an apparatus for applying the data reading method according to an exemplary embodiment of the present invention.

Flash memory storage systems generally include a flash memory chip and controller (also known as a control circuit). Typically, a flash memory storage system is used with the host system to enable the host system to write data to or read data from the flash memory storage system. In addition, there are also flash memory storage systems that include embedded flash memory and software executable on the host system to substantially act as a controller for the embedded flash memory.

2A illustrates a host system using a flash memory storage device in accordance with an embodiment of the present invention.

Referring to FIG. 2A, the host system 290 generally includes a microprocessor 1102, a random access memory (RAM) 1104, an input/output (I/O) device 1106, a system bus 1108, and data. Transmission interface 1110. It must be understood that the host 290 may further include other components, such as a display device or a network device.

Host system 290 can be a computer, digital camera, camera, communication device, audio player, or video player. In general, host 290 can be substantially any system that can store data.

In the embodiment of the present invention, the flash memory storage device 200 is coupled to other components of the host system 290 through the data transmission interface 1110. The data can be written to or read from the flash memory storage device 200 by the processing of the microprocessor 1102, the random access memory 1104, and the input/output device 1106.

2A discloses a detailed block diagram of the flash memory storage device 200 of FIG. 2B.

Referring to FIG. 2B, the flash memory storage device 200 includes a connector 202, a flash memory controller 204, and a flash memory chip 220.

The connector 202 is coupled to the flash memory controller 204 and is configured to connect to the host system 290 via the bus bar 295. In the present exemplary embodiment, the connector 202 is a Serial Advanced Technology Attachment (SATA) connector. However, it must be understood that the present invention is not limited thereto, and the connector 110 may also be a Universal Serial Bus (USB) connector, Institute of Electrical and Electronic Engineers (IEEE) 1394 connector. , Peripheral Component Interconnect Express (PCI Express) connector, secure digital (SD) interface connector, Memory Stick (MS) interface connector, multimedia memory card (Multi Media Card, MMC) interface connector, compact flash (Compact Flash, CF) interface connector, Integrated Device Electronics (IDE) connector or other suitable connector.

The flash memory controller 204 executes a plurality of logic gates or control instructions implemented in a hard or firmware type and writes and reads data in the flash memory chip 220 in accordance with instructions from the host system 290. Take and erase and other operations. The flash memory controller 204 includes a microprocessor unit 206, a memory management unit 208, a host interface unit 210, a flash memory interface unit 212, and a buffer memory 214.

The microprocessor unit 206 is a main control unit of the flash memory controller 204 for cooperating with the memory management unit 208, the host interface unit 210, and the flash memory interface unit 212 to perform a flash memory storage device. 200 various operations.

The memory management unit 208 is coupled to the microprocessor unit 206 for performing the read command and the block management mechanism according to the exemplary embodiment. The operation of the memory management unit 208 will be described in detail below. .

In the present exemplary embodiment, the memory management unit 208 is implemented in the flash memory controller 204 in a firmware version. For example, the memory management unit 208 including a plurality of control instructions is burned into a program memory (for example, a read only memory (ROM)) and the program memory is embedded in the flash memory control. In the processor 204, when the flash memory storage device 200 operates, a plurality of control commands of the memory management unit 208 are executed by the microprocessor unit 206 to complete the read command and block management according to the embodiment of the present invention. mechanism.

In another exemplary embodiment of the present invention, the control of the memory management unit 208 The instructions can also be stored in a soft area in a particular area of the flash memory chip 220 (e.g., in a system area dedicated to storing system data in a flash memory chip). Similarly, when the flash memory storage device 200 is in operation, a plurality of control commands of the memory management unit 208 are executed by the microprocessor unit 206. In addition, in another exemplary embodiment of the present invention, the memory management unit 208 can also be implemented in the flash memory controller 204 in a hardware format.

The host interface unit 210 is coupled to the microprocessor unit 206 and configured to receive and identify the instructions and data transmitted by the host system 290 and to communicate the data to the host system 290. That is to say, the instructions and data transmitted by the host system 290 are transmitted to the buffer memory 214 through the host interface unit 210, and the memory management unit 208 transmits the data to the host system 290 through the host interface unit 210. In the present exemplary embodiment, the host interface unit 210 is a corresponding connector 204 that is a SATA interface. However, it should be understood that the present invention is not limited thereto, and the host interface unit 210 can also be a USB interface, an IEEE 1394 interface, a PCI Express interface, an SD interface, an MS interface, an MMC interface, a CF interface, an IDE interface, or other suitable data transmission interface. .

The flash memory interface unit 212 is coupled to the microprocessor unit 206 and is coupled to the flash memory chip 220.

The buffer memory 214 is coupled to the microprocessor unit 206 and is used to temporarily store data from the host system 200 or from the flash memory chip 220.

In addition, although not shown in the present exemplary embodiment, the flash memory control The device 204 also further includes an error correction unit, a power management unit, and the like.

The flash memory chip 220 is coupled to the flash memory controller 204 and is used to write data and read data according to the instructions of the flash memory controller 204. In the present exemplary embodiment, the flash memory chip 220 is a multi-level cell (MLC) NAND flash memory chip. However, the present invention is not limited thereto, and the flash memory chip 220 may also be a single level cell (SLC) NAND flash memory chip.

The flash memory chip 220 includes a storage area 402, a first buffer 404, and a second buffer 406.

The storage area 402 includes a plurality of physical blocks and is used to store data. The physical block is the smallest unit of erasure. That is, each physical block contains one of the smallest number of erased memory cells. Each physical block has a plurality of pages. In this exemplary embodiment, the page is the smallest unit of stylization and reading, but in another exemplary embodiment, the minimum unit for programming the data to the flash memory chip 220 may be a fan smaller than the page. District. The page in an exemplary embodiment of the present invention may be the smallest unit for writing data or reading data. Each page typically includes a user data area and a redundant area. The user data area is used to store user data, and the redundant area is used to store system data (for example, Error Checking and Correcting Code (ECC Code).

It is worth mentioning that since the memory cells of the flash memory can only be programmed from "1" to "0", the data in the physical block must be erased first when updating the data in the physical block. However, the flash memory is written in pages, and the erase is The physical block is used as a unit, so the physical block in the storage area 402 stores the data in a rotating manner. Specifically, the memory management unit 208 logically groups the physical blocks in the storage area 204 into a system area, a data area, a spare area, and a replacement area. The physical block grouped into the system area is used to store important information related to the flash memory storage device, and the physical block grouped as the replacement area is used to replace the damaged physical block in the data area or the spare area. Therefore, in the general access state, the host system 290 cannot access the physical blocks in the system area and the replacement area. As for the physical block grouped into the data area, the data written by the host write command is stored, and the physical block in the spare area is used to replace the physical block in the data area when the host write command is executed. For example, when the flash memory storage device 200 receives a host write command from the host system 290 and wants to update (or write) the data to a certain page of a physical block in the data area, the memory management unit 208 Extracting a physical block from the spare area and writing the valid old data in the physical block to be updated and the new data to be written into the physical block extracted from the spare area, and the write is valid The old data is logically associated with the physical block of the new data as a data area, and the physical blocks in the data area to be updated are erased and logically associated as a spare area. In order to enable the host system 290 to smoothly access physical blocks that store data in a rotating manner, the flash memory storage device 200 provides a logical address to the host system 290. That is, the flash memory storage device 200 records and updates between the logical address and the physical block of the data area in the logical address-physical address mapping table. The mapping relationship reflects the rotation of the physical block, so the host system 290 only The write to the provided logical address is required, and the flash memory storage device 200 reads or writes the physical address of the mapped physical block according to the logical address-physical address mapping table.

The first buffer 404 and the second buffer 406 are used for temporarily storing data transmitted between the flash memory controller 204 and the storage area 402. As described above, the process of the flash memory controller 204 reading data from the flash memory chip 220 includes data uploading and internal data transfer, wherein the data to be read in the data uploading portion is first The storage area 402 is moved to the second buffer 406, and the later to be read is moved from the second buffer 406 to the first buffer 404. In the portion of the internal data transfer, the data to be read is transferred from the first buffer 404 to the buffer memory 214. Here, the first buffer 404 for transferring data to the buffer memory 214 is also referred to as a data cache area, and the second buffer 406 for receiving data from the storage area 402 is also referred to as A cache buffer area, wherein the first buffer 404 and the second buffer 406 can temporarily store data of one page to correspond to a read unit (ie, a page).

In the present exemplary embodiment, the memory management unit 208 issues a general read command to the flash memory chip 220 through the flash memory interface unit 212 according to the logical address in the host read command from the host system 290. The cache read command is used to read the data. For example, the memory management unit 208 uses a general read instruction consisting of a string of "instruction C1", "physical address" and "instruction C2", and a cache read consisting of a "command C3" string. The instruction reads the data, wherein the memory management unit 208 instructs the flash memory chip 220 to execute the reading process by "instruction C1", The address to be read by the flash memory chip 220 is indicated by the "physical address", and the flash memory chip 220 is instructed to move the data from the storage area 402 to the second buffer 206 by "command C2", and The flash memory chip 220 is instructed by the "command C3" to move the material from the second buffer 406 to the first buffer 404. In particular, when the host system 290 wants to read data stored in a plurality of logical addresses, the use of the cache read command can effectively increase the speed of reading.

For example, when the memory management unit 208 needs to read data in a plurality of consecutive pages of the flash memory chip 220 according to the host read command, since the flash memory chip 220 has 2 buffers (ie, the first The buffer 404 and the second buffer 406), therefore, after the flash memory chip 220 moves the data of the first page from the storage area 402 to the second buffer 406, by using the cache read command (ie, The "instruction C3" instruction causes the flash memory chip 220 to move the data of the first page from the second buffer 406 to the first buffer 404, and then the data on the first page is from the first buffer. While the 404 is being transferred to the buffer memory 214, the second buffer 406 can receive the data of the second page from the storage area 402. That is, by using the cache read command, the flash memory chip 220 continues to move the data of the next page while the data is being transferred from the flash memory chip 220 to the flash memory controller 204. This speeds up the reading.

In particular, the host system 290 continuously issues a plurality of host read commands to the flash memory storage system 200 and the physical addresses mapped by the logical addresses indicated by the host read commands are consecutive examples. The memory management unit 208 continuously uses a cache read instruction (ie, an "instruction C3" instruction) to serially (or combine) the sequential The host from the host system 290 reads the instructions without having to issue a general read command consisting of the "instruction C1", "physical address" and "instruction C2" strings, thereby increasing the speed of reading. It should be noted that the instructions “C1”, “C2”, “C3”, etc. mentioned in the exemplary embodiment are only one implementation manner, and each manufacturer can customize different instructions to implement similar functions. For example, the functions of "C1" and "C2" described in the examples of this example are implemented by a single instruction, and thus should not be limited thereto.

3 is a schematic diagram showing an example of a flash memory controller issuing a read command according to an exemplary embodiment of the present invention, and FIG. 4 is a timing chart showing the operation of the flash memory chip according to the instruction shown in FIG. . In the example of FIG. 3 and FIG. 4, the memory management unit 208 sequentially receives two host read commands from the host system 290 and reads and stores them in four consecutive frames according to the logical address in the host command. Data D1, data D2, data D3, and data D4 in the physical address (ie, 4 pages). Specifically, the first host read command includes a logical address to be read and information for reading two pages (ie, data D1 and data D2), wherein the logical address to be read is indicated in the first The host initiates the instruction to read the starting logical address of the data (ie, the first starting logical address). The second host read command also includes the logical address to be read and the information to read two pages (ie, data D3 and data D4), wherein the logical address to be read is indicated on the second host. The starting logical address (ie, the second starting logical address) at which the reading of the data begins in the read command.

Referring to FIG. 3 and FIG. 4, after the flash memory controller 204 receives the first host read command from the host system 290, the memory management unit 208 of the flash memory controller 204 reads the host according to the host. The logical address in the instruction fetches to flash The memory chip 220 issues a general read command consisting of a string of "instructions C1", "ADD" and "command C2" (such as the commands CM1, CM2 and CM3 shown in FIG. 3) and the word "command C3". A cache read instruction consisting of a string (such as the instruction CM4 shown in FIG. 3), where "ADD" indicates the starting entity address of the read data. That is to say, the memory management unit 208 transfers the physical address mapped by the first starting logical address to the flash memory chip 200 according to the logical address-physical address mapping table to start reading data. At this time, the flash memory chip 220 moves the data D1 of the first page to the second buffer 406 from the storage area 402 according to the command CM3, during which the flash memory chip 220 is in a busy state (see FIG. 4). Busy time shown B1). After completing the command CM3, the flash memory chip 220 executes a cache read command (such as the command CM4 shown in FIG. 3) to move the data D1 temporarily stored in the second buffer 406 to the first buffer. In 404, and after moving the material D1 from the second buffer 406 to the first buffer 404, the data D2 of the second page is moved from the next physical address to the second buffer 406.

In particular, the flash memory chip 220 returns to the ready state after the data D1 temporarily stored in the second buffer 406 is moved to the first buffer 404 (the busy time B2 as shown in FIG. 4). The status, and the data D1 temporarily stored in the first buffer 404 is transferred to the buffer memory 214 (internal data transmission T1 as shown in FIG. 3). At this time, the internal data transmission of the data D1 and the data upload of the data D2 are simultaneously performed.

That is, since there are two buffers (ie, the first buffer 404 and the second buffer 406) in the flash memory chip 220, the read command is read through the cache. After the data to be read is moved from the second buffer 406 to the first buffer 404, the first buffer 404 is used to transfer the data from the storage area 402 to the buffer memory 214, and the second buffer. 406 is for receiving data from storage area 402. Based on this, the internal data transmission of the data D1 and the data upload of the data D2 can be simultaneously performed.

In general, the time required for flash memory chip 220 to execute a cache read command (eg, busy time B2) is much shorter than the time required to execute a normal read command (eg, busy time B1). For example, the time required for the flash memory chip 220 to execute the cache read command is 1 millisecond, and the time required to execute the general read command is 50 milliseconds.

After that, after the internal data transmission of the data D1 is completed, the memory management unit 208 will again issue a cache read command (the command CM5 shown in FIG. 3) to the flash memory chip 220 to temporarily store the second data. The data D2 in the buffer 406 is moved into the first buffer 404 (busy time B3 as shown in FIG. 4), and after the data D2 is moved from the second buffer 406 to the first buffer 404 from the next The data of the next page is moved to the second buffer 406 in the physical address. Similarly, the flash memory chip 220 returns to the standby state after the data D2 temporarily stored in the second buffer 406 is moved to the first buffer 404, and is temporarily stored in the first buffer 404. The data D2 is transferred to the buffer memory 214 (internal data transmission T2 as shown in FIG. 3). At this time, the internal data transmission of the data D2 and the data upload of the data of the next page are simultaneously performed.

After the transmission T2 is completed, the data corresponding to the first host read command (ie, the data D1 and the data D2) is transferred from the buffer memory 214 to the host system. 290, that is, external data transmission. Thereafter, the flash memory controller 204 receives the second host read command from the host system 290, and the memory management unit 208 determines whether the logical address to be accessed by the second host read command is connected. The logical address accessed by the first host read instruction.

As described above, in the examples of FIG. 3 and FIG. 4, the physical address mapped by the logical address to be accessed by the second host read instruction is the logic accessed by the first host read instruction. The physical address to which the address is mapped. Therefore, the data of the next page moved by the flash memory chip 220 from the storage area 402 in accordance with the command CM5 is the data D3. Accordingly, the memory management unit 208 issues a cache read command (the command CM6 as shown in FIG. 3) to the flash memory chip 220 to move the data D3 temporarily stored in the second buffer 406 to the first In the buffer 404, and after moving the data D3 from the second buffer 406 to the first buffer 404 (such as the busy time B4 shown in FIG. 4), the data of the fourth page is moved from the next physical address. D4 to the second buffer 406. Similarly, the flash memory chip 220 returns to the standby state after the data D3 temporarily stored in the second buffer 406 is moved to the first buffer 404, and is temporarily stored in the first buffer 404. The data D3 is transferred to the buffer memory 214 (internal data transmission T3 as shown in FIG. 3). At this time, the internal data transmission of the data D3 and the data upload of the data D4 are simultaneously performed.

After that, after the internal data transmission of the data D3 is completed, the memory management unit 208 will again issue a cache read command (the command CM7 shown in FIG. 3) to the flash memory chip 220 to temporarily store the second data. The data D4 in the buffer 406 is moved into the first buffer 404, and the data D4 is moved from the second buffer 406 to the first A buffer 404 (such as the busy time B5 shown in FIG. 4) then moves the data of the next page from the next physical address to the second buffer 406. Similarly, the flash memory chip 220 returns to the standby state after the data D4 temporarily stored in the second buffer 406 is moved to the first buffer 404, and is temporarily stored in the first buffer 404. The data D4 is transferred to the buffer memory 214 (internal data transmission T4 as shown in FIG. 3). At this time, the internal data transmission of the data D4 and the data upload of the data of the next page are simultaneously performed.

After the transfer T4 is completed, the data corresponding to the second host read command (ie, the data D3 and the data D4) is transferred from the buffer memory 214 to the host system 290.

It is worth mentioning that when the memory management unit 208 issues the command CM5 and the command CM7, the memory management unit 208 only instructs the flash memory chip 220 to read the data of the next page in advance, and the memory management unit 208 is Whether the host system 290 accesses the pre-read data can be confirmed when the next host command is executed. Here, the program in which the flash memory chip 220 continues to read the next page in accordance with the cache read command is referred to as a pre-read program. However, the next host read command from host system 290 may just have to read this data (eg, data D3 shown in FIG. 3), so when the pre-read data is exactly the data pre-read by host system 290. At this time, the pre-read data can be transmitted to the host system 290, thereby effectively increasing the reading speed.

In addition, it is worth mentioning that, as described above, the memory management unit 208 is to pre-read the data of the next physical address to improve the reading speed. However, when When the logical block mapped by the previously accessed logical address is in the state of opening the parent and child blocks, that is, one logical block is the state of mapping multiple physical blocks, and the data in the continuous physical address may be Non-corresponding to consecutive logical addresses. In this case, prefetching the data in the next physical address will have a higher probability of becoming meaningless (ie, the pre-read data is not the data to be read by the next host read command). Therefore, in another exemplary embodiment of the present invention, the memory management unit 208 first determines whether the logical block mapped by the currently accessed logical address is in the above-mentioned open parent block before performing the pre-reading process. The pre-reading process is performed only if the logical block mapped by the currently accessed logical address is not in the state in which the parent-child block is turned on.

In the present exemplary embodiment, when the flash memory controller 204 executes the host read command, after the flash memory chip 220 completes the data upload of the data to be accessed by the current host read command, the memory management unit 208 The cache read command will continue to be used to cause the flash memory chip 220 to read the data of the next page. Thereafter, if the next host command received by the flash memory controller 204 from the host system 290 is not a host read command, the memory management unit 208 issues a reset to the flash memory chip 220 (reset). An instruction (e.g., an instruction consisting of a "0xFF" string) stops the operation of the flash memory chip 220.

FIG. 5 is a flow chart of a read command issued according to an exemplary embodiment of the present invention.

Referring to FIG. 5, first, in step S501, the flash memory storage device 200 receives a host command from the host system 290 and in step S503, the memory management unit 208 determines whether the received host command is a host read command.

If it is determined in step S503 that the received host command is not a host read command, the memory management unit 208 issues a reset command to the flash memory chip 220 in step S505. Thereafter, in step S507, the memory management unit 208 executes the corresponding steps in accordance with the received host command, and ends the flow of FIG. In the present exemplary embodiment, FIG. 5 is only used to describe the steps of the memory management unit 208 executing the host read instruction. As for the steps of executing other host instructions, those skilled in the art may learn from the related art, and the details are not detailed here. Step S507 is explained.

If it is determined in step S503 that the received host command is a host read command, then in step S509, the memory management unit 208 determines whether the previously executed host command is a host read command.

If it is determined in step S509 that the previous host command executed is not the host read command, then the memory management unit 208 issues a general read command to the flash memory chip 220 in step S511 (ie, by "instruction" The data consists of C1", "physical address" and "instruction C2" string) and the cache read instruction (ie, the instruction consisting of the "command C3" string), and the data is terminated. Process. Specifically, in step S511, the memory management unit 208 sequentially reads in the flash memory chip 200 from the physical address mapped by the starting logical address indicated by the received host read command. Corresponds to the data read by this host. In particular, as described above, the last cached read command issued will pre-read the data in the next physical address.

If it is determined in step S509 that the host command executed by the previous one is the host read command, the memory management unit 208 determines the current master in step S513. Whether the machine read instruction is connected to the previous host read command. For example, in step S513, the memory management unit 208 determines whether the physical address mapped by the logical address accessed by the current host read instruction is mapped by the logical address accessed by the previous host read instruction. Physical address, and when the physical address mapped by the logical address accessed by the current host read instruction is connected to the physical address mapped by the logical address accessed by the previous host read instruction, Then, the memory management unit 208 determines whether the current host read command is connected to the previous host read command.

If it is determined in step S513 that the current host read command is subsequent to the previous host read command, then in step S515, the memory management unit 208 issues a cache read command to the flash memory chip 220 to continue reading. A page of information and end the process of Figure 5. Specifically, in step S513, the memory management unit 208 sequentially reads the data corresponding to the host read command from the next physical address of the pre-read physical address in the flash memory chip 200. . That is, since the current host read command is subsequent to the previous host read command, the previously pre-read data can be used to transfer to the host system 290, but only from the next physical address. Similarly, the last cache read instruction issued in step S515 also pre-reads the data in the next physical address.

If it is determined in step S513 that the current host read command is not connected to the previous host read command, the memory management unit 208 issues a reset command to the flash memory chip 220 in step S517, and then executes. Step S511 is to read the data by issuing a general read command and a cache read command to the flash memory chip 220.

It is worth mentioning that the last cache read instruction issued in step S511 and step S515 pre-reads the data in the next entity address, so in another exemplary embodiment of the present invention, in step S513 Whether the current host read command is connected to the previous host read or not by comparing the physical address mapped to the logical address accessed by the current host read command to the pre-read physical address. The fetching instruction, wherein when the physical address mapped by the logical address accessed by the current host read command is the same as the pre-read physical address, the memory management unit determines that the current host read command is continuous The previous host reads the instruction.

The method for obtaining a read instruction and the data reading method thereof according to an exemplary embodiment of the present invention are applicable to a flash memory, and therefore, the method for reading a read instruction and the data reading thereof according to an exemplary embodiment of the present invention are provided. The method can apply various devices that use flash memory as a storage medium. That is, the flash memory storage device 200 may be a flash disk 604a, an MMC card 604b, a CF card 604c, and a memory stick used by the flash drive 602, the digital camera (camera) 604 as shown in FIG. 604d or Solid State Drive (SSD) 606 and so on.

In summary, the method for issuing a read command according to an exemplary embodiment of the present invention combines a plurality of host read commands for reading consecutive logical addresses with cache read commands, thereby shortening execution host read commands. time. In addition, pre-reading the data of the next page through the pre-reading program can effectively shorten the time for executing the host read command.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art without departing from the invention In the spirit and scope, the scope of protection of the present invention is subject to the definition of the scope of the appended patent application.

S501, S503, S505, S507, S509, S511, S513, S515, S517‧‧‧ steps to read the command

Claims (15)

A method for issuing a read command to a flash memory chip, the flash memory chip having a first buffer, a second buffer, and a storage area, wherein the method for issuing the read command comprises: having one A flash memory controller of the buffer memory receives a host command from the host system, wherein the host command is a host read command and the host command includes a first logical address, wherein the first logical address Mapping to a first physical address of the storage area; the flash memory controller issues a general read command and a first cache read command to the flash memory chip according to the host command The first physical address sequentially reads a first data, wherein the first data is moved from the storage area to the second buffer, and the second buffer is moved to the first buffer, and Transmitting from the first buffer to the buffer memory, a second data is moved from the storage area to the second buffer during the transfer of the first data from the first buffer to the buffer memory. District, and After the first data is transferred from the first buffer to the buffer memory, the second data is moved from the second buffer to the first buffer, wherein the second data is not requested by the host instruction. And a logical address corresponding to the second data is connected to the first logical address; a second cache read command is issued by the flash memory controller to the flash memory chip to read a first a third data, wherein the third data is moved from the storage area to the second buffer during the period from which the second data is transferred to the buffer memory, and the second data is from the The first buffer is transferred to the After buffering the memory, the third data is moved from the second buffer to the first buffer; receiving a host instruction from the host system, wherein the next host instruction includes a second logical address; Whether the next host instruction reads the instruction for the host and whether the next host instruction is connected to the host instruction; if the next host instruction is the host read instruction and the next host instruction is connected to the host instruction Transmitting the second data from the buffer memory to the host system; and if the next host command is the host read command and the next host command is not connected to the host command, by the flash memory The controller issues a reset command to the flash memory chip, and issues the general read command and a third cache read command to the flash memory chip for mapping from the flash memory chip. A physical address of a third logical address begins to sequentially read a fourth data corresponding to the next host instruction. The method for reading a read command to the flash memory chip as described in claim 1 further includes: if the next host command does not read the command from the host, the flash memory controller The reset command is issued to the flash memory chip. The method for determining a read command to the flash memory chip, as described in claim 1, wherein the step of determining whether the next host command is subsequent to the host command comprises: Determining whether the second logical address is connected to the first logical address; and if the second logical address is subsequent to the first logical address, determining that the next host instruction is subsequent to the host instruction. The method for determining a read command to the flash memory chip, as described in claim 1, wherein determining whether the next host command is connected to the host command comprises: determining whether the second logical address is Same as the logical address corresponding to the second data in the buffer memory; and if the second logical address is the same as the logical address corresponding to the second data in the buffer memory, determining the next one The host command is connected to the host command. The method for reading a read command to the flash memory chip as described in claim 1 of the patent application, further comprising: determining, before reading the second data that is not the host command request from the flash memory chip, Whether a logical block mapped by the first logical address is in an open parent and child block state, wherein the flash block is flashed only when the logical block corresponding to the first logical address is not in the open parent and child block state The second data that is not requested by the host instruction is read in the memory chip. A flash memory controller for reading data to be accessed by a host system from a flash memory chip having a first buffer, a second buffer, and a storage area, the flash memory The body controller includes: a microprocessor unit; a flash memory interface unit coupled to the microprocessor unit for connecting a flash memory chip; a host interface unit coupled to the microprocessor unit for connecting to the host system; a buffer memory coupled to the microprocessor unit; and a memory management unit coupled Connected to the microprocessor unit for receiving a host command from the host system through the host interface unit, wherein the host command is a host read command and the host command includes a first logical address, wherein the A logical address is mapped to a first physical address of the storage area; wherein the memory management unit is further configured to issue a general read command and a first cache to the flash memory chip according to the host command Reading a command to sequentially read a first data from the first physical address, wherein the first data is moved from the storage area to the second buffer, and the second buffer is moved to the first a buffer buffer is transferred from the first buffer to the buffer memory, and a second data is moved from the storage area while the first data is transferred from the first buffer to the buffer memory To this a second buffer, and after the first data is transferred from the first buffer to the buffer memory, the second data is moved from the second buffer to the first buffer, wherein the second data is not For the host command, a logical address corresponding to the second data is connected to the first logical address; wherein the memory management unit is further configured to send a second cache to the flash memory chip. Reading a command to read a third data, wherein the third data is moved from the storage area to the second buffer during the second data being transferred from the first buffer to the buffer memory. And the second data is transmitted from the first buffer After being input to the buffer memory, the third data is moved from the second buffer to the first buffer; wherein the memory management unit is further configured to receive a host command from the host system, where the next The host command includes a second logical address; wherein the memory management unit is further configured to determine whether the next host command is a read command of the host and whether the next host command is connected to the host command, and if The next host command reads the command for the host and the next host command is the host command, and the memory management unit transmits the second data from the buffer memory to the host system, wherein the next host The instruction is that the host reads the instruction and the next host instruction is not connected to the host instruction, and the memory management unit issues a reset instruction to the flash memory chip, and issues the general to the flash memory chip. Reading instructions and a third cache read instruction to sequentially sequence from a physical address of the third logical address in the flash memory chip A fourth reading of data should be the next host instruction. The flash memory controller of claim 6, wherein the memory management unit issues the reset command to the flash memory chip if the next host command does not read the command from the host. The flash memory controller of claim 6, wherein the memory management unit determines whether the next host instruction is an operation subsequent to the host instruction, including: determining whether the second logical address is connected to The first logical address; If the second logical address is connected to the first logical address, it is determined that the next host instruction is connected to the host instruction. The flash memory controller of claim 6, wherein the memory management unit determines whether the next host instruction is an operation subsequent to the host instruction, comprising: determining whether the second logical address is the same a logical address corresponding to the second data in the buffer memory; and determining the next host instruction if the second logical address is the same as the logical address corresponding to the second data in the buffer memory To continue with the host command. The flash memory controller of claim 6, wherein the memory management unit is further configured to determine the second data that is not requested by the host command from the flash memory chip. Whether a logical block mapped by the first logical address is in an open parent and child block state, wherein the memory management is only when the logical block corresponding to the first logical address is not in the open parent and child block state The unit reads the second data that is not requested by the host instruction from the flash memory chip. A flash memory storage system includes: a connector for coupling to a host system; a flash memory chip having a first buffer, a second buffer, and a storage area; and a flash a memory controller coupled to the connector and the flash memory chip and having a buffer memory The flash memory controller is configured to receive a host command from the host system, wherein the host command is a host read command and the host command includes a first logical address, wherein the first logical address is mapped a first physical address to the storage area; wherein the flash memory controller is further configured to issue a general read command and a first cache read command to the flash memory chip according to the host command And sequentially reading a first data from the first physical address, wherein the first data is moved from the storage area to the second buffer, and the second buffer is moved to the first buffer. And being transferred from the first buffer to the buffer memory, and a second data is moved from the storage area to the second during the transfer of the first data from the first buffer to the buffer memory. a buffer, and after the first data is transferred from the first buffer to the buffer memory, the second data is moved from the second buffer to the first buffer, wherein the second data is not Requested by the host command, A logical address corresponding to the second data is connected to the first logical address; wherein the flash memory controller is further configured to issue a second cache read command to the flash memory chip to read a third data, wherein the third data is moved from the storage area to the second buffer during the second data transfer from the first buffer to the buffer memory, and the second data is After the first buffer is transferred to the buffer memory, the third data is moved from the second buffer to the first buffer; wherein the flash memory controller is further used from the host system Receiving a host instruction, wherein the next host instruction includes a second logical address; The flash memory controller is further configured to determine whether the next host command is a read command of the host and whether the next host command is connected to the host command, and if the next host command is read by the host And the memory management unit transmits the second data from the buffer memory to the host system, wherein the next host instruction reads the instruction for the host and the The next host command is not connected to the host command, the flash memory controller issues a reset command to the flash memory chip, and issues the general read command and a third to the flash memory chip. The cache read command sequentially reads a fourth data corresponding to the next host command from a physical address of the mapped third logical address in the flash memory chip. The flash memory storage system of claim 11, wherein the flash memory controller issues a reset to the flash memory chip if the next host command does not read the command from the host instruction. The flash memory storage system of claim 11, wherein the flash memory controller determines whether the next host instruction is an operation subsequent to the host instruction, including: determining whether the second logical address is And continuing to the first logical address; and if the second logical address is subsequent to the first logical address, determining that the next host instruction is subsequent to the host instruction. The flash memory storage system of claim 11, wherein the flash memory controller determines whether the next host command is connected to the main The operation of the machine instruction includes: determining whether the second logical address is the same as a logical address corresponding to the second data in the buffer memory; and if the second logical address is the same as the buffer memory corresponding to the The logical address of the second data determines that the next host command is connected to the host command. The flash memory storage system of claim 11, wherein the flash memory controller is further used before reading the second data that is not requested by the host instruction from the flash memory chip. Determining whether a logical block mapped by the first logical address is in an open parent and child block state, wherein only when the logical block corresponding to the first logical address is not in the open parent and child block state, the fast The flash memory controller reads the second data that is not requested by the host instruction from the flash memory chip.