TWI493843B - Multi-stage sampling circuit for a power converter controller - Google Patents

Description

Multi-stage sampling circuit for power converter controller

The present invention relates generally to power converter controllers, and more particularly to multi-stage sampling circuits for power converter controllers.

Most electrical devices, such as mobile phones, personal digital assistants (PDA's), laptops, etc., use power to operate. Since the power supply typically delivers high voltage alternating current (ac) via a wall outlet, a device is typically considered to be a power converter that can be used to convert a high voltage alternating current (ac) input to an appropriately adjusted direct current via an energy transfer element ( Dc). Usually, due to its high efficiency, small size and low weight, a switching power converter is used to provide power for most electronic devices today. In operation, a switch is used to vary the switching frequency or the number of pulses per unit time by varying the duty cycle of the switch in a power converter (typically the ratio of the operating time of the switch to the total switching time). Provide the required output.

A power converter can use a controller to sense and control the output of the power converter in a closed loop to provide output regulation to an electrical device (generally considered a load). More specifically, the controller can be coupled to a sensor to provide feedback information relating to the output of the power converter in order to adjust the amount of output delivered to the load. The controller adjusts the output delivered to the load by controlling a switch to turn on and off in response to feedback information originating from the sensor to transfer energy pulses to an input power source such as a power line to the power conversion Output.

The sensor used in the power converter to provide the feedback information can include an optocoupler that receives information related to the output voltage directly from the output of the power converter. The output of the power converter is also coupled to a secondary winding of one of the energy transfer elements. This type of control plan is typically considered "secondary side control." Another type of control plan can be used alternately by the controller, which is generally referred to as "primary side control." The primary side control, the sensor may include one of the energy transfer elements once a reference winding (eg, a bias winding) to provide energy to the switching event of the output, providing the power converter A signal representative of the output voltage. Although the primary side control eliminates the cost and power consumed by an optocoupler, the output voltage cannot be sensed without switching. Moreover, particularly during light loads, the amount of time that the signal is provided by the primary reference winding representing the output voltage is limited.

The present invention discloses an integrated circuit controller for a power converter, the controller comprising: a tracking and holding circuit coupled to receive a signal from a single terminal of the controller, the signal being used to represent One of the power converters outputs a voltage during at least a portion of the first switch, wherein the tracking and holding circuit includes a first capacitor coupled to provide a first voltage at the first switch Tracking the signal during the portion of the turn-off time and maintaining the first voltage at the end of the portion of the turn-off time; a sample-and-hold circuit coupled to the track-and-hold circuit for when the first voltage is Sampling the first voltage while remaining on the first capacitor, wherein the sample and hold circuit includes a second capacitor Coupled to maintain a second voltage representative of the first voltage after a sampling period, wherein the second capacitor has a capacitance value that is greater than the capacitance value of the first capacitor; and drive logic Coupled to the sample and hold circuit and coupled to control the first switch to adjust an output of the power converter after responding to the second voltage.

The present disclosure discloses examples related to sensing voltages in power converters. In the following description, numerous specific details are set forth. However, it will be apparent to those skilled in the art that this specific detail is not required to practice the invention. In other instances, well-known materials or methods have not been described in detail, in order to avoid obscuring the invention.

Reference to "one embodiment", "an embodiment", "an example" or "one example" as used throughout the specification is intended to mean A particular feature, structure, or characteristic described in connection with the particular embodiment or example is included in at least one embodiment of the invention. Accordingly, the phrase "one embodiment", "an embodiment", "an example" or "an" "One example" does not necessarily refer to the same specific embodiment or example. Furthermore, particular features, structures, or characteristics may be combined in any suitable combination or sub-combination in one or more embodiments or examples. Special features, structures or features can be included Included in an integrated circuit, an electronic circuit, a combined logic circuit, or other suitable component that provides the desired functionality. In addition, it is to be understood that the drawings are provided for the purpose of illustration

As will be explained, the exemplary integrated controller for power converters provides output regulation by sensing and controlling the output of the power converter in a closed loop. A sensing circuit included in the power converter can provide a signal representative of the output voltage based on magnetic coupling between the isolated windings of an energy transfer element. As mentioned previously, this type of control is generally considered to be "primary side control" or control using primary side feedback.

Although the primary side feedback eliminates the cost and power consumed by an optocoupler, the output voltage cannot be sensed without switching. Thus, an exemplary controller in accordance with the teachings herein includes a sampling circuit to sample the signals provided by the sensing circuit. In one example, the sampling circuit includes a capacitor to store the sampled signal. A sense signal stored on the capacitor is then received by the controller's drive logic to control the power switch. However, particularly during light loads, the amount of time required to provide the signal by the sensing circuit is limited.

Moreover, in the case of a controller that uses pulse skipping under light load, the capacitor storing the sensed signal should be large enough to maintain the value of the sensed signal for the complex clock cycle. As will be further described, the controller includes an oscillator that provides a clock signal. The frequency of the clock signal can partially determine the switching frequency of the switch. In some operating conditions, the switch is capable of cycling at each clock cycle and for itself, the switching frequency is substantially The system is equal to the period of the clock frequency. However, under light load conditions, the switch is not capable of operating at each clock cycle and the effective switching frequency is below the clock frequency. As such, the capacitor storing the sensed signal should be large enough to maintain the value of the sensed signal for the complex clock cycle at least until the next switching event.

Therefore, in order to charge a single large capacitor for a short period of time to store the sensed output, it is necessary to use a fast, high current buffer that utilizes more power and is difficult to design. Thus, embodiments of the present invention utilize a multi-level sampling circuit to sense and store the signal provided by the sensing circuit. In one example, the multi-stage sampling circuit includes a tracking hold phase performed after a sample hold phase to sense and store the output voltage of a power converter. On a small capacitor that is charged using a simple buffer, a tracking hold phase is coupled to track the sensed output voltage and then maintain the sensed output voltage. Once the sensed output voltage is maintained at the smaller tracking hold capacitor, the hold value is thus transferred to a larger capacitor (eg, approximately ten times the capacitance) using a sample hold phase. As such, the multi-stage feedback circuit can quickly maintain the sensed output voltage on a small capacitor of the track-and-hold circuit and then transfer the sensed output voltage to the larger of the sample-and-hold circuit A capacitor that maintains the value of the sensed output voltage for a plurality of clock cycles. In one embodiment, the tracking and holding circuit is utilized to allow the controller to obtain the value of the sensed output voltage at the most recent possible time.

For illustrative purposes, FIG. 1 is a functional block diagram showing an exemplary power conversion of a controller 122 in accordance with the teachings of the present invention. 100. An example of the illustrated power converter 100 includes an energy transfer component T1 104, a primary winding 106 of the energy transfer component T1 104, a secondary winding 108 of the energy transfer component T1 104, a switch S1 110, an input The circuit 111, a clamping circuit 112, a rectifier D1 114, an output capacitor C1 116, an output circuit 117, a sensing circuit 120, a controller 122 and an integrated circuit 125. The controller 122 is shown to include a single feedback terminal 123, a multi-stage sampling circuit 132, and drive logic 134. Also shown in FIG. 1 is an input voltage VIN 102, an output UO, an output current IO, a sense signal USENSE 124, a current sense signal 126, a drive signal 128, and a switching current ID 130. In the illustrated example, the power converter 100 is shown for purposes of explanation as a power converter having a flyback topology. It will be appreciated that other well-known topologies and configurations of power converters may also benefit from the teachings of the present invention.

The power converter 100 provides output power from an unregulated input VIN 102 to a load 118. In one embodiment, the input VIN 102 is a rectified and filtered AC line voltage. In another embodiment, the input voltage VIN 102 is a DC input voltage. The input VIN 102 is coupled to the energy transfer element T1 104. In some embodiments of the invention, the energy transfer element T1 104 can be a coupled inductor. In some other embodiments of the invention, the energy transfer element T1 104 can be a transformer. In the example of FIG. 1, the energy transfer element T1 104 includes two windings, a primary winding 106 and a secondary winding 108. NP and NS are the top of the primary winding 106 and the secondary winding 108, respectively. number. In the example of FIG. 1, primary winding 106 is understood to be an input winding, and secondary winding 108 is understood to be an output winding. The primary winding 106 is further coupled to a power switch S1 110, which is then further coupled to the input circuit 111. Additionally, the clamp circuit 112 is coupled across the primary winding 106 of the energy transfer element T1 104.

The secondary winding 108 of the energy transfer element T1 104 is coupled to the rectifier D1 114. In the example illustrated in FIG. 1, the rectifier D1 114 is illustrated as a diode and the secondary winding 108 is coupled to the anode of the diode. However, in some examples, the rectifier D1 114 can be a transistor that is used as a synchronous rectifier. Both output capacitor C1 116 and the load 118 are coupled to the rectifier D1 114. In the example of FIG. 1, both output capacitor C1 116 and the load 118 are coupled to the cathode of the diode. An output is provided to load 118 and can be provided as an output voltage VO, an output current IO, or a combination of the two.

The power converter 100 further includes circuitry to adjust the output that is illustrated as output UO. A sensing circuit 120 is coupled to sense the output UO and provide a sensing signal USENSE 124, which is representative of the output UO. As will be explained in more detail below, the sensing circuit 120 can sense the output from an additional winding of the energy transfer element T1 104. In another embodiment, the sensing circuit 120 can sense the output UO directly from the output of the power converter 100 via a circuit, such as an optocoupler. Generally, the output UO is an output voltage VO, an output current IO, or a combination of the two.

Controller 122 is coupled to the sensing circuit 120 and may include a complex end end. At the terminal 123, the controller 122 receives the sensing signal USENSE 124 from the sensing circuit 120. The controller 122 further includes a terminal for receiving the current sense signal 126 and for providing the drive signal 128 to the switch S1 110. The current sense signal 126 can be representative of the switch current ID 130 in the switch S1 110. Additionally, the controller 122 provides a drive signal 128 to the switch S1 110 to control different switching parameters. Examples of such parameters may include switching frequency, switching period, duty cycle, or respective number of on and off times of the switch S1 110.

As illustrated in FIG. 1, the controller 122 includes a multi-stage sampling circuit 132 and drive logic 134. The multi-stage sampling circuit 132 is coupled to receive the sense signal USENSE 124. The output of the multi-stage sampling circuit 132 is then coupled to and received by the drive logic 134. Drive logic 134 further receives current sense signal 126 and output drive signal 128 in response to the output of multi-stage sampling circuit 132. In some embodiments, the drive logic 134 also outputs a drive signal 128 in response to the current sense signal 126.

In the example of FIG. 1, input voltage VIN 102 is positive with respect to input loop 111, and output voltage VO 120 is positive with respect to output loop 117. This example of FIG. 1 shows galvanic isolation between the input loop 111 and the output loop 117. In other words, the DC voltage applied between the input circuit 111 and the output circuit 117 will substantially produce zero current. Thus, the circuitry electrically coupled to the primary winding 106 is galvanically isolated from the circuitry electrically coupled to the secondary winding 108.

In operation, the power converter 100 of FIG. 1 provides output power by An input VIN 102 is unregulated to the load 118. The power converter 100 utilizes the energy transfer element T1 104 to transfer energy between the primary winding 106 and the secondary winding 108. The clamp circuit 112 is coupled to the primary winding 106 of the energy transfer element T1 104 to limit the maximum voltage across the switch S1 110. Switch S1 110 is opened and closed in response to the drive signal 128 received from the controller 122. It is generally understood that a closed switch conducts current and is understood to be on, while a switch that is turned on cannot conduct current and is understood to be turned off. In the example of FIG. 1, switch S1 110 controls a current ID 130 after responding to controller 122 to conform to a specified performance of power converter 100. In some embodiments, the switch S1 110 can be a transistor and the controller 122 can include integrated circuitry and/or individual electrical components. In one embodiment, controller 122 and switch S1 110 are included together in a single integrated circuit 125. In one example, the integrated circuit is a monolithic integrated circuit. In another example, the integrated circuit is a hybrid integrated circuit.

The operation of switch S1 110 also produces a time varying voltage VP across the primary winding 106. A proportional replica voltage VP across the secondary winding 108 is produced by the action of a transformer which is the ratio of the number of turns NS of the secondary winding 108 divided by the number of turns NP of the primary winding 106. Switching of switch S1 110 also produces a ripple current at rectifier D1 114. The current in rectifier D1 114 is filtered by output capacitor C1 116 to produce a substantially constant output voltage VO, output current IO, or a combination of the two at load 118.

The sensing circuit 120 senses the output UO to provide the sensing signal USENSE 124 to the controller 122. In the example of FIG. 1, the controller 122 also receives the current sense input 126 that relays the sense switch current ID 130 in the switch S1 110. The switching current ID 130 can be sensed in various ways, such as, for example, when the transistor is conducted, across the voltage of a respective resistor or across the voltage of the transistor.

The controller 122 output drive signal 128 also operates the switch S1 110 in response to a different system input to substantially adjust the output UO output to the desired value. The output of the switched mode power converter 100 is adjusted in a closed loop by using the sensing circuit 120 and the controller 122. The controller 122 further includes a multi-stage sampling circuit 132 to receive and store the output UO provided by the sensed signal USENSE 124. The stored output UO is then output to the drive logic 134. The multi-stage sampling circuit 132 provides a means to quickly store the output UO and save the output UO for several clock cycles without using a fast, expensive buffer.

2 is a functional block diagram illustrating an exemplary power converter 200 having a sense circuit 120 (eg, bias winding 206) including a primary reference winding in accordance with the teachings of the present invention. Power converter 200 is a possible application of power converter 100 and provides further details regarding a possible sensing circuit 120 and multi-stage sampling circuit 132. In FIG. 2, exemplary sensing circuit 120 is illustrated as including bias winding 206 and resistors R1 208 and R2 210. The bias winding 206 can be an additional winding to one of the energy transfer elements T1. The illustrated example of multi-stage sampling circuit 132 is shown in FIG. 2 and includes a track-and-hold circuit 220 and a sample and hold circuit 222.

In the particular embodiment of the illustration, the sensing circuit 120 provides the sense signal USENSE 124. Resistors R1 208 and R2 210 are coupled across the bias winding 206. Bias winding 206 and resistor R2 210 are coupled to output loop 111. In the example shown, this voltage across the resistor R2 210 (feedback voltage VFB) is utilized as the sense signal USENSE 124. The feedback voltage VFB is received by the controller 122 at the terminal 123 and additionally by the multi-stage sampling circuit 132.

In operation, the bias winding 206 produces a voltage VB that is responsive to the output voltage VO as the rectifier D1 114 conducts on the secondary winding 108. The feedback voltage VB and the sense signal USENSE 124 are representative of the output voltage VO during at least a portion of one of the switches S1 110 being turned off (OFF). In one embodiment, the sense signal USENSE 124 is representative of the output voltage VO only during the OFF time of the portion. During one of the switches S1 110, the bias winding 206 generates a voltage VB that is responsive to the input voltage VIN 102. In another example, the bias windings 206 can also provide a power source to the circuits within the controller 122. Resistors R1 208 and R2 210 are utilized to correspondingly reduce the voltage of the bias winding 206. For its part, the voltage VFB is a scaled version of the bias voltage VB.

It will be appreciated that there can be multiple variations in the use of a bias winding to sense an output voltage VO and to provide sensing while providing power to a controller with galvanic isolation. For example, a bias winding can be applied with a rectifier and a capacitor similar to rectifier D1 114 and capacitor C1 116, respectively, to generate a DC bias voltage while providing a source derived from the rectifier. An alternating current feedback signal of the anode. As such, an additional passive component, such as a resistor, can be used on the bias winding, the voltage being scaled by the winding to a value more suitable for receipt by controller 122.

The bias winding 206 is used to sense the output voltage VO to provide galvanic isolation between the output voltage VO and the controller 122 without the expense of an optocoupler. However, when a winding of an energy transfer element 104 is used to sense the output voltage VO, the voltage VB at the bias winding 206 represents the output voltage VO only when the output rectifier D1 114 is conducting. In other words, the sensing circuit 120 can sense only the output voltage VO during the off-time of the switch S1 110. However, when the switching frequency of the switch S1 110 is high (corresponding to a shorter switching period), the time for sensing the output of the power converter is shorter. As will be further shown, this voltage VB is representative of the output voltage VO and then drops to zero during the off time of a switching cycle. The lighter the load, the faster the output voltage VO drops to zero during the off time. For its part, it takes less time to sense the output voltage VO of the power converter 200. The specific embodiment of the present invention utilizes a multi-stage sampling circuit 132 to quickly obtain the value of the sensed signal USENSE 124 (i.e., the feedback voltage VFB) at a recently feasible time, without the need for a fast, high current buffer. Maintaining the feedback voltage VFB on a large capacitor covers a plurality of switching cycles. As will be further explained, the feedback voltage VFB is tracked by the tracking and holding circuit 220 and quickly maintains the value of the feedback voltage VFB on a small capacitor. Once the value is maintained, the value of the feedback voltage VFB is transferred, via the sample and hold circuit 222, to a larger capacitor which maintains the value for a plurality of Switching the loop and the pulse cycle does not need to worry about the state of the actual feedback voltage VFB.

3 is a functional block diagram illustrating an exemplary controller 322 in accordance with the teachings of the present invention. Controller 322 is a possible application of controller 122 shown in Figures 1 and 2. Examples of the illustration of controller 322 include terminal 123, drive logic (e.g., pulse width modulation (PWM) circuit 302), an oscillator 304, a track hold circuit 306, a sample hold circuit 308, and an adaptive Sampling timer 312. The PWM circuit 302 is shown to include a latch 316, a current limit generator 317, and a comparator 314. The trace hold circuit 306 is shown to include a track hold capacitor 318, a track hold switch S2, a resistor 320, and a buffer 324. The sample and hold circuit 308 is illustrated as including a sample and hold capacitor 330, a sample and hold switch S3, and a buffer 332.

As shown in FIG. 3, trace hold circuit 306 is coupled to terminal 123 to receive sense signal USENSE 124. Within trace hold circuit 306, buffer 324 is coupled to receive signal UFB 124 originating from terminal 123. A buffer 324 is further coupled to the resistor 320 and the resistor 320 is coupled to the switch S2. Switch S2 is coupled to control tracking hold circuit 306 to track or maintain the value output from buffer 324 in response to the enable signal SW2_EN. For example, when switch S2 is energized (i.e., closed), the voltage across capacitor 318 tracks the output of buffer 324. Similarly, when switch S2 is inactive (i.e., turned on), the voltage across capacitor 318 is maintained.

In the illustrated example of FIG. 3, the sample and hold circuit 308 is coupled. The output to the tracking hold circuit 306. Buffer 332 is coupled to receive the output of tracking hold circuit 306 and is further coupled to switch S3. The switch S3 is further coupled to the sample and hold capacitor 330 and coupled to control the sample and hold circuit 308 to sample or hold the value output from the buffer 332 in response to the enable signal SW3_EN. For example, when switch S3 is energized (i.e., closed), the output of voltage integration buffer 332 across capacitor 330 encompasses a sampling period. Similarly, when switch S3 is inactive at the end of the sampling period (i.e., turned on), the voltage across capacitor 330 is maintained. In one embodiment, the capacitance of capacitor 330 is much greater than the capacitance of capacitor 318. For example, capacitor 330 can have a capacitance value that is approximately 10 times the capacitance of capacitor 318. In one embodiment, the complex clock cycle capacitor 318 for the switch S1 110 is small enough to quickly track and acquire the sense signal USENSE 124 while the capacitor 318 is large enough to store and maintain the sense signal USENSE 124 The value (in one embodiment, the feedback voltage VFB shown in Figure 2). By way of example, capacitor 318 can be approximately 5 pF and capacitor 330 can be approximately 50 pF. This value for capacitor 330 is dependent on the process leakage at elevated temperatures and the specifications used for the regulation of the output.

PWM circuit 302 is coupled to the output of sample and hold circuit 308. The PWM circuit 302 generates a drive signal 128 to control the switch S1 110 to adjust the power converter after responding to the output of the sample and hold circuit (i.e., the voltage held on the capacitor 330) and also in response to the current sense signal 126. The output. In particular, current limit generator 317 is coupled to capacitor 330 and outputs a variable current limit after the voltage held on responsive capacitor 330. System threshold 319. In one embodiment, current limit generator 317 includes an error amplifier (not shown) for amplifying the sampled output voltage, as indicated by the value held on capacitor 330, and a difference from a reference value. . The output of the error amplifier can thus be converted to a current limit threshold which is representative of a load condition at the output of the power converter. For example, a high current limit threshold may represent a heavy load condition and a low current limit threshold may represent a light load condition at the output.

Comparator 314 is coupled to compare current sense signal 126 to variable current limit threshold 319 and to disable switch S1 110 (see Figure 2). Comparator 314 is coupled to the reset-input of latch 316, and latch 316 is reset when the current sense signal 126 exceeds the variable current limit threshold 319. Latch 316 is also coupled such that switch S1 110 is enabled via each clock cycle via the clock signal received at the set-in input of latch 316. In one embodiment, the frequency of the oscillator 304 is also the switching frequency of the switch S1 110. However, this is not necessarily applicable under light load operation. In one embodiment, the oscillator 304 generates a clock signal having a fixed frequency such that the switching period T of each switching cycle is fixed. During light load conditions, the power switch S1 110 is not capable of operating at each clock cycle, and the effective switching frequency is below the clock frequency. As such, the capacitor 330 should be large enough to maintain the value of the sensed signal for a number of clock cycles at least until the next switching event.

As shown in FIG. 3, controller 322 also includes an adaptive sampling timer 312. The adaptive sampling timer 312 is compliant to produce adaptive sampling A timer signal AST_SIGNAL, which can be utilized to generate multiple timing signals, controls the operation of track hold circuit 306 and sample and hold circuit 308. For example, the illustrated example of adaptive sampling timer 312 is coupled to provide the adaptive sampling timer signal AST_SIGNAL, which can be utilized to generate the enabling signal SW2_EN and the enabling signal SW3_EN. As mentioned above, the sense signal USENSE 124 may represent the output voltage only during a portion of the time when the power switch S1 is OFF. Accordingly, the adaptive sampling timer 312 can generate the adaptive sampling timer signal AST_SIGNAL such that the length of the logic high segment of the adaptive sampling timer signal AST_SIGNAL is such that when the sensing signal USENSE 124 is provided in relation to the output voltage The representative of the information. Therefore, the adaptive sampling timer 312 controls the tracking and holding circuit 306 such that the capacitor 318 is only at this portion of time (i.e., when the portion of the switch S1 is turned off, the sensing signal USENSE 124 represents The sense signal USENSE 124 is tracked during the output voltage). The time of this portion can be considered as the adaptive sampling time (for example, when the AST_SIGNAL is logic high). Therefore, the adaptive sampling time is at least the time at which the sensed signal USENSE 124 can be part of the representative of the output voltage.

In one embodiment, the adaptive sampling timer signal AST_SIGNAL generates a pulse to a logic high value based on the drive signal. For the example shown in Figure 2, the sense signal USENSE 124 represents the output voltage VO during the turn-off time. For its part, the adaptive sampling timer signal AST_SIGNAL generates a pulse to the logic high value during the turn-off time of the switch S1 110. The length of the logic high section (also That is, the adaptive sampling time can be based on the load conditions. Furthermore, the sampling timer 312 can generate the adaptive sampling timer signal AST_SIGNAL such that the switch S2 is turned on (ie, closed) for a fixed delay time (eg, 0.22 micro) after the power switch S1 110 is turned off. Second), the ringing of the sensing signal USENSE 124, which can occur immediately after the power switch S1 110 is turned off, is allowed to fade.

Moreover, the amount of time that the sensed signal USENSE 124 represents the output voltage can vary as a function of load conditions at the output of the power converter. For example, for light load conditions, the sensed signal USENSE 124 represents the amount of time for the output voltage to be less than the amount of time for a heavy load condition. Accordingly, the adaptive sampling timer 312 is coupled to generate the adaptive sampling timer signal AST_SIGNAL after responding to a load condition signal ULOAD representing the load condition at the output of the power converter. Thus, in one embodiment, the adaptive sampling timer 312 generates the adaptive sampling timer signal AST_SIGNAL such that the adaptive sampling time (eg, switch S2 is closed) as the output of the power converter The load condition at the location changes (eg, between 1.2-2.5 microseconds).

In one embodiment, each of the timing signals SW2_EN and SW3_EN generates a pulse for a fixed period of time after responding to the adaptive sampling timer signal AST_SIGNAL. Although not shown, a monostable multi-resonator can be utilized to generate the enable signals SW2_EN and SW3_EN. Furthermore, the enable signals SW2_EN and SW3_EN generate pulses in response to the adaptive sampling time. Yu Yishi In the example, at the end of the adaptive sampling time, the enable signal SW2_EN falls to a logic low value. Furthermore, at the end of the adaptive sampling time, the enable signal SW3_EN generates a pulse to a logic high value. Thus, the time that the track-and-hold circuit holds the value on capacitor 318 and the time the sample-and-hold circuit samples is also in response to the load condition at the output of the power converter.

As mentioned above, the variable current limit threshold 319 represents the load condition at the output of the power converter. Thus, in one embodiment, the adaptive sampling timer 312 is coupled to receive the output of the current limiting generator 317, and the load condition signal ULOAD is the variable current limiting threshold 319. In another embodiment, the error voltage (the output of the error amplifier in current limit generator 317) can be utilized as the load condition signal ULOAD to determine the load conditions. In these examples, the adaptive sampling timer 312 generates the adaptive sampling timer signal AST_SIGNAL in response to the power switch S1 110 being turned off. In one example, when the adaptive sampling timer signal AST_SIGNAL generates a pulse to a logic high value, charging a capacitor (included in the adaptive sampling timer 312) after responding to the power switch S1 110 being turned off The adaptive sampling timer 312 is started. The current used to charge the capacitor is the difference between a fixed current source and a current representative of the current limit threshold. Once the voltage on the capacitor is increased to a reference voltage, the adaptive sampling timer 312 transitions the adaptive sampling timer signal AST_SIGNAL back to a logic low value. Therefore, when the current limit threshold is lowered, it is included in the adaptive sampling The current charged by the capacitor in timer 312 is increased. As such, in terms of light load conditions, the time it takes to charge the capacitor and the adaptive sampling time will be reduced. The adaptive sampling timer 312 can further include one or more monostable multi-resonators (eg, one-shots) that are triggered by the adaptive sampling timer signal AST_SIGNAL to generate the timing signal SW2_EN and SW3_EN.

4 is an exemplary voltage and current waveform and clock signal associated with an exemplary multi-stage sampling circuit, such as that included in controller 322 of FIG. 3, in accordance with the teachings of the present invention. The waveforms and clock signals of Figure 4 are illustrated with further reference to Figures 1-3.

The bias winding voltage VB and the drive signal are shown at the top of FIG. As shown in FIG. 4, the bias winding voltage VB (and the feedback voltage VFB) is representative of the line input voltage VIN during the on time of the switch S1 (eg, when the drive signal is HIGH). And representing the output voltage VO during the off time of switch S1 (eg, when the drive signal is LOW). At the beginning of the switching cycle T1, the AST_SIGNAL is LOW. Furthermore, the enable signal SW2_EN is low (LOW) and the capacitor 318 does not track the sense signal USENSE 124. At the beginning of the switching cycle T1, the sense signal USENSE 124 is representative of the output voltage via the bias winding voltage VB.

As shown in Figure 4, there is a click in the bias winding voltage when the switch is turned off for the first time. Thus, the adaptive sampling timer 312 can delay determining the AST_SIGNAL to allow a sound to be heard for the first fade. In a specific embodiment, this is determining the AST_SIGNAL and the enabling signal. The delay before SW2_EN is a fixed delay. Once the AST_SIGNAL is determined (i.e., transitioned to a logic high), the enable signal SW2_EN transitions to a logic high value and the capacitor 318 begins tracking the sense that the current representative voltage represents the output voltage via the feedback voltage VFB. Signal USESE 124.

This amount of time is due to the load condition at the output of the power converter before the bias winding voltage VB drops to zero. Therefore, the amount of time that the bias winding voltage VB represents the output voltage VO is also dependent on the load conditions. For example, the lighter the load, the shorter the bias winding voltage VB represents the output voltage. Accordingly, the adaptive sampling timer 312 provides an adaptive sampling time 402 responsive to the load conditions to allow for efficient feedback information to the multi-level sampling circuit 132.

At the end of the adaptive sampling time 402, the AST_SIGNAL is transitioned to a logic low (LOW). At the same time as the end of the adaptive sampling time 402, the enable signal SW2_EN switches to a logic low (LOW) for maintaining the value on the tracking hold capacitor 318. At the end of the adaptive sampling time 402, the switch S2 is turned on (i.e., disabled), and to some extent, since the sound actually fades in the sensed signal USENSE 124 at this time, a more accurate representation is ensured. The output voltage is maintained on the tracking hold capacitor 318.

At the end of the adaptive sampling time 402, the enable signal SW3_EN transitions to a logic high (HIGH) value. When SW3_EN transitions to a logic high value to enable switch S3 to operate, capacitor 330 begins sampling the value maintained on tracking hold capacitor 318. Capacitor 330 is integrated into the tracking This value maintained on hold capacitor 318 covers a sample period (i.e., the time at which the SW3_EN signal is HIGH). In one embodiment, the time during which the SW3_EN signal is high is a fixed period. At the end of the sampling period of the sample and hold circuit 308, the value maintained on the track holding capacitor 318 is now held on the capacitor 330 for use by the drive logic 302 when adjusting the output of the power converter. Over time, a capacitor will discharge and lose the value (ie, voltage) stored on the capacitor. A larger capacitor will hold its value longer than a smaller capacitor. As discussed above, the capacitance value of capacitor 330 is large (e.g., 50 pF) such that the sample held on capacitor 330 is active for several clock cycles. Therefore, the drive logic 302 can continue to obtain valid feedback information even in the absence of switching conditions. Meanwhile, as shown in FIG. 4, the sampling by the sample and hold circuit 308 can be performed even after the bias winding voltage VB, and thus the sense signal USENSE 124, no longer represents the output voltage.

The above description of the illustrated examples of the invention, including the description of the invention, is not intended to be exhaustive or limited to the precise forms disclosed. Although the specific embodiments and examples of the present invention are described herein for the purpose of illustration, various modifications and equivalents may be made without departing from the spirit and scope of the invention. Rather, it is to be appreciated that such specific voltages, currents, frequencies, power range values, times, etc. are provided for purposes of explanation, and that teachings in accordance with the present invention may be utilized in other specific examples and examples. Use other values.

Such modifications may be made to the examples of the invention in light of the above detailed description. The terms used in the following claims are not to be construed as limiting the invention to the particular embodiments disclosed herein. Rather, the scope of the invention is determined by the following claims, which are inferred from the principles of the invention. The description and drawings are to be regarded as illustrative rather

100‧‧‧Power Converter

102‧‧‧Input voltage

104‧‧‧ energy transfer element

106‧‧‧First winding

108‧‧‧second winding

110‧‧‧ switch

111‧‧‧Input circuit

112‧‧‧Clamping circuit

114‧‧‧Rectifier

116‧‧‧Output capacitor

117‧‧‧Output circuit

118‧‧‧ load

120‧‧‧Sensor circuit

122‧‧‧ Controller

123‧‧‧Single feedback terminal

124‧‧‧Sensing signal

125‧‧‧ integrated circuit

126‧‧‧ Current sensing signal

128‧‧‧ drive signal

130‧‧‧Switching current

132‧‧‧Multi-level sampling circuit

134‧‧‧Drive Logic

200‧‧‧Power Converter

206‧‧‧ bias winding

208‧‧‧Resistors

210‧‧‧Resistors

220‧‧‧ Tracking and holding circuit

222‧‧‧Sampling and holding circuit

302‧‧‧Drive Logic

304‧‧‧Oscillator

306‧‧‧ Tracking and holding circuit

308‧‧‧Sampling and holding circuit

312‧‧Sampling timer

314‧‧‧ comparator

316‧‧‧Latch

317‧‧‧ Current Limit Generator

318‧‧‧ Tracking Holding Capacitors

319‧‧‧Variable current limit threshold

320‧‧‧Resistors

322‧‧‧ Controller

324‧‧‧buffer

330‧‧‧Sampling and holding capacitor

332‧‧‧buffer

402‧‧‧Adaptable sampling time

UO‧‧‧ output

IO‧‧‧ output current

NP‧‧‧ turns of primary winding

NS‧‧‧ turns of secondary winding

VO‧‧‧ output voltage

VP‧‧‧Variable voltage over time

VFB‧‧‧ feedback voltage

VB‧‧‧ bias winding voltage

S2‧‧‧ Tracking keep-alive switch

S3‧‧‧Sampling and holding switch

SW2_EN‧‧‧Energy signal

SW3_EN‧‧‧Energy signal

T‧‧‧ switching cycle

T1-T4‧‧‧ switching cycle

AST_SIGNAL‧‧‧Sampling timer signal

ULOAD‧‧‧ load status signal

VIN‧‧‧ line input voltage

The non-limiting and non-exhaustive examples of the present invention are described in the accompanying drawings, in which the same reference

1 is a functional block diagram illustrating an exemplary power converter including a controller in accordance with the teachings of the present invention.

2 is a functional block diagram illustrating an exemplary power converter having a sensing circuit including a primary reference winding in accordance with the teachings of the present invention.

3 is a functional block diagram illustrating an exemplary controller in accordance with the teachings of the present invention.

4 is an exemplary voltage and current waveform and clock signal associated with an exemplary multi-stage sampling circuit in accordance with the teachings of the present invention.

100‧‧‧Power Converter

102‧‧‧Input voltage

104‧‧‧ energy transfer element

106‧‧‧First winding

108‧‧‧second winding

110‧‧‧ switch

111‧‧‧Input circuit

112‧‧‧Clamping circuit

114‧‧‧Rectifier

116‧‧‧Output capacitor

117‧‧‧Output circuit

118‧‧‧ load

120‧‧‧Sensor circuit

122‧‧‧ Controller

123‧‧‧Single feedback terminal

124‧‧‧Sensing signal

125‧‧‧ integrated circuit

126‧‧‧ Current sensing signal

128‧‧‧ drive signal

130‧‧‧Switching current

132‧‧‧Multi-level sampling circuit

134‧‧‧Drive Logic

Claims (15)

An integrated circuit controller for a power converter, the controller comprising: a tracking and holding circuit coupled to receive a signal from a single terminal of the controller, the signal being used to represent a first switch One of the power converters outputs a voltage during at least a portion of the time, wherein the tracking and holding circuit includes a first capacitor coupled to provide a first voltage, the turn-off time of the first switch Tracking the signal during the portion and maintaining the first voltage at the end of the portion of the turn-off time; a sample-and-hold circuit coupled to the track-and-hold circuit for maintaining the first voltage at the Sampling the first voltage on the first capacitor, wherein the sample and hold circuit includes a second capacitor coupled to integrate the output of the first capacitor to cover a sampling period, and an on time below the first switch Ending and maintaining a second voltage representative of the first voltage after a sampling period, wherein the second capacitor has a capacitance value that is greater than the first The capacitance value of the container; and a drive logic coupled to the sample and hold circuit coupled to control the output of a first one of the switching regulator after the power converter in response to the second voltage. The controller of claim 1, wherein the signal received from the single terminal does not represent the output of the power converter when the sample and hold circuit samples the first voltage held on the first capacitor Voltage. The controller of claim 1, wherein the tracking and holding circuit further comprises a tracking and holding switch coupled to the first capacitor, wherein the A voltage is tracked as the track-and-hold switch functions and remains when the track-and-hold switch fails. A controller of claim 3, further comprising an adaptive sampling timer coupled to the tracking hold circuit to control the tracking hold switch. The controller of claim 4, wherein the adaptive sampling timer is adapted to cause the tracking hold switch to disable the tracking hold switch after responding to a load condition at the output of the power converter To maintain the first voltage on the first capacitor. The controller of claim 4, wherein the sample hold circuit further comprises a sample hold switch coupled to the second capacitor, wherein the sampling period begins when the sample hold relationship can function, and the sampling The second voltage is maintained on the second capacitor when the switch is disabled. The controller of claim 1, wherein the first open relationship is included in the integrated circuit controller. A power converter comprising: an energy transfer element; a first switch coupled to the energy transfer element to control energy transfer via the energy transfer element; and a controller coupled to the first switch The controller includes: a tracking and holding circuit coupled to receive a signal from a single terminal of the controller for indicating the power conversion during at least a portion of a turn-off time of the first switch One of the output voltages, The tracking and holding circuit includes a first capacitor coupled to provide a first voltage that tracks the signal during the portion of the first switch that is off and at the end of the portion of the turn-off time Holding the first voltage; a sample and hold circuit coupled to the tracking and holding circuit for sampling the first voltage when the first voltage is held on the first capacitor, wherein the sample and hold circuit includes a The second capacitor is coupled to integrate the output of one of the first capacitors to cover a sampling period that ends before an opening time of the first switch and to maintain one of the first voltages after a sampling period a second voltage, wherein the second capacitor has a capacitance value that is greater than the capacitance value of the first capacitor; and drive logic coupled to the sample and hold circuit and coupled to control the first switch in response to the The output of one of the power converters is adjusted after the second voltage. The power converter of claim 8 wherein the signal received from the single terminal does not represent the output voltage of the power converter when the sample and hold circuit samples the first voltage on the first capacitor . The power converter of claim 8, wherein the tracking and holding circuit further comprises a tracking hold switch coupled to the first capacitor, wherein the first voltage is tracked while the tracking hold switch is active and remains in the tracking Maintained when the switch fails. For example, the power converter of claim 10, wherein the controller One step includes an adaptive sampling timer coupled to the tracking hold circuit to control the tracking hold switch. The power converter of claim 11, wherein the adaptive sampling timer is adapted to cause the tracking hold switch to cause the tracking hold switch after responding to a load condition at the output of the power converter Failed to maintain the first voltage on the first capacitor. The power converter of claim 11, wherein the sample hold circuit further comprises a sample hold switch coupled to the second capacitor, wherein the sampling period begins when the sample hold relationship can function, and The second voltage is maintained on the second capacitor when the sample hold switch fails. A power converter as in claim 8 further comprising a sensing circuit coupled to provide the signal to the controller, the sensing circuit comprising one of the energy transfer elements, a reference winding, wherein the crossing a voltage of the primary reference winding represents the output voltage during at least the portion of the first switch of the turn-off time and is representative of the power converter during at least a portion of the turn-on time of the first switch One line input voltage. The power converter of claim 8, wherein the controller and the first open relationship are included in a single integrated circuit.