TWI491172B - Oscillator apparatus embedded in chip - Google Patents

Description

In-wafer oscillating device

The present invention relates to an in-wafer oscillating device, and more particularly to an in-wafer oscillating device that can adjust and set the frequency of the generated oscillating output signal.

In a conventional integrated circuit, the adjustment operation of the frequency of the oscillation output signal generated by the oscillation circuit in the wafer is usually performed by a wafer level (Chip Probing, CP) test operation before the wafer is packaged. carry out. However, due to the parasitic resistance, parasitic capacitance and parasitic inductance effect of the chip package on the wafer package, the oscillating output signal generated by the internal oscillating circuit after the wafer is packaged The frequency will drift to some extent.

It is worth noting that the frequency drift of the above oscillating output signal does not have a fixed trend. Therefore, there is no way to compensate for the frequency of the oscillation output signal generated by the built-in oscillation circuit of the wafer that has been packaged by a simple compensation method. Therefore, in the prior art, the chip often causes the frequency of the oscillating output signal generated by the built-in oscillating circuit to exceed the specification due to the package, resulting in a decrease in yield.

The present invention provides an intra-wafer oscillating device that can effectively adjust the frequency of the generated oscillating output signal after the wafer is packaged.

The invention provides an intra-wafer oscillating device comprising a selector, an oscillating circuit, a control circuit and a reservoir. The selector selects to output external input data or store data according to the control signal as the selected data. The oscillating circuit is coupled to the selector, and the oscillating circuit receives the selected data and generates an oscillating output signal. The oscillating circuit adjusts the frequency of the oscillating output signal according to the selected data. The control circuit is coupled to the selector. The control circuit receives the test mode enable signal and generates a control signal according to the test mode enable signal. The storage is coupled to the controller and the selector for providing stored data. The control circuit further generates a data write command, and writes the external input data to the memory by using a data write command.

In an embodiment of the invention, the control circuit device further receives the read command and reads the stored data in the memory according to the read command.

In an embodiment of the invention, when the test mode activation signal indicates that the test action is initiated, the control circuit generates a control signal to cause the selector to select to output the external input data as the selected data.

In an embodiment of the invention, wherein the intra-wafer oscillating device further comprises an internal circuit. The internal circuit is coupled to the control circuit and the oscillating circuit. The internal circuitry is based on an external command to generate a test mode enable signal. The internal circuit and when the frequency of the oscillating output signal enters the frequency range of the preset specification, causes the control circuit to generate a data write command to write the external input data to the memory.

In an embodiment of the invention, the oscillating circuit includes a current source, a first charging circuit, a second charging circuit, and an output signal generating circuit. The current source provides a charging current. The first charging circuit and the second charging circuit are coupled The current source, wherein the first charging circuit and the second charging circuit alternately receive the charging current to perform a charging operation, and thereby generate the first charging voltage and the second charging voltage, respectively. The output signal generating circuit is coupled to the first charging circuit and the second charging circuit to receive the first and second charging voltages and the preset voltage. The output signal generating circuit compares the preset voltage with the first and second charging voltages to set a logic level of the oscillating output signal.

In an embodiment of the invention, the current source receives and adjusts the current value of the charging current according to the selected data.

In an embodiment of the invention, the oscillating circuit further includes a reference current source. The reference current source is coupled to the current source and generates a reference current according to the reference voltage to provide to the current source to cause the current source to generate a charging current according to the mirror reference current.

In an embodiment of the invention, the oscillating circuit further includes a voltage generator. The voltage generator is coupled to the reference current source for generating a reference voltage according to the selected data.

In an embodiment of the invention, the voltage generator is further coupled to the output signal generating circuit. The voltage generator generates a preset voltage to provide to the output signal generating circuit.

In an embodiment of the invention, the first charging circuit includes a first switch, a first variable capacitor, and a second switch. The first end of the first switch is coupled to the current source. The first switch is controlled by a switch control signal to be turned on or off. The first variable capacitor is connected in series between the second end of the first switch and the reference ground voltage. The second switch is also connected in series between the second end of the first switch and the reference ground voltage. The second switch is controlled by the switch control signal to be turned on or off open. The first and second switches are opposite in conduction and disconnection.

In an embodiment of the invention, the second charging circuit includes a third switch, a second variable capacitor, and a fourth switch. The first end of the third switch is coupled to the current source, and the third switch is controlled by the switch control signal to be turned on or off. The second variable capacitor is connected in series between the second end of the third switch and the reference ground voltage. The fourth switch is connected in parallel with the second variable capacitor, and the fourth switch is controlled by the switch control signal to be turned on or off. The third and fourth switches are turned on and off in opposite directions, and the third and first switches are turned on and off in opposite directions.

In an embodiment of the invention, the capacitance value of at least one of the first variable capacitor and the second variable capacitor is changed according to the selected data.

In an embodiment of the invention, the output signal generating circuit described above provides an oscillating output signal as a switch control signal.

In an embodiment of the invention, the output signal generating circuit includes a first comparator, a second comparator, and an SR latch. One input of the first comparator receives the preset voltage and the other input receives the first charging voltage. One input of the second comparator receives the preset voltage and the other input receives the second charging voltage. The SR latch has a set end, a reset end and an output end, the set end is coupled to the output end of the first comparator, and the reset end of the SR latch is coupled to the output end of the second comparator, the SR latch The output of the lock produces an oscillating output signal.

In an embodiment of the invention, the storage device is a non-volatile memory.

Based on the above, the present invention utilizes a selector to receive external input data to adjust the frequency of the oscillating output signal generated by the oscillating circuit, and writes the corresponding external input data to the storage when the frequency of the oscillating output signal meets the specifications required by the design. In the device. Then, through the selector, the stored data in the memory is selected to set the frequency of the oscillation output signal generated by the oscillation circuit. In this way, the frequency of the oscillating output signal can be effectively controlled within a range that meets the preset specifications, thereby improving the production yield of the wafer.

The above described features and advantages of the present invention will be more apparent from the following description.

Please refer to FIG. 1. FIG. 1 is a schematic diagram of an intra-wafer oscillating device 100 according to an embodiment of the present invention. The intra-wafer oscillating device 100 includes a selector 110, an oscillating circuit 120, a control circuit 130, and a memory 140. The selector 110 selectively outputs the external input material ODAT or the stored material SDAT as the selected material SELD according to the control signal CTR. The external input data ODAT may be data input from outside the wafer when the test mode of the wafer is activated. That is, the external input data ODAT can be transmitted to the oscillating circuit 120 as the selected material SELD when the test mode of the wafer is activated by the selector 110. The oscillating circuit 120 changes the frequency of the oscillating output signal CKOUT generated by the oscillating circuit 120 according to the accepted selected data SELD. Therefore, when the test mode is activated, the frequency of the oscillating output signal CKOUT generated by the oscillating circuit 120 and the selected data can be measured by inputting a plurality of different values of the external input data ODAT to the chip. Correspondence between SELDs.

In addition, the stored data SDAT is provided by the storage 140, and the selector 110 selects the stored data SDAT as the selected data SELD to be transmitted to the oscillating circuit 120 when the test mode of the wafer is turned off. That is, when the test mode of the wafer is turned off (that is, when the wafer is in the normal mode), the selector 110 provides the stored data SDAT as the selected data SELD to cause the oscillation circuit 120 to generate the oscillation output signal CKOUT.

The control circuit 130 is coupled to the selector 110 and the storage 140. The control circuit 130 receives the test mode enable signal TEN and generates a control signal CTR according to the test mode enable signal TEN, and transmits the control signal CTR to the selector 110. Specifically, when the test mode enable signal TEN indicates that the test mode of the wafer is the activated state, the control circuit 130 transmits the control signal CTR to cause the selector 110 to select the external input data ODAT as the selected data SELD. Conversely, when the test mode enable signal TEN indicates that the test mode of the wafer is turned off, the control circuit 130 transmits a control signal CTR to cause the selector 110 to select the stored data SDAT as the selected material SELD.

At the same time, when the test mode start signal TEN indicates that the test mode of the wafer is changed from the activated state to the closed state, the control circuit 130 correspondingly generates the data write command WCMD, and transmits the data write command WCMD to the memory. 130 is such that the external input material ODAT at this time is written in the storage 130 to become the storage material SDAT. That is to say, when the test mode of the wafer is turned off and returns to the normal mode, the frequency of the oscillating output signal CKOUT generated by the oscillating circuit 120 is based on the storage resource. Set by SDAT.

Incidentally, the test mode enable signal TEN can be supplied from a test machine (not shown) external to the wafer through a test pin provided on the wafer. The test mode enable signal TEN can also be decoded by the internal circuit of the in-wafer oscillating device 100 in accordance with command data received by the test machine outside the wafer. Of course, the above command data can also be received by the test machine outside the wafer through one or more pins on the wafer.

Regarding the overall operation of the intra-wafer oscillating device 100, first, after receiving the test mode enable signal TEN indicating that the wafer is to start the test mode, the control circuit 130 correspondingly transmits a control signal CTR of, for example, a logic level "1" to the selector 110. Moreover, the tester (for example, the test machine) transmits the external input data ODAT from outside the wafer, and selects the external input data ODAT through the selector 110 to become the selected data SELD to control the frequency of the oscillation output signal CKOUT generated by the oscillation circuit 120. Then, the test machine can adjust the provided external input data ODAT by detecting the frequency of the oscillating output signal CKOUT and the frequency range in the preset specification, so that the frequency of the oscillating output signal CKOUT can enter the preset specification. The frequency range.

For example, if the selected data SELD (which is equal to the external input data ODAT) is proportional to the frequency of the oscillation output signal CKOUT, when the frequency of the oscillation output signal CKOUT is lower than the lower limit of the frequency range in the preset specification, Correspondingly, the value of the external input data ODAT is increased, and when the frequency of the oscillation output signal CKOUT is higher than the frequency range in the preset specification When the upper limit of the circumference is exceeded, the value of the external input data ODAT is lowered accordingly. Of course, if the selected data SELD (which is equal to the external input data ODAT) is inversely proportional to the frequency of the oscillation output signal CKOUT, when the frequency of the oscillation output signal CKOUT is lower than the lower limit of the frequency range in the preset specification, The value of the external input data ODAT is lowered. In contrast, when the frequency of the oscillation output signal CKOUT is higher than the upper limit of the frequency range in the preset specification, the value of the external input data ODAT is increased accordingly.

When the frequency of the oscillation output signal CKOUT is adjusted to fall within the frequency range of the preset specification (the frequency of the oscillation output signal CKOUT is usually adjusted to be equal to the center point of the frequency range in the preset specification), the test mode start signal TEN Indicates that the test mode is turned off. The control circuit 130 correspondingly generates and transmits a control signal CTR of a logic level "0" to the selector 110. At the same time, the control circuit 130 generates a data write command WCMD and transmits a data write command WCMD to the memory 140 so that the external input data ODAT at this time can be written to the storage 140.

Incidentally, the above-mentioned external input data ODAT written in the memory 140 can set the frequency range in which the frequency of the oscillation output signal CKOUT generated by the oscillation circuit 120 falls within a preset specification. Therefore, when the wafer is in the normal mode, the frequency of the oscillation output signal CKOUT set according to the selected data SELD equal to the stored data SDAT can conform to the frequency range set by the preset specification.

Referring to FIG. 2, FIG. 2 is a schematic diagram of an intra-wafer oscillating device 200 according to another embodiment of the present invention. The intra-wafer oscillating device 200 includes a selector 210, an oscillating circuit 220, a control circuit 230, and a non-volatile memory 240. And an internal circuit 250. Unlike the one embodiment, the intra-wafer oscillating device 200 further includes an internal circuit 250. The internal circuit 250 is coupled to the control circuit 230 and the oscillating circuit 220. The internal circuit 250 generates a test mode enable signal TEN in accordance with an external command OINS. The internal circuit 250 receives the oscillation output signal CKOUT to perform an alignment operation of the frequency of the oscillation output signal CKOUT and the frequency range of the preset specification of the oscillation frequency. The internal circuit 250 causes the control circuit 230 to generate a data write command WCMD to write the external input data ODAT to the non-storage memory when the frequency of the oscillation output signal CKOUT enters the frequency range of the preset specification through the test mode enable signal TEN. Volatile memory 240.

On the other hand, the internal circuit 250 can also transmit the read command RCMD, and drive the control circuit 230 to perform the data reading operation on the non-volatile memory 240, and store the stored data SDAT in the non-volatile memory 240. Transfer to control circuit 230 (or to internal circuit 250).

Please refer to FIG. 3, which illustrates an embodiment of an oscillating circuit 120 according to an embodiment of the present invention. The oscillation circuit 120 includes a current source 321, a charging circuit 322, 323, and an output signal generating circuit 324. The current source 321 is coupled to the operating voltage VDD and provides a charging current Ir2. The charging circuits 322 and 323 are coupled to the current source 321 and alternately receive the charging current Ir2 to perform a charging operation. The charging circuits 322, 323 are alternately charged in accordance with the charging current Ir2 in different time intervals, and thereby generate charging voltages SV1 and SV2.

The output signal generating circuit 324 is coupled to the charging circuits 322 and 323, And receiving the charging voltages SV1, SV2 and the preset voltage Vr1. The output signal generating circuit 324 compares the preset voltage Vr1 with the charging voltages SV1 and SV2, respectively, and sets the logic level of the oscillating output signal CKOUT.

Specifically, when the charging circuit 322 receives the charging current Ir2 to perform the charging operation, the path of the charging circuit 323 receiving the charging current Ir2 is cut off. At this time, the charging voltage SV1 supplied from the charging circuit 322 gradually rises and the charging voltage SV2 supplied from the charging circuit 323 is maintained at a fixed voltage level (for example, 0 volt). The output signal generating circuit 324 performs the comparison operation of the charging voltage SV1 and the preset voltage Vr1, and when the charging voltage SV1 is greater than the preset voltage Vr1, the output signal generating circuit 324 sets the logic level of the oscillation output signal CKOUT to be equal to, for example, logic. Level "1".

At the same time, the charging operation of the charging circuit 322 is completed, and the charging operation of the charging circuit 323 is started. While the charging circuit 323 is charging, the charging circuit 322 performs a discharge operation and causes the charging voltage SV1 to drop to, for example, 0 volts. In addition, the output signal generating circuit 324 performs a comparison operation of the charging voltage SV2 and the preset voltage Vr1, and when the charging voltage SV2 is greater than the preset voltage Vr1, the output signal generating circuit 324 sets the logic level of the oscillation output signal CKOUT to be equal to, for example, The logic level is "0".

As can be seen from the above description, the oscillation circuit 120 can cause the output signal generating circuit 324 to generate the oscillation output signal CKOUT by the alternate charging operation of the charging circuits 322 and 323. By controlling the charging voltages SV1 and SV2 to rise to a time greater than the preset voltage Vr1, it is possible to control The frequency of the oscillation output signal CKOUT.

Incidentally, in the present embodiment, the charging circuits 322 and 323 can determine whether to perform charging according to the switching control signals SCTR and SCTRB, respectively, wherein the switching control signal SCTR is an inverted signal of the switching control signal SCTRB.

Please refer to FIG. 4. FIG. 4 illustrates another embodiment of the oscillating circuit 120 according to an embodiment of the present invention. The oscillator circuit 120 includes a current source 421, charging circuits 422 and 423, an output signal generating circuit 424, a reference current source 427, and a voltage generator 429. The charging circuit 422 includes switches SW1, SW2 and a variable capacitor C1. The first end of the switch SW1 is coupled to the current source 421, and the switch SW1 is controlled by the switch control signal SCTR to be turned on or off. The variable capacitor C1 is connected in series between the second end of the switch SW1 and the reference ground voltage GND. The switch SW2 is connected in series between the second end of the switch SW1 and the reference ground voltage GND. The switch SW2 is also controlled by the switch control signal SCTR to be turned on or off. Among them, the operations of turning on and off the switches SW1 and SW2 are reversed.

The charging circuit 423 includes switches SW3, SW4 and a variable capacitor C2. The first end of the switch SW3 is coupled to the current source 421, and the switch SW3 is controlled by the switch control signal SCTRB to be turned on or off. The variable capacitor C2 is connected in series between the second end of the switch SW3 and the reference ground voltage GND. The switch SW4 is connected in series between the second end of the switch SW3 and the reference ground voltage GND. The switch SW4 is also controlled by the switch control signal SCTRB to be turned on or off. The operation of turning on and off the switches SW3 and SW4 is reversed, and the operations of turning on and off the switches SW1 and SW3 are performed. The opposite is true.

That is, when the switch SW1 is in the on state (the switch SW2 is off), the charging circuit 422 receives the charging current Ir2 to cause the variable capacitor C1 to proceed and gradually increase the charging voltage SV1. At the same time, the switch SW3 is turned off, and the switch SW4 is turned on. The variable capacitor C2 at this time is discharged, and the charging voltage SV2 is equal to the reference ground voltage GND. In contrast, when the switch SW3 is in the on state (the switch SW4 is off), the charging circuit 423 receives the charging current Ir2 to cause the variable capacitor C2 to proceed and gradually increase the charging voltage SV2. At the same time, the switch SW1 is off and the switch SW2 is on. The variable capacitor C1 at this time is discharged, and the charging voltage SV1 is equal to the reference ground voltage GND.

The output signal generating circuit 424 in the present embodiment includes comparators CMP1, CMP2 and an SR latch SR1. One input of the comparator CMP1 receives the preset voltage Vr1, and the other input receives the charging voltage SV1. One input of the comparator CMP2 receives the preset voltage Vr1, and the other input receives the charging voltage SV2. The SR latch SR1 has a set terminal S, a reset terminal R, and output terminals Q and QN. The set terminal S of the SR latch SR1 is coupled to the output of the comparator CMP1. The reset terminal R of the SR latch SR1 is coupled to the output of the comparator CMP2, and the output terminal Q of the SR latch SR1 oscillates. The output signal CKOUT is output, and the output terminal QN of the SR latch SR1 generates the inverted signal CKOUTN of the oscillating output signal CKOUT. The preset voltage Vr1 in this embodiment is generated by the voltage generator 429.

The SR latch SR1 compares the charging voltage SV1 at the comparator CMP1 When the voltage is greater than the preset voltage Vr1, the oscillation output signal CKOUT is set to a logic level "1", and the SR latch SR1 sets the oscillation output signal CKOUT to a logic level when the comparator CMP2 compares the charging voltage SV2 to be greater than the preset voltage Vr1. Bit "0".

The output signal generating circuit 424 supplies the oscillating output signal CKOUT as the switch control signal SCTR and provides the inverted signal CKOUTN of the oscillating output signal CKOUT as the switch control signal SCTRB.

It is not difficult to find from the above description that the frequency of the oscillation output signal CKOUT of the oscillation circuit 120 in the present embodiment can be completed by controlling the charging time of at least one of the charging circuits 422 and 423. The frequency of the oscillation output signal CKOUT can be effectively controlled by controlling at least one of the magnitude of the charging current Ir2 generated by the current source 421, the capacitance of the variable capacitor C1, and the capacitance of the variable capacitor C2.

In the present embodiment, the charging current Ir2 generated by the current source 421 is generated according to the reference current generated by the mirror reference current source 427, and the reference current source 427 is coupled to the voltage generator 429 to receive the voltage generator. The reference voltage Vr2 generated by 429. In addition, the voltage generator 429 can receive the selected data SELD and generate the reference voltage Vr2 according to the selected data SELD. That is to say, the oscillating circuit 120 in the present embodiment can adjust the charging current Ir2 generated by the current source 421 according to the selected data SELD, and thereby adjust the frequency of the oscillating output signal CKOUT.

In addition, the capacitance values of the variable capacitors C1 and C2 can also be adjusted according to the selected data SELD, and thereby control the frequency of the oscillation output signal CKOUT.

In summary, the present invention adjusts the frequency of the oscillating output signal generated by the oscillating circuit through external input data, and writes the external input data into the memory when the frequency of the oscillating output signal falls within the frequency range of the preset specification. . When the wafer enters the normal mode, the stored data in the memory is read to set the frequency of the oscillating output signal. In this way, each intra-wafer oscillating device can generate an oscillating output signal conforming to the specification to ensure that the wafer can operate normally, and effectively improve the yield of the packaged wafer.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100,200‧‧‧In-wafer oscillating device

110, 210‧‧‧Selector

120, 220‧‧‧Oscillation circuit

130, 230‧‧‧Control circuit

140‧‧‧Storage

240‧‧‧ Non-volatile memory

250‧‧‧Internal circuits

321, 421‧‧‧ current source

322, 323, 422, 423‧‧‧ charging circuits

324, 424‧‧‧ Output signal generation circuit

427‧‧‧Reference current source

429‧‧‧Voltage generator

VDD‧‧‧ operating voltage

Ir2‧‧‧Charging current

OINS‧‧‧External instructions

CTR‧‧‧ control signal

ODAT‧‧‧ external input data

SDAT‧‧‧Storage information

SELD‧‧‧Selected materials

CKOUT‧‧‧ oscillating output signal

TEN‧‧‧ test mode start signal

WCMD‧‧‧ Data Write Command

RCMD‧‧‧ read command

SV1, SV2‧‧‧ charging voltage

Vr1‧‧‧Preset voltage

SCTR, SCTRB‧‧‧ switch control signals

SW1~SW4‧‧‧ switch

C1, C2‧‧‧ variable capacitor

GND‧‧‧reference ground voltage

SR1‧‧‧SR latch

S‧‧‧Setting end

R‧‧‧Reset end

Q, QN‧‧‧ output

CMP1, CMP2‧‧‧ comparator

CKOUTN‧‧‧reverse signal

FIG. 1 is a schematic diagram of an intra-wafer oscillating device 100 according to an embodiment of the invention.

2 is a schematic diagram of an intra-wafer oscillating device 200 according to another embodiment of the present invention.

FIG. 3 illustrates an embodiment of an oscillating circuit 120 in accordance with an embodiment of the present invention.

FIG. 4 illustrates another embodiment of an oscillating circuit 120 in accordance with an embodiment of the present invention.

100‧‧‧In-wafer oscillating device

110‧‧‧Selector

120‧‧‧Oscillation circuit

130‧‧‧Control circuit

140‧‧‧Storage

CTR‧‧‧ control signal

ODAT‧‧‧ external input data

SDAT‧‧‧Storage information

SELD‧‧‧Selected materials

CKOUT‧‧‧ oscillating output signal

TEN‧‧‧ test mode start signal

WCMD‧‧‧ Data Write Command

Claims (15)

An intra-wafer oscillating device includes: a selector for selectively outputting an external input data or a stored data as a selected data according to a control signal; an oscillating circuit coupled to the selector, receiving the selected data and generating An oscillating output signal, wherein the oscillating circuit adjusts the frequency of the oscillating output signal according to the selected data; a control circuit is coupled to the selector, the control circuit receives a test mode start signal and generates the signal according to the test mode start signal a control signal; and a memory coupled to the controller and the selector for providing the stored data, wherein the control circuit further generates a data write command, and the external input is input by the data write command The data is written to the storage. The intra-wafer oscillating device of claim 1, wherein the control circuit further receives a read command and reads the stored data in the memory according to the read command. The intra-wafer oscillating device of claim 1, wherein the test mode enable signal indicates that a test action is initiated, the control circuit generates the control signal to cause the selector to select and output the external input data as the selected data. The intra-wafer oscillating device of claim 3, further comprising: an internal circuit coupled to the control circuit and the oscillating circuit, the inner The circuit is configured to generate the test mode enable signal according to an external command, and when the frequency of the oscillating output signal enters a frequency range of a preset specification, the control circuit generates the data write command to the external Input data is written to this storage. The intra-wafer oscillating device of claim 1, wherein the oscillating circuit comprises: a current source to provide a charging current; a first charging circuit coupled to the current source; and a second charging circuit coupled The current source, wherein the first charging circuit and the second charging circuit alternately receive the charging current to perform a charging operation, and respectively generate a first charging voltage and a second charging voltage; and an output signal generating circuit, The first charging circuit and the second charging circuit are coupled to receive the first and second charging voltages and a predetermined voltage, and the output signal generating circuit is configured to the preset voltage and the first and second charging voltages Compare and set the logic level of the oscillating output signal. The intra-wafer oscillating device of claim 5, wherein the current source receives and adjusts the current value of the charging current according to the selected data. The intra-wafer oscillating device of claim 5, wherein the oscillating circuit further comprises: a reference current source coupled to the current source, the reference current source generating a reference current according to a reference voltage to provide the The current source is based on the mirror A reference current is generated to generate the charging current. The oscillating circuit further includes: a voltage generator coupled to the reference current source for generating the reference voltage according to the selected data. The intra-wafer oscillating device of claim 8, wherein the voltage generator is further coupled to the output signal generating circuit, and the voltage generator generates the predetermined voltage to be supplied to the output signal generating circuit. The intra-wafer oscillating device of claim 5, wherein the first charging circuit comprises: a first switch having a first end coupled to the current source, the first switch being controlled by a switch control signal Turning on or off; a first variable capacitor connected in series between the second end of the first switch and a reference ground voltage; and a second switch connected in series at the second end of the first switch and the Between the reference ground voltages, the second switch is controlled to be turned on or off by the switch control signal, wherein the first switch is opposite to the on and off actions of the second switch. The in-wafer oscillating device of claim 10, wherein the second charging circuit comprises: a third switch having a first end coupled to the current source, the third switch being controlled by the switch control signal Turning on or off; a second variable capacitor connected in series at the second end of the third switch and the Referring to a ground voltage; and a fourth switch connected in series between the second end of the third switch and the reference ground voltage, the fourth switch is controlled by the switch control signal to be turned on or off, wherein the fourth switch The three switches are opposite to the on and off actions of the fourth switch, and the third switch is opposite to the on and off actions of the first switch. The intra-wafer oscillating device of claim 11, wherein a capacitance value of at least one of the first variable capacitor and the second variable capacitor is changed according to the selected data. The intra-wafer oscillating device according to claim 9, wherein the output signal generating circuit supplies the oscillating output signal as the switch control signal. The intra-wafer oscillating device of claim 5, wherein the output signal generating circuit comprises: a first comparator, an input terminal receives the preset voltage, and another input terminal receives the first charging voltage a second comparator having an input receiving the preset voltage and another input receiving the second charging voltage; and an SR latch having a set end, a reset end, and an output end, the set end The output end of the SR latch is coupled to the output of the second comparator, and the output of the SR latch generates the oscillating output signal. The intra-wafer oscillating device of claim 1, wherein the reservoir is a non-volatile memory.