TWI480881B - One-time programmable memory, electronics system, and method for providing one-time programmable memory - Google Patents

Description

Single-shot programmable memory, electronic system, and method for providing single-time programmable memory

The present invention relates to a programmable memory element, particularly a programmable resistive element of a memory array.

A programmable resistive element generally means that the resistive state of the component can be changed after programming. The resistance state can be determined by the resistance value. For example, the resistive element can be a One-Time Programmable (OTP) component (such as an electrical fuse), and the programming method can apply a high voltage to generate a high current through the OTP component. When a high current flows through the OTP component by turning the programming selector on, the OTP component will be programmed to be fired in a high or low resistance state (depending on whether it is a fuse or an antifuse).

Electrical fuses are a common type of OTP, and such programmable resistive elements can be polycrystalline germanium, germanium polysilicon, germanium, thermally isolated active regions, metals, metal alloys, or combinations thereof. The metal can be aluminum, copper or other transition metal. The most commonly used electrical fuse is a deuterated polysilicon, made of a gate of a complementary MOS transistor (CMOS), used as an interconnect. Electrical fuses can also be one or more contacts or vias instead of small segments. Internal connection. High current can burn contacts or layers indirectly to a high resistance state. The electrical fuse can be an anti-fuse, where a high voltage reduces the resistance rather than increasing the resistance. The antifuse may be composed of one or more contacts or layer indirect points and has an insulator therebetween. The antifuse can also be coupled to the CMOS body by a CMOS gate that contains a gate oxide layer as an insulator.

A conventional programmable resistive memory storage unit is shown in FIG. The memory cell 10 includes a resistive element 11 and an N-type MOS transistor (NMOS) programming selector 12. The resistive element 11 is coupled at one end to the drain of the NMOS and at the other end to a positive voltage V+. The gate of NMOS 12 is coupled to select signal SEL and the source is coupled to a negative voltage V-. When a high voltage is applied to V+ and a low voltage is applied to V-, the resistive element 10 can be programmed to turn on the NMOS 12 by raising the program select signal SEL. One of the most common resistive components is deuterated polysilicon, which is the same material used in the fabrication of MOS gates at the same time. The area of the NMOS programming selector 12 needs to be large enough to allow the required programming current to last for a few microseconds. The programming current for deuterated polysilicon is typically from a few milliamps (for a fuse of about 40 nanometers in width) to 20 milliamps (for a fuse of about 0.6 micrometers in width). Therefore, an electrical fuse storage unit using a deuterated polysilicon tends to have a large area.

As shown in Figure 2a, phase change memory (PCM) is another conventional programmable resistive element 20. The PCM memory cell includes a phase change material film 21 and a bipolar transistor 22 as a program selector having a P+ emitter 23, the N-type base 27 and the P-type substrate being the collector 25. The phase change film 21 is coupled at one end to the emitter 23 of the bipolar transistor 22 and at the other end to a positive voltage V+. The N-type base 27 of the bipolar transistor 22 is coupled to a negative voltage V-. The collector 25 is coupled to ground. Applying a voltage between V+ and V- for a suitable and continuous period of time, the phase change film 21 can be programmed to a high or low resistance state, depending on the voltage and duration. By convention, programming a phase change The memory is in a high-resistance state (or reset state) requiring approximately 3 volts of continuous voltage of 50 ns, consuming approximately 300 uA of current. Programming the phase change memory into a low-resistance state (or set state) requires a 2V voltage of approximately 300ns and consumes approximately 100uA of current. This type of memory cell requires a special process to properly isolate each memory cell, thus requiring 3-4 more masks than standard CMOS logic processes, making it more expensive to make.

Figure 2b shows a programmable resistive element of another phase change memory (PCM). The phase change memory material has a phase change film 21' and a diode 22'. The phase change film 21' is coupled between the diode anode 22' and the positive voltage V+. The cathode 22' of the diode is coupled to a negative voltage V-. Applying the appropriate voltage between V+ and V- for an appropriate period of time, the phase change film 21' can be programmed to a high or low resistance state, depending on voltage and duration. See "Kwang-Jin Lee et al., "A 90nm 1.8V 512Mb Diode-Switch PRAM with 266MB/s Read Throughput," International Solid-State Circuit Conference, 2007, pp. 472-273", Figure 2b shows An example of a programming selector using a diode as a phase change memory (PCM) memory cell. Although this technology can reduce the size of PCM memory cells to only 6.8F2 (F stands for feature size), diodes require very complex manufacturing processes such as Selective Epitaxial Growth (SEG). As a result, the application of embedded PCM will become very expensive.

Figures 3a and 3b show some embodiments of electrical fuse elements 81 and 85 fabricated from interconnects. The inner connection acts as a specific type of resistive element. The resistive element has three parts: the anode, the cathode, and the body. The anode and cathode provide circuitry for the connection of the resistive element to other portions such that current can flow from the anode through the body to the cathode. The width of the body determines the current density, which in turn determines the electromigration threshold for the programming current. Figure 3a shows a conventional electrical fuse element 81 comprising an anode 80 , cathode 82, and body 83. This embodiment has a large and symmetrical anode and cathode. Figure 3b shows another conventional electrical fuse element 85 comprising an anode 84, a cathode 86, and a body 87. This embodiment has an asymmetrical shape of large anodes and small cathodes to increase electromigration effects based on polarity and storage effects. The polarity effect means that electromigration always starts from the cathode. The effect of the storage effect is that small cathodes can make electromigration easier to occur. Because when electromigration occurs, the smaller area can have fewer ions to replenish the void. The fuse elements 81 and 85 in Figures 3a and 3b are relatively large structures which make them unsuitable for some applications.

It is an object of the present invention to provide a programmable resistive element memory cell that uses a diode as a program selector, wherein the programmable resistive element can be fabricated using standard CMOS logic processes to reduce the size and cost of the memory cell.

In accordance with another embodiment of the present invention, a single-shot programmable memory includes: a plurality of single-shot programmable memory cells, at least one single-shot programmable memory cell including: a single-shot programmable component coupled to a first power voltage line; and a diode includes at least a first active region and a second active region, wherein the first active region has a first type of doping, and the second active region has a second type of doping The first active region provides a first end of the diode and the second active region provides a second end of the diode, and both the first active region and the second active region are present In a common well, the first active region is coupled to a single-shot programmable component, and the second active region is coupled to a second supply voltage line; wherein the first and second active regions are from a complementary gold A source or a drain of an oxy-semiconductor transistor (CMOS) device is fabricated, and a well is fabricated from a CMOS well. Wherein the single-shot programmable element is configured to be programmable, changing the resistance to a different logic by applying a voltage to the first and second supply voltage lines A state in which the single-time programmable element is composed of an electrical fuse.

In accordance with another embodiment of the present invention, an electronic system includes: a processor; and a single-shot programmable memory operatively coupled to the processor, the single-shot programmable memory including at least a plurality of singularities a programmable memory cell to provide data storage, each of the one-time programmable memory cells comprising: a single-shot programmable component coupled to the first supply voltage line; and a diode comprising at least one first active region and one The second active region is isolated from the first active region, wherein the first active region has a first type of doping, the second active region has a second type of doping, and the first active region provides a first end of the diode The second active region provides a second end of the diode, and both the first and second active regions are in a common well, the first active region being coupled to the single-shot programmable component The second active region is coupled to a second supply voltage line; wherein the first and second active regions are fabricated from a source or drain of a CMOS device, and the well is fabricated from a CMOS well; wherein Single-shot programmable components are configured to be editable , Via application of a voltage to the first and second power supply voltage line and a single programmable element changes to a different logic state; wherein the single element is composed of an electrically programmable fuse.

In accordance with another embodiment of the present invention, a method of providing a one-time programmable memory, comprising: providing a plurality of single-shot programmable memory cells, at least one single-shot programmable memory cell comprising at least (i) a single pass The programmable element is coupled to the first supply voltage line; and (ii) a diode includes at least a first active region and a second active region, the first active region having a first type of doping, the second The active region has a second type of doping, the first active region provides a first end of the diode, and the second active region provides a second end of the diode, both the first and second active regions Manufactured from the source or drain of a CMOS component, and there is a common well that is from CMOS Manufactured from the well, the first active region is coupled to the single-shot programmable resistance element and the second active region is coupled to a second supply voltage line, and via applying a voltage to the first and second voltages a line to program a logic state to at least one of the one-time programmable memory cells; wherein the single-shot programmable component is comprised of an electrical fuse.

The programmable resistive element memory of the present invention can reduce programming current and can use standard CMOS logic processes to reduce the size and cost of the memory cells.

[知知]

10‧‧‧ storage unit

11‧‧‧Resistive components

12‧‧‧ NMOS programming selector

20,20'‧‧‧Programmable Resistive Components

21,21'‧‧‧ phase change film

22‧‧‧Bipolar transistor

23‧‧‧P+ emitter

27‧‧‧N type base

25‧‧‧

22'‧‧‧ Diode

81,85‧‧‧Electrical fuse components

80,84‧‧‧Anode

82,86‧‧‧ cathode

83,87‧‧‧Ontology

[this invention]

30‧‧‧storage unit

30a‧‧‧resistive components

30b‧‧‧ diode

32,32’,32”‧‧‧dipole

33,33’,33”‧‧‧P+ active zone

34,34’,34”‧‧‧N Well

37,37’,37”‧‧N+ active zone

36,36’‧‧‧Shallow trench isolation

31', 31" ‧ ‧ active area

39’‧‧‧ gate

39"‧‧‧ Telluride barrier

35,35’,35”‧‧‧ base

45‧‧‧Connected diode

31-1, 31-2, 31-3‧‧‧ islands

39-1, 39-2, 39-3‧‧‧ MOS gate

4040-1 and 4040-2

33-1, 2, 3, ‧‧‧P+ active zone

37-1, 2, 3‧‧‧N+ active zone

38'‧‧‧P+ implant layer

88‧‧‧Electrical fuse element

89‧‧‧Anode

90‧‧‧ cathode

91‧‧‧Ontology

92‧‧‧P+ implant layer

40, 50, 60, 60', 70, 60", 60" ‧ ‧ ‧ diode

43,44,,51,73,74,64’‧‧‧active area

49,59,79‧‧‧STI

42,52,62’‧‧‧Fuse components

46,76‧‧‧Metal

47,67’,77,67‧‧‧P+ implant layer

45,55,75,65’‧‧‧N well

54,64,64’‧‧‧around active area

53,63,63’‧‧‧Central Active Area

58‧‧‧False MOS gate

68‧‧‧ring MOS gate

68'‧‧‧ ring-shaped telluride barrier

71‧‧‧ single contact

69‧‧‧First layer of metal fuse

62'‧‧‧Anode

66'‧‧‧First metal body

70‧‧‧First indirect point (via1) fuse storage unit

73a, 73b‧‧‧N type well contact (active area)

79‧‧‧Via1 fuse storage unit

79a‧‧‧via1

76‧‧‧First metal

72‧‧‧Second metal

74‧‧‧active area

77‧‧‧P+ implant layer

78‧‧‧STI

75‧‧‧N Well

90‧‧‧Two-dimensional array

91‧‧‧active area

96‧‧‧ layer indirect point fuse storage unit

92‧‧‧False CMOS Gate

99‧‧‧Contacts

97‧‧‧N+ implant layer

94‧‧‧P+ implant layer

100‧‧‧Programmable Resistor Memory

101‧‧‧Array

110‧‧‧ memory storage unit

111‧‧‧Resistive components

112‧‧‧ diode

150-i‧‧‧ character line driver

170-j‧‧‧ bit line BLj

LWLBi‧‧‧local word line

S700-S760, S800-S870‧‧‧ steps

700‧‧‧Processor System

740‧‧‧ memory

744‧‧‧Programmable resistance element

742‧‧‧Memory Cell Array

710‧‧‧Central Processing Unit

715‧‧‧Common bus

720‧‧‧Input and output unit

730‧‧‧ Hard disk drive

750‧‧‧DVD

740‧‧‧ memory

760‧‧‧Other memory

Figure 1 shows a circuit diagram of a conventional programmable resistive memory storage unit.

Figure 2a shows a circuit diagram of another conventional programmable resistive element for phase change memory (PCM) that uses a bipolar transistor as a programming selector.

Figure 2b shows a conventional phase change memory (PCM) circuit diagram using a diode as a programming selector.

3a and 3b show schematic views of an embodiment of an electrical fuse element fabricated from an interconnect, respectively.

Figure 4 shows a block diagram comprising a memory storage unit using junction diodes in accordance with the present invention.

Figure 5a shows a cross section of a junction diode. According to this embodiment, the diode is isolated from the anode and cathode by shallow trench isolation (STI) and when the selector is programmed.

Figure 5b shows a cross section of a junction diode. According to this embodiment, the diode isolates the anode and cathode with a dummy CMOS gate and when the selector is programmed. Figure 5c shows a cross section of a junction diode. According to this embodiment, the diode is separated from the anode and cathode by a deuteration barrier (SBL) and when the selector is programmed.

Figure 6a shows a cross section of a junction diode. According to this embodiment, the diode is isolated from the anode and cathode by a dummy CMOS gate in an insulating germanium (SOI) technique and when the selector is programmed.

Figure 6b shows a cross section of a junction diode. According to this embodiment, the diode is insulated with a dummy CMOS gate in a fin field effect transistor (FINFET) technique to isolate the anode and cathode, and when programming the selector.

Figure 7a shows a schematic diagram of an embodiment of an electrical fuse element.

Figure 7b shows a top view of an electrical fuse. The electrical fuse is coupled to a junction diode that is shallow trench isolation (STI) on all four sides.

Figure 7c shows a top view of an electrical fuse. The electrical fuse is coupled to a two-sided shallow trench isolation (STI) and the other two sides are dummy CMOS isolated junction diodes.

Figure 7d shows a top view of an electrical fuse. The electrical fuse is coupled to a junction diode that is all four sides are pseudo CMOS isolated.

Figure 7e shows a top view of an electrical fuse. The electrical fuse is coupled to a junction diode that is isolated on all four sides by a germanide barrier.

Figure 7f shows a contact coupled to the P-terminal junction of the resistive element and the junction diode, with the metal filled in the same single contact.

Figure 8a shows a top view of a metal fuse coupled to a junction diode. This junction diode is surrounded by dummy CMOS gates.

Figure 8b shows a top view of a metal fuse coupled to a junction diode. The junction diode has four memory cells sharing one N-well contact.

Figure 8c shows a top view of a layer of via fuse coupled to a junction diode. The junction diode has four memory cells sharing one N-well contact.

Figure 8d shows a top view of a two-dimensional array of indirect point fuses. These layer indirect fuses use P+/N well diodes.

Figure 9 shows a portion of a programmable resistive memory. According to this embodiment, a single diode memory cell of n rows and (m+1) columns is constructed with n word line drivers.

Figure 10a depicts a flow diagram of a method for programming a programmable resistive memory.

Figure 10b depicts a flow diagram of a method for reading a programmable resistive memory.

Figure 11 shows a schematic diagram of an embodiment of a system of processors.

In an embodiment of the invention, the P+/N well junction diode system acts as a programming selector for the programmable resistive component. This diode can include P+ and N+ active regions in the N well. Since the P+ and N+ active regions and the N-well are both off-the-shelf standard CMOS logic processes, these components can be fabricated in an efficient and cost-effective manner without the need for additional masks or process steps to save cost. This programmable resistive element can be included in an electronic system.

4 is a block diagram of a memory storage unit 30 using junction diodes in accordance with an embodiment. In particular, the memory unit 30 includes a resistive element 30a and a diode 30b. The resistive element 30a can be coupled between the anode of the junction diode 30b and a positive voltage V+. The cathode of junction diode 30b can be coupled to a negative voltage V-. In an embodiment, the memory storage unit 30 may be a fuse storage unit and include a resistance element as an electrical fuse. Piece 30a. Junction diode 30b can be used as a programming selector. The junction diode can be fabricated from a standard CMOS process P+/N well using a P-type substrate. The P+ and N+ active regions as the diode anode and cathode are the source or drain of the CMOS component. Well N is a CMOS well used to embed PMOS components. Alternatively, the junction diode can be constructed from an N+/P well in a CMOS process using an N-type substrate. The connection between the resistive element 30a and the junction diode 30b between the supply voltages V+ and V- is interchangeable. By applying an appropriate voltage (between V+ and V-) over a suitable time, the resistive element 30a can be programmed to a high or low resistance state depending on the voltage and duration, so the programmed memory storage unit 30 can store the data value. (for example, the bit of data). The P+ and N+ active regions of the diode can be isolated using a dummy CMOS gate, shallow trench isolation (STI), local oxidation (LOCOS), or a germanide barrier layer (SBL). If no germanide is near the boundary of the first and second active regions, the first and second active regions may be butted or doped with a low dose active region to separate the active regions.

The storage unit of the electrical fuse can be used as an example to illustrate the key implementation concepts. Figure 5a shows a cross section of a diode 32 in which a shallow trench isolated P+/N well diode is used as a programming selector in a programmable resistive element. The P+ active region 33 and the N+ active region 37, which respectively constitute the P and N terminals of the diode 32, are the source or drain of the PMOS and NMOS in a standard CMOS logic process. The N+ active region 37 is coupled to an N-well 34 that embeds a PMOS in a standard CMOS logic process. Shallow trench isolation 36 isolates the active regions of the different components. A resistive element (not shown in Figure 5a), such as an electrical fuse, can be coupled to the P+ active region 33 at one end and to the high voltage power supply V+ at the other end. To program such a programmable resistive component, a high voltage is applied to V+, a low voltage or ground potential is applied to the N+ active region 37. Therefore, a high current is passed through the fuse element and the diode 32 to program the resistive element.

Figure 5b shows a cross-sectional view of another junction diode 32' embodiment as programming The selector is isolated with a dummy CMOS gate. Shallow trench isolation 36' provides isolation of other active regions. The active region 31' is defined by a shallow trench isolation 36'. Here, the N+ and P+ active regions 37' and 33' are further defined by a mixture of a dummy CMOS gate 39', a P+ implant layer 38', and an N+ implant layer (complementary to the P+ implant layer 38'), respectively. N and P ends of the polar body 32'. The diode 32' is fabricated as a PMOS-like component and includes 37', 39', 33', and 34' as source, gate, drain, and N wells, except that the source 37' is covered with N+ The implant layer, rather than the P+ implant layer 38' covered by a true PMOS. The dummy MOS gate 39' is preferably biased at a fixed voltage for the purpose of isolation between the P+ active region 33' and the N+ active region 37' during fabrication. The N+ active region 37' is coupled to the N-well 34', which is a body embedded in the PMOS in a standard CMOS logic process. The P substrate 35' is a matrix of P-type germanium. A resistive element (not shown in Figure 5b), such as an electrical fuse, can be coupled to P+ region 33' at one end and to a high voltage supply V+ at the other end. To program such a programmable resistive element, a high voltage is applied to V+ and a low voltage or ground is applied to the N+ active region 37'. Therefore, a high current flows through the fuse element and the diode 32' to program the resistance element. This embodiment has an ideal small size and low resistance.

A cross-section of another embodiment, shown in Figure 5c, in which the junction diode 32" is isolated by a telluride barrier (SBL) 39" and serves as a programming selector. Figure 5c is similar to Figure 5b, however the dummy CMOS gate 39' in Figure 5b is replaced by a telluride blocking layer 39" in Figure 5c to prevent the growth of germanide on top of the active region 31". If there is no dummy CMOS gate or germanium blocking layer, the N+ and P+ active regions will be shorted by the germanium on the surface of the active region 31.

Figure 6a shows a cross section of another embodiment in which the junction diode 32" is used as a programming selector and employs a technique of insulating germanium (SOI). In SOI technology, the substrate The 35" is an insulator such as cerium oxide or the like, which contains a thin layer of germanium grown on top. All NMOS and PMOS are in the well, separated from each other and the substrate 35" by cerium oxide or the like. A one-piece active region 31" is divided into N+ active regions 37" by a mixture of a dummy CMOS gate 39', a P+ implant layer 38", and a complement of the N+ implant layer (P+ implant layer 38). , P + active area 33" and body 34". Therefore, the N+ active region 37" and the P+ active region 33" respectively constitute the N terminal and the P terminal of the junction diode 32". The N+ active region 37" and the P+ active region 33" can respectively be combined with the NMOS and PMOS in the standard CMOS logic process. The source or drain is the same. Similarly, the dummy CMOS gate 39' can be the same as the CMOS gate constructed in a standard CMOS process. The dummy MOS gate 39' can be biased at a fixed voltage for the purpose of fabrication. As the isolation between the P+ active region 33" and the N+ active region 37", the N+ active region 37" is coupled to the low voltage V- and N wells 34, which are embedded in the PMOS body in a standard CMOS logic process. A resistive element (not shown in Figure 6a), such as an electrical fuse, can be coupled to the P+ active region 33" at one end and to the high voltage supply V+ at the other end. To program such an electrical fuse storage unit, Gaohe The low voltage is applied to V+ and V-, respectively, and a large current is passed through the fuse element and the junction diode 32" to program the resistance element. Other embodiments of CMOS isolation techniques, such as shallow trench isolation (STI), dummy CMOS gates, or germanium blocking layers (SBL) on one to four sides or on either side, can be readily applied to corresponding CMOS SOI technologies.

Figure 6b shows a cross-sectional view of another embodiment of a junction diode 45 that is a programming selector using a fin field effect transistor (FinFET) technology. FinFET is a basic multi-gate transistor with a fin (FIN). The FinFET technology is similar to conventional CMOS, but has a high thin island that is raised on the germanium substrate to serve as the body of the CMOS component. The main body is like a traditional CMOS, divided into source, bungee and polysilicon or non-aluminum metal gates. Extreme passage. The main difference is that in FinFET technology, the body of the MOS device is lifted onto the substrate. The height of the island is the width of the channel, but the direction of current flow is still parallel to the surface of the crucible. Figure 6b shows an example of a FinFET technique in which the germanium substrate 35 is an epitaxial layer built on top of an SOI insulating layer or other high resistance germanium substrate. The ruthenium substrate 35 can be etched into several tall rectangular island regions 31-1, 31-2, and 31-3. The island regions 31-1, 31-2, and 31-3 can cover both sides of the raised island region with MOS gates 39-1, 39-2, and 39-3, respectively, through the growth of the appropriate gate oxide layer. And define the source and drain regions. The source and drain regions are formed in island regions 31-1, 31-2, and 31-3, and then filled with germanium, such as filled in germanium 40-1 and germanium 40-2, allowing the combined source and drain The area is large enough to put down the joint. In Fig. 6b, the filling regions of the crotch region 40-1 and the crotch region 40-2 are only used to illustrate and reveal the cross section, for example, the filling region may be filled to the surfaces of the island regions 31-1, 31-2 and 31-3. . In this embodiment, the active regions 33-1, 2, 3 and 37-1, 2, 3 are respectively covered by the P+ implant layer 38' and the N+ implant layer (the complement of the P+ implant layer 38') to form the junction. The P and N terminals of diode 45, rather than the PMOS like a conventional FinFET, are all covered by P+ implant layer 38'. The N+ active regions 37-1, 2, 3 are coupled to a low voltage power supply V-. Resistive elements (not shown in Figure 6b), such as electrical fuses, are coupled at one end to P+ active regions 33-1, 2, 3 and at the other end to a high voltage supply V+. To program such an electrical fuse, high and low voltages are applied across V+ and V-, respectively, to conduct a large current through the resistive element and junction diode 45 to program the resistive element. Other embodiments of CMOS body technology isolation, such as shallow trench isolation (STI), dummy CMOS gate or germanium blocking layer (SBL), can be readily applied to the corresponding FinFET technology.

Figure 7a is a top view of an electrical fuse element 88 in accordance with another embodiment. This electrical fuse element 88 can be used as a resistive element as shown in FIG. Electrical fuse element 88 package The anode 89, the cathode 90 and the body 91 are included. In this embodiment, the electrical fuse element 88 is rod shaped and includes a large anode 89 and a small cathode 90 to reduce the cathode area. The anode 89 and the cathode 90 may protrude from the body 91 to form a joint. The number of contacts of the anode 89 and the cathode 90 may be one to make the area very small. However, the anode 89 junction area tends to be larger, such that the anode 89 is larger than the cathode 90, allowing the anode 89 to be more resistant to electromigration. The body 91 of the fuse may have a width of 0.5-6 squares, that is, a ratio of length to width of about 6 to 0.5 to optimize the memory cell area and programming current. The fuse element 88 has a P+ implant layer 92 covering a portion of the body 91 and the cathode 90, while the N+ implant layer covers the remaining area. This embodiment causes the fuse element 88 to behave like a reverse biased diode to increase the post-programmable resistance when the top telluride is depleted by other effects such as electromigration, ion diffusion, and hydrazine decomposition. In order to make the memory cell smaller and reduce the resistance of the overall conduction path, the contact point of the programmable resistance element or diode can be no more than two in one memory cell. Similarly, the contact area of the programmable resistive element or diode can be larger than the contacts outside the memory array.

The electrical fuse element that can implement the above embodiments includes polysilicon, polysilicon, thermally isolated active regions, local interconnects, or other CMOS gate materials. In particular, some electrical fuse components allow P+ and N+ implants to create diodes after programming, such as polysilicon, thermally isolated active regions, or gated CMOS gates. For example, if the metal gate CMOS has a sandwich structure of polysilicon between the metal alloy layers, the metal alloy layer can be blocked by a mask created by the layout to create a diode in the fuse element. In SOI or processes such as SOI, electrical fuses can also be constructed from thermally isolated active regions. At both ends of the thermally isolated active region, such fuses can be implanted with N+, P+, or N+ and P+ doping. If a portion of the fuse is implanted with N+ doping and a portion of P+ doping, the fuse can be shaped when the top germanide is programmed to be depleted. Imaging a reverse biased diode. In the fuse element constructed in this way, the fuses can be combined into a part of the active region of the diode, so that the fuse and the diode are formed in a single active area to save area. There are processes that provide local interconnects that can be directly interconnected with the active region by the by-products of the telluride manufacturing process to save points. In this way, the electrical fuse element can be directly connected to the active area of the diode without any contacts to save area. There are many variations in the construction of electrical fuse elements in the CMOS process. The above discussion is for illustrative purposes, and variations and combinations thereof are part of the embodiments and fall within the scope of the invention.

Figures 7b, 7c, 7d, 7e and 7f show top views of P+/N well diodes from embodiments of different isolation and fuse elements. Without isolation, the P+ and N+ active regions will be shorted together via the telluride grown at the top. The isolation may be provided via a shallow trench isolation (STI), a dummy CMOS gate, or a telluride blocking layer (SBL) from one to four sides or a combination of any of the sides. The P+ and N+ active regions, which are the P and N terminals of the diode, are the source or drain of the CMOS device. The N well where P+ and N+ are located is used to embed the same N well of the PMOS in a standard CMOS process. The N+ active regions of the diodes can be shared in many memory cells. However, for simplicity, Figures 7b-7f show only one N+ active zone for a P+ active zone.

Figure 7b shows a top view of another embodiment of a P+/N well diode 40 in an electrical fuse storage unit. The electrical fuse storage unit has active regions 43 and 44 and has an STI 49 isolated from four sides. Fuse element 42 is coupled to active region 43 via metal 46. The active regions 43 and 44 are covered by a P+ implant layer 47 and an N+ implant layer (complementary to the P+ implant layer 47), respectively, to form the P terminal and the N terminal of the diode 40. The active regions 43 and 44 of the diode 40 are present in an N-well 45, and the same N-well can be used to embed the PMOS in a standard CMOS process. In this embodiment, the P+ active region 43 and the N+ active region 44 are surrounded by STI 49. . Since the STI 49 is deeper than the P+ and N+ active regions, the diode resistance between the P+ active region 43 and the N+ active region 44 can be high.

Figure 7c shows a top view of another embodiment of a P+/N well diode 50 in an electrical fuse storage unit. The electrical fuse storage unit has active sides 53 and 54 separated by two sides STI 49 and the other two sides of the dummy CMOS gate. The electrical fuse unit includes an active region 51 of two STI 59 trenches on the right and left, and is divided into a peripheral active region 54 and a central active region 53 via two CMOS gates at the top and bottom. The central active region 53 is covered by a P+ implant layer 57, while the peripheral active region is covered by an N+ implant layer, which constitutes the P terminal and the N terminal of the diode. The active area 51 has an N-well of 55, and the same N-well can be used to embed PMOS in a standard CMOS process. Fuse element 52 is coupled to P+ active region 53. The dummy MOS gate 58 is preferably biased to a fixed voltage. In this embodiment, the P+ active region 53 and the N+ active region 54 are surrounded by the STI 59 on the left and right sides and the dummy MOS gate 58 is at the top and bottom. Isolation of the isolation ratio STI provided by the dummy MOS gate 58 provides lower resistance because the distance between the P+ active region 53 and the N+ active region 54 is narrower and there is no oxide blocking current path under the surface of the germanium.

Figure 7d shows a top view of another embodiment of a P+/N well diode 60 in an electrical fuse storage unit. This electrical fuse storage unit has a dummy CMOS gate isolated on all four sides. The single active region is divided into a central active region 63 and a peripheral active region 64 by a ring MOS gate 68. Separately, the central active region 63 is covered by the P+ implant layer 67, while the peripheral active region 64 is covered by the N+ implant layer (complementary to the P+ implant layer 67) to form the P and N ends of the diode 60. . The active area 61 is present in an N well, and the same N well can be used to embed PMOS in a standard CMOS process. Fuse element 62 is coupled to P+ active region 63 via metal 66. The dummy MOS gate 68 can be biased to a fixed voltage to provide four-sided isolation between the P+ active region 63 and the N+ active region 64. This embodiment provides a low resistance to the P of the diode 60. Between the N and the N.

Figure 7e shows a top view of a P+/N well diode 60', another embodiment in an electrical fuse storage unit. The electrical fuse memory cell has active regions 63' and 64' that are provided with four sides isolation with a telluride blocking layer (SBL) 68'. The single piece active region is divided into a central active region 63' and a peripheral active region 64' by a ring-shaped telluride barrier layer (SBL) 68'. The central active region 63' and the peripheral active region 64' are respectively covered by the P+ implant layer 67' and the N+ implant layer (complementary to the P+ implant layer 67') to form the P terminal and the N of the diode 60'. end. The boundary between the P+ implant layer 67' and the N+ implant layer is approximately in the middle of the ring-shaped telluride barrier layer (SBL) 68'. The active zone 61' exists in an N-well 65'. Fuse element 62' is coupled to P+ active region 63' via metal 66'. A ring-shaped telluride barrier (SBL) 68' barrier telluride is formed on top of the P+ active region 63' and the N+ active region 64'. In this embodiment, the P+ active region 63' and the N+ active region 64' are isolated by four sides of the P/N junction. This embodiment has a low resistance between the P and N terminals of the diode 60', although the telluride blocking layer (SBL) may be wider than the MOS gate. In another embodiment, a void exists between the P+ implant layer 67' and the N+ implant layer, although both the P+ implant layer 67' and the N+ implant layer are surrounded by a ring-shaped germanide blocking layer (SBL) 68'. Covered.

Figure 7f shows a top view of another embodiment in which the P+/N well diode 70 contains a single contact in an electrical fuse storage unit. The active regions 73 and 74 separated by the STI 79 are covered by the P+ implant layer 77 and the N+ implant layer (complementary to the P+ implant layer 77), respectively, forming the P terminal and the N terminal of the diode 70. Both active regions 73 and 74 have an N-well 75, and the same N-well can be used to embed PMOS in a standard CMOS process. Fuse element 72 is coupled to P+ active region 73 via metal 76 in a single contact 71. This single contact 71 is completely different from the double contacts in Figures 7b, 7c, 7d and 7e, where one contact connects the fuse element via metal and then the other contact connects another P+ active area via metal . this In an embodiment, a fuse element is directly connected to a P+ active region via a metal in a single contact, and the area of the memory cell can be greatly reduced. Embodiments of this fuse element can be constructed from CMOS gates, including polysilicon, deuterated polysilicon or non-aluminum metal CMOS gates that allow the fuse element and active region to pass through a single point of contact on the metal.

In general, polysilicon or germanium polysilicon fuses are more commonly used as electrical fuses because they require lower programming current than metal, or contact/layer indirect points. However, metal fuses have certain advantages, such as smaller size and large resistance ratio after programming. The use of metal fuse elements can be directly connected to the P+ active region, thereby reducing the number of additional contacts compared to polysilicon fuses. In advanced CMOS technology with feature sizes less than 65 nanometers, the metal fuse can be programmed at voltages below 3.3V, making metal fuses a viable solution.

Figure 8a shows a top view of the P+/N well diode 60" with the first metal (metal1) fuse with a dummy CMOS gate isolation. The single active region is isolated by the ring MOS gate 68 to be centrally active. Region 63 and peripheral active region 64. Separately, central active region 63 is covered by P+ implant layer 67, and peripheral active region 64 is covered by N+ implant layer (complementary to P+ implant layer 67) to form a pole The P end and the N end of the body 60". The active area 61 is present in an N well, and the same N well can be used to embed a PMOS in a standard CMOS process. The first layer of metal fuse element 62" is directly coupled to P+ region 63. Ring MOS gate 68 provides dummy CMOS gate isolation, can be biased to a fixed voltage, and can provide P+ active region 63 and N+ active The isolation between the four sides of the region 64. In this embodiment, the metal fuse has an aspect ratio of about 0.5-6.

If the diode conduction current is not large, the size of the metal fuse in Figure 8a can be further reduced. Figure 8b shows a top view of a row of metal fuse storage units 60'". In this embodiment, there are four metal fuse storage units sharing an N-well contact on each side. The first layer of metal fuse 69 has an anode 62', a first layer of metal body 66' and a cathode (coupled to active region 64'), and active region 64' is covered by P+ implant layer 67' and acts as a diode P end. The active zone 61' exists in an N-well 65'. The other active region 63' is covered by the N+ implant layer (complementary to the P+ implant layer 67') to serve as the N-terminal of the diode. The four diodes are isolated by the STI 68' and share an N+ active zone 63' on each side. The N+ active region 63' is connected by a horizontal second metal layer (metal2), and the diode anode is connected by a vertical third metal layer (metal3). If the first layer of metal is used for programming, the other types of metal lines in the conduction path should be wider. Similarly, more contacts and layer indirect points should be placed in the conduction path to resist improper programming. The use of the first layer of metal in the metal fuse of Figure 8b is for illustrative purposes only, and it will be apparent to those skilled in the art that the above description can be applied to any metal, such as a second, third, or four layer metal, or in other embodiments. Also, it will be apparent to those skilled in the art that the present invention is applicable to different isolated or different metal structures. Moreover, the number of memory cells sharing an N+ active zone may vary in other embodiments.

For advanced CMOS technologies with feature sizes less than 65 nanometers, contact or layer indirect (Via) fuses become a more viable technique because the small contact/layer indirect points make the programming current relatively low. Figure 8c shows a top view of a row of four first indirect point (via1) fuse storage units 70, which in accordance with this embodiment share N-well contacts 73a and 73b. The Via1 fuse storage unit 79 has a via 179a coupled to the first layer of metal 76 and the second layer of metal 72. The second layer of metal 72 is coupled via via2 to the third layer of metal in the vertical direction as the bit line. The first layer of metal 76 is coupled to an active region 74 that is covered by the P+ implant layer 77 and is considered to be the P terminal of a diode 71. The active regions 73a and 73b are covered by the N+ implant layer (complementary to the P+ implant layer 77) and are considered to be the N-terminal of the diode 71 in the via1 fuse storage unit 79. In addition, the active area 73a and 73b is considered to be the common N-terminal of the diodes in the four fuse storage units 70, coupled to the word line of the fourth metal (metal4) in the horizontal direction. The active zones 74, 73a and 73b are located in the same N well 75. The four diodes in the Via1 fuse storage unit 70 are STI 78 isolated from each other. If you want to program via1, more other contacts and more other types of layer indirect points should be placed in the conduction path. And the other metal lines in the conduction path should be relatively wide and contain large surrounds around the junction/layer indirect points to resist improper programming. In Fig. 8c, the use of Via1 as a layer indirect fuse is for illustrative purposes, and it is well known to those skilled in the art that the above description can be applied to any type of contact or layer indirect point, such as second, third, fourth or fourth. Inter-layer connection points via2, via3 or via4. Similarly, it is known to those skilled in the art that the P and N ends of the diode of the present invention have different isolation and different metal structures. Moreover, the number of memory cells sharing an N+ active zone may change in other embodiments.

Figure 8d shows a top view of another embodiment showing a 4x5via1 fuse array with dummy CMOS gate isolation. Figure 8c shows a row of indirect point fuses that can be expanded into a two dimensional array 90 (as shown in Figure 8d). Array 90 has four columns of active regions 91, each column having a separate N-well, and five-layer indirect-point fuse storage unit 96 being isolated from the active interval by dummy CMOS gate 92. Each layer of the via fuse memory unit 96 has a contact 99 over the active area covered by the P+ implant layer 94 to serve as the P terminal of a diode, which is further coupled to the vertical direction. Two-layer metal bit line. The active regions on both sides of array 90 are covered by N+ implant layer 97 as the N-side of the same column of diodes, which is further coupled to the third layer of metal as a word line in the horizontal direction. In order to program an indirect point fuse, a voltage can be selected and applied to the desired word line and bit line to conduct current from the metal2 bit line, via1, metal1, contact, P+ active region and N+ active region, to Three-layer metal word line. To ensure that only via1 is programmed, other metals It can be wider and the number of other types of layer indirect points or other contacts can be more than one. In order to simplify the drawing, the metal1-via1-metal2 connection can be referred to FIG. 8c, and thus will not be shown in each of the memory cells in the 8d figure. It will be appreciated by those skilled in the art that different types of contacts or layer indirect points can be used as the resistive elements of the present invention, and the structure of the different metals can be varied in other embodiments. Similarly, the number of memory cells in rows and columns, the number of rows and columns in an array, or the number of memory cells between N+ active regions can vary in other embodiments.

According to another embodiment, a programmable resistive element can be used to create a memory. In accordance with this embodiment, FIG. 9 shows a portion of a programmable resistive memory 100 having an array 101 of single-diode memory cells 110 of n rows x (m+1) columns and n word line drivers 150- i (where i = 0, 1, ..., n-1) is constructed. The memory array 101 has m normal columns and a reference column, and shares a sense amplifier for differential sensing. For each memory storage unit 110 of the memory storage unit 110 in the same column, a resistive element 111 is coupled to the P terminal of a diode 112 of the programming selector and to a bit line BLj 170-j (j =0, 1, ..m-1) or reference bit line BLR0 175-0. For those memory cells 110, the N-terminal of the diode 112 in the same row is coupled to a word line WLBi 152 via a local word line LWLBi 154-i, (i = 0, 1, ..., n-1). -i,. Each word line WLBi is coupled to at least one local word line LWLBi, where i = 0, 1, ..., n-1. The local word line LWLBi 154-i is typically constructed of a high resistance material, such as a N-well or polysilicon, to connect the memory cells and then coupled to WLBi (eg, low-resistance metal WLBi) via contacts or layer indirect points, buffers, Or post decoder 172-i, where i = 0, 1, ..., n-1. When using a diode as a programming selector, a buffer or post decoder 172-i may be required because current flows through WLBi, especially when a WLBi drives multiple memory cells for simultaneous programming and reading. Other embodiments. The word line WLBi is driven by the word line driver 150-i, and can be switched between different voltages in order to program and read its supply voltage vddi. Each BLj 170-j or BLR0 175-0 is programmed via a Y-write channel gate 120-j or 125 to a supply voltage VDDP, respectively, by the selected YSWBj (j=0,1,.. , m-1) or YSWRB0. The Y-write channel gate 120-j (j = 0, 1, ..., m-1) or 125 may be constructed by a PMOS, although an NMOS, diode, or bipolar element may be used in some embodiments. Each BL or BLR0 is coupled to data line DLj or reference data line DLR0 via a Y-read channel gate 130-j or 135, selected by YSRj (j = 0, 1, .., m-1) or YSRR0, respectively. . In the portion of the memory array 101, m normal data lines DLj (j = 0, 1, ..., m-1) are coupled to an input 160 of a sense amplifier 140. The reference data line DLR0 provides the other input 161 of the sense amplifier 140 (generally no multiplexer is required in the reference portion). The output of sense amplifier 140 is Q0.

To program a memory cell, the particular WLBi and YSWBj are turned on and a high voltage is supplied to VDDP, where i = 0, 1, .., n-1 and j = 0, 1, ..., m-1. In some embodiments, the reference memory cell can be programmed to 0 or 1 by turning on WLRBi (i = 0, 1, ..., n-1) and YSWRB0. To read a memory cell, the data column line DLj 160 can be enabled by a specific WLBi and YSRj, (where i = 0, 1, ..., n-1, and j = 0, 1, ..., m- 1) Selected, and a reference data line DLR0 161 can be selected by enabling a particular reference memory unit, both coupled to sense amplifier 140. This sense amplifier 140 can be used to sense and compare the difference in resistance between DL and DLR0 and ground, while turning off all YSWBj and YSWRB0, where j = 0, 1, .., m-1.

Figures 10a and 10b show a flow chart embodiment depicting programmable resistive memory Programming method S700 and reading method S800. Methods S700 and S800 describe the programming and reading of the programmable resistive memory 100 of FIG. 9 in the case of a programmable resistive memory. Moreover, although it is a one-step process, it will be apparent to those skilled in the art that at least some of the steps may be performed in a different order, including simultaneous or skipping.

Figure 10a shows a flow chart for a method S700 for programming a resistive memory. According to this embodiment, in a first step S710, an appropriate power supply selector is selected to apply a high voltage power supply to the word line and bit line drivers. In a second step S720, the data to be programmed is analyzed in the control logic (not shown in Figure 9) depending on the type of programmable resistive element. For electrical fuses, programming is usually a one-time programmable element (OTP), which usually means burning the fuse to a non-original state and is irreversible. The programming voltage and duration are often determined by external control signals rather than from within the memory. In a third step S730, a column of a memory cell is selected so that the opposite local word line can be turned on. In a fourth step S740, the sense amplifier is deactivated to save power and prevent interference to the programmed operation. In a fifth step S750, a row (group) of memory cells can be selected and the corresponding Y-write channel gate can be opened to couple the selected bit line to a supply voltage. At the last step S760, the programmed operation is completed by an established conduction path to drive the required current for a desired period of time. For most programmable resistor memories, this conduction path is made up of a high voltage power supply, through a selected bit line (group), a resistive element, as a diode of the programming selector (group), and a local character. Line driver (group) NMOS pull-down component to ground.

Figure 10b shows a flow chart for programming a resistive memory read method S800 in accordance with another embodiment. In a first step S810, a suitable power selector is provided to select the supply voltage to the local word line driver, sense amplifier and other circuitry. In the second In step S820, all Y-write channel gates, such as bit line programming selectors, can be turned off. In a third step S830, the desired local word line driver (group) can be selected such that the diodes (groups) as programming selectors (groups) have a conductive path to ground. In a fourth step S840, the sense amplifier (group) and the input signal ready for sensing are activated. In a fifth step S850, the data line and the reference data line are precharged to the V-voltage of the programmable resistive element memory cell. In a sixth step S860, the desired Y-read pass gate is selected such that the desired bit line (group) is coupled to an input of the sense amplifier. A conduction path is then established, from the bit line (group) to the desired resistive element of the memory cell, as a diode (group) of the programming selector (group) and a pull-down element of the local word line driver (group) to Ground. The same applies to the reference branch. At the last step S870, the sense amplifier can compare the difference between the read current and the reference current to determine whether the logic output is 0 or 1 to complete the read operation.

FIG. 11 shows an embodiment of a processor system 700. In accordance with this embodiment, processor system 700 can include a programmable resistive element 744, such as in a memory cell array 742, in memory 740. Processor system 700 can, for example, belong to a computer system. The computer system can include a central processing unit (CPU) 710 that communicates with various memory and peripheral devices via a common bus 715, such as input and output unit 720, hard disk drive 730, optical disk 750, memory 740, and other memory 760. The other memory 760 is a conventional memory such as a static access memory (SRAM), a dynamic access memory (DRAM) or a flash memory, usually connected to the central processing unit 710 via a memory controller. communication. Central processing unit 710 is typically a microprocessor, digital signal processor, or other programmable digital logic element. Memory 740 is preferably constructed in an integrated circuit that includes a memory array 742 having at least programmable resistive elements 744. Usually, the memory 740 is connected via a memory controller. The central processing unit 710 is touched. If desired, the memory 740 can be combined with a processor (e.g., central processing unit 710) in a monolithic integrated circuit.

The invention may be implemented in part or in whole in an integrated circuit, on a printed circuit board (PCB), or on a system. The programmable resistive element can be a fuse, an anti-fuse, or an emerging non-volatile memory. The fuse may be a deuterated or non-deuterated polysilicon fuse, a thermally isolated active region fuse, a metal fuse, a contact fuse, or a layer indirect fuse. The antifuse may be a gate oxide breakdown antifuse, a dielectric or a layer indirect antifuse therebetween. Emerging non-volatile memory devices can be magnetic access memory (MRAM), phase change memory (PCM), conductive bridge random access memory (CBRAM) or resistive random access memory (RRAM). Although the programming mechanism is different, its logic state can be distinguished by different resistance values. The above description and drawings are only intended to illustrate the realization of the demonstration.

However, the above description is only for the detailed description and the drawings of the preferred embodiments of the present invention, and the present invention is not limited thereto, and is not intended to limit the present invention. The scope of the patent application is intended to be included in the scope of the present invention, and any one skilled in the art can readily appreciate it in the field of the present invention. Variations or modifications may be covered by the patents in this case below.

30‧‧‧storage unit

30a‧‧‧resistive components

30b‧‧‧ diode

Claims (11)

A single-time programmable memory comprising: a plurality of single-shot programmable memory cells, at least one single-shot programmable memory cell comprising: a single-shot programmable component coupled to a first supply voltage line; and a The diode includes at least one first active region and a second active region separated from the first active region, wherein the first active region has a first type of doping, and the second active region has a second type of doping, first The active region provides a first end of the diode and the second active region provides a second end of the diode. The first active region and the second active region both exist in a common well. The first active region is coupled to the single-shot programmable element, and the second active region is coupled to a second supply voltage line; wherein the first and second active regions are from a complementary MOS transistor The source or the drain of the (CMOS) device is fabricated, and the well is fabricated from a CMOS well. The two active regions are used as two ends of the diode, separated by a dummy MOS gate; two different single-shot properties are available. The diodes of the programmed memory cell are separated by a shallow trench Wherein the single-shot programmable element is configured to be programmable to change the resistance to a different logic state by applying a voltage to the first and second supply voltage lines; wherein the single-shot programmable element is electrically fused Silk composition. The one-time programmable memory of claim 1, wherein the electrical fuse is an internal connection formed by a CMOS gate. a single-time programmable memory as described in claim 1, wherein the electrical property The fuse includes at least polysilicon, deuterated polysilicon, germanide, thermally isolated active regions, local interconnects, metals or metal alloys. The one-time programmable memory of claim 1, wherein the ratio of the length to the width of the single-length programmable element body is 6 to 0.5. The single-length programmable memory of claim 1, wherein at least one of the first or second end of the single-time programmable element or the first end or the second end of the diode is There are no more than two contacts. A single-time programmable memory as claimed in claim 1, wherein the electrical fuse element is coupled to the active region of the diode at a single contact via a metal line. The single-time programmable memory of claim 1, wherein at least one of the first or second end of the single-time programmable element or the first end or the second end of the diode is connected The contact is larger than the contact outside the memory array. A single-time programmable memory as described in claim 1, wherein the diode is a programming selector using a fin field effect transistor technology. The single-shot programmable memory of claim 1, wherein the single-time programmable element is a conductive contact or a layer indirect point. An electronic system comprising: a processor; and a single-shot programmable memory operatively coupled to the processor, the single-shot programmable memory comprising at least a plurality of single-shot programmable memory cells to provide data storage Each of the one-time programmable resistance memory cells includes: a single-shot programmable component coupled to the first supply voltage line; and a diode comprising at least one first active region and a second active region separated from the first An active region, wherein the first active region has a first type of doping, the second active region has a second type of doping, the first active region provides a first end of the diode, the second active a second end of the diode is provided, the first and second active regions are each in a common well, the first active region being coupled to the single-shot programmable element and the second active region Coupled to a second supply voltage line; wherein the first and second active regions are fabricated from a source or drain of a CMOS device, and the well is fabricated from a CMOS well; the two active regions are diodes The two ends of the body are separated by a dummy MOS gate; the diodes of two different single-stage programmable memory cells are separated by a shallow trench; wherein the single-time programmable component is configured to be Programming, changing the single-shot programmable element to a different logic state by applying a voltage to the first and second supply voltage lines; wherein the single-shot programmable element is comprised of an electrical fuse. A method of providing a one-time programmable memory, comprising: providing a plurality of single-shot programmable memory cells, at least one single-shot programmable memory cell including at least (i) a single-shot programmable component coupled to a power supply voltage line; and (ii) a diode comprising at least a first active region and a second active region, the first active region having a first type of doping and the second active region having a second type of doping The first active region provides a first end of the diode, and the second active region provides a second end of the diode, the first and second active regions are both from a source or a MOSFET of the CMOS device Extremely manufactured, and there is a common well that is fabricated from a CMOS well, the first active region being coupled to the single-shot programmable resistance element and the second active region coupled to a second Two power supply voltage lines; the two active regions are used as two ends of the diode, separated by a dummy MOS gate; the two diodes of two different single-stage programmable memory cells are separated by a shallow trench. And programming by applying a voltage to the first and second voltage lines Series state to at least A single-shot programmable memory cell; wherein the single-shot programmable component is comprised of an electrical fuse.