TWI473401B - Charge pump circuit - Google Patents

Description

Voltage boost circuit

The present invention relates to a voltage stabilizing technique, and more particularly to a voltage pump circuit.

As electronic technology tends to be short and light, the driving voltage of today's electronic components, such as processors and memories, has gradually declined. In addition, the tolerance range of the voltage ripple of the driving voltage is also reduced, so that the electronic component can operate at a precise voltage.

Furthermore, the driving voltage of the electronic component may be provided by a charge pump circuit. The charge pump circuit raises (or down) its input voltage level at a predetermined rate to produce voltages of different levels. When the current at the output of the charge pump circuit changes due to load changes, if the current cannot be detected and changed for this current, the output voltage will be more severely chopped with the load current.

In order to stabilize the output voltage of the charge pump circuit, in the past, multiple comparators were used to detect the level change, and then the output voltage was adjusted to the desired level. For this analog detection mechanism, the circuit design is complicated due to the use of a plurality of comparators, and it is easy to increase power consumption and increase manufacturing cost.

In view of this, in order to solve the problems described in the prior art, an embodiment of the present invention provides a voltage pump circuit including: a voltage source module, a feedback circuit, a comparator, a first PMOS transistor, and a first Two PMOS transistors and control circuits. The voltage boost circuit has a voltage output. The voltage source module includes a positive voltage pump. The voltage source module is configured to provide a drive voltage. The feedback circuit is coupled to the voltage output and provides a feedback voltage associated with the voltage output. The comparator is coupled to the feedback circuit and the voltage source module, and compares the reference voltage with the feedback voltage to generate an error signal. The source of the first PMOS transistor is coupled to the driving voltage, and the drain of the first PMOS transistor is coupled to the voltage output terminal. The source of the second PMOS transistor is coupled to the driving voltage, and the drain of the second PMOS transistor is coupled to the voltage output terminal. The control circuit is coupled to the voltage source module, the comparator, the first PMOS transistor and the second PMOS transistor, and the control circuit is configured to generate the detection signal by sampling the error signal at least twice according to the oscillation signal in the time domain, The first PMOS transistor is switched by the detection signal and the error signal, and the second PMOS transistor is switched by the error signal, thereby stabilizing the voltage level of the voltage output terminal.

In an exemplary embodiment of the invention, the voltage source module includes an oscillator, or a gate, a clock generator, and a positive voltage pump. The oscillator is used to generate an oscillating signal. Or the gate receives the oscillation signal and the error signal. The clock generator is configured to generate a clock signal according to the oscillation signal or the error signal. The positive voltage pump generates a driving voltage according to the clock signal.

In an exemplary embodiment of the invention, the feedback circuit includes a PMOS transistor string coupled between the voltage output terminal and the ground terminal.

In an exemplary embodiment of the invention, each of the PMOS transistor strings The drain of a PMOS transistor is coupled to its own gate.

In an exemplary embodiment of the invention, the inverting input of the comparator is coupled to the reference voltage, and the non-inverting input of the comparator is coupled to the feedback voltage.

In an exemplary embodiment of the invention, the first PMOS transistor has a relatively wide channel width relative to the second PMOS transistor.

In an exemplary embodiment of the invention, the channel widths of the first PMOS transistor and the second PMOS transistor are 90 micrometers and 10 micrometers, respectively.

In an exemplary embodiment of the invention, the control circuit includes a detection circuit, a first switch control unit, and a second switch control unit. The detecting circuit receives the oscillation signal and the error signal, and the detecting circuit is configured to sample the error signal according to the rising edge and the falling edge of the oscillation signal respectively. The first switch control unit switches the first PMOS transistor according to the detection signal and the error signal. The second switch control unit switches the second PMOS transistor according to the error signal.

In an exemplary embodiment of the invention, the detection circuit includes a first flip-flop, a second flip-flop, and a non-gate. The input end of the first flip-flop receives the detection signal, and the clock input terminal receives the oscillation signal. The input end of the second flip-flop receives the detection signal, and the inverted clock input receives the oscillation signal. The first input end and the second input end of the non-gate are respectively coupled to the output ends of the first flip-flop and the second flip-flop, and the output of the non-gate is outputting the detection signal.

In an exemplary embodiment of the invention, when the control circuit determines that the voltage level of the voltage output terminal is within the preset chopping range, the first PMOS transistor is turned off.

Based on the above, in the present invention, the control circuit generates the detection signal by detecting the signal at least twice in the time domain based on the oscillation signal. The first PMOS transistor is switched with the error signal, and the second PMOS transistor is switched by the error signal, and the first PMOS transistor can have a relatively wide channel width with respect to the second PMOS transistor. Therefore, the voltage level outputted by the voltage pump circuit can be appropriately adjusted without excessive voltage chopping, thereby solving the problems described in the prior art.

It is to be understood that the foregoing general description and claims

10‧‧‧Voltage pump circuit

110‧‧‧Voltage source module

112‧‧‧Oscillator

114‧‧‧ or gate

116‧‧‧ Clock Generator

118‧‧‧Positive voltage pump

120‧‧‧Return circuit

120_1~120_5‧‧‧ PMOS transistor

130‧‧‧ comparator

140‧‧‧Control circuit

142‧‧‧Detection circuit

144‧‧‧First switch control unit

146‧‧‧Second switch control unit

202‧‧‧First forward and reverse

204‧‧‧second flip-flop

206‧‧‧Non-gate

A, B‧‧‧sampled content

GND‧‧‧ ground terminal

Sdet‧‧‧ error signal

Shvosc‧‧‧ oscillation signal

Sosc‧‧‧ clock signal

Svpon‧‧‧Detection signal

SW1‧‧‧First PMOS transistor

SW2‧‧‧Second PMOS transistor

T_PUMP‧‧‧ voltage output

Vdrive‧‧‧ drive voltage

Vfdbk‧‧‧ feedback voltage

Vpump‧‧‧ output voltage

Vref‧‧‧reference voltage

The following drawings are a part of the specification of the invention, and are in the

FIG. 1 is a circuit block diagram of a charge pump circuit 10 according to an exemplary embodiment of the present invention.

FIG. 2 is a schematic diagram of an implementation of the control circuit 140 of FIG. 1.

3 and 4 are partial operational waveform diagrams of the detection circuit 142 of FIG. 2.

DETAILED DESCRIPTION OF THE INVENTION Reference will now be made in detail to the exemplary embodiments embodiments In addition, the same or similar reference numerals are used in the drawings and the embodiments to represent the same or the like.

FIG. 1 is a circuit block diagram of a charge pump circuit 10 according to an exemplary embodiment of the present invention. Referring to FIG. 1, the voltage pump circuit 10 includes a voltage source module 110 and a feedback circuit. (feedback circuit) 120, a comparator 130, a first PMOS transistor SW1, a second PMOS transistor SW2, and a control circuit 140.

The voltage boost circuit 10 has a voltage output T_PUMP. The voltage source module 110 includes a positive voltage pump 118. The voltage source module 110 is configured to provide a drive voltage Vdrive. The feedback circuit 120 is coupled to the voltage output terminal T_PUMP and provides a feedback voltage Vfdbk associated with the voltage output terminal T_PUMP. The comparator 130 is coupled to the feedback circuit 120 and the voltage source module 110. The comparator 130 compares the reference voltage Vref with the feedback voltage Vfdbk to generate an error signal Sdet. The source of the first PMOS transistor SW1 is coupled to the driving voltage Vdrive, and the drain thereof is coupled to the voltage output terminal T_PUMP. The source of the second PMOS transistor SW2 is coupled to the driving voltage Vdrive, and the drain thereof is coupled to the voltage output terminal T_PUMP.

In the present exemplary embodiment, the control circuit 140 is coupled to the voltage source module 110, the comparator 130, the first PMOS transistor SW1, and the second PMOS transistor SW2. The first PMOS transistor SW1 may have a relatively wide channel width with respect to the second PMOS transistor SW2. For example, the channel widths of the first PMOS transistor SW1 and the second PMOS transistor SW2 are 90 micrometers and 10 micrometers (μm), respectively, but are not limited thereto.

The control circuit 140 is configured to generate the detection signal Svpon by sampling the error signal Sdet at least twice in the time domain based on the oscillation signal Shvosc. The first PMOS transistor SW1 is switched by the detection signal Svpon and the error signal Sdet, and the second PMOS transistor SW2 is switched by the error signal Sdet. In addition, it is assumed that the channel widths of the first PMOS transistor SW1 and the second PMOS transistor SW2 are 90 micrometers and 10 micrometers, respectively. When the first PMOS transistor SW1 and the second are turned on at the same time PMOS transistor SW2, with a fast adjustment (similar to coarse adjustment, channel width of 100 microns) output voltage Vpump level effect; and only turn on the second PMOS transistor SW2 can produce micro-step adjustment (similar to fine-tuning, channel width 10 Micron) The output voltage Vpump level effect prevents the voltage from rising too fast (or voltage burst).

For example, when the voltage level of the output voltage Vpump at the voltage output terminal T_PUMP has not reached the preset level, the first PMOS transistor SW1 and the second PMOS transistor SW2 are both turned on (the channel width is equivalent to 100 micrometers). ) so that the output voltage Vpump quickly reaches the preset level. After the output voltage Vpump reaches the preset level, if the output voltage Vpump does not fall below a preset level of, for example, ±0.1% (preset chopping range), the control circuit 140 switches only the second PMOS. The transistor SW2 (channel width is equivalent to 10 μm) and the first PMOS transistor SW1 is turned off. After the output voltage Vpump reaches the preset level, if the output voltage Vpump decreases by more than 0.1% of the preset level, the control circuit 140 can switch the first PMOS transistor SW1 and the second PMOS transistor again. SW2, according to the quick adjustment to the preset level. Therefore, the control circuit 140 can reduce the ripple variation of the output voltage Vpump, so that the voltage level of the voltage output terminal T_PUMP can be stabilized.

On the other hand, the voltage source module 110 can include an oscillator 112, or a gate 114, a clock generator 116, and a positive voltage pump 118. The oscillator 112 is used to generate an oscillation signal Shvosc. The OR gate 114 receives the oscillation signal Shvosc and the error signal Sdet. The clock generator 116 is configured to generate the clock signal Sosc according to the oscillation signal Shvosc or the error signal Sdet. The positive voltage pump 118 generates a driving voltage Vdrive according to the clock signal Sosc. When the error signal Sdet generated by the comparator 130 is represented as a logic 1, it represents that the output voltage Vpump has reached the preset level, and will cause the OR gate 114 to also Logic 1 is output to turn off clock generator 116.

The feedback circuit 120 can include a PMOS transistor string composed of PMOS transistors 120_1~120_5. The PMOS transistor string (120_1~120_5) is coupled between the voltage output terminal T_PUMP and the ground terminal GND. The feedback voltage Vfdbk can be provided where the PMOS transistors 120_4 and 120_5 are coupled. In addition, the feedback voltage Vfdbk may also be provided at the coupling of the PMOS transistors 120_3 and 120_4 (not shown), so the feedback voltage Vfdbk may be proportional to the output voltage Vpump. In addition, the drain of each PMOS transistor in the PMOS transistor string (120_1~120_5) is coupled to its own gate, and this connection can produce an effect similar to a diode. The PMOS transistor string can also be replaced with a resistor string, but the PMOS transistor string can pass a small current.

The inverting input terminal of the comparator 130 is coupled to the reference voltage Vref, and the non-inverting input terminal of the comparator is coupled to the feedback voltage Vfdbk.

More specifically, the control circuit 140 includes a detection circuit 142, a first switch control unit 144, and a second switch control unit 146. The detection circuit 142 is shown in FIG. 2 and may include a first flip-flop 202, a second flip-flop 204, and a non-OR gate 206. The input end of the first flip-flop 202 receives the detection signal Sdet, and the clock input terminal receives the oscillation signal Shvosc. The input end of the second flip-flop 204 receives the detection signal Sdet, and the inverted clock input terminal receives the oscillation signal Shvosc. The first input end and the second input end of the non-OR gate 206 are respectively coupled to the output ends of the first flip-flop 202 and the second flip-flop 204, and the output end of the non-gate 206 outputs the detection signal Svpon.

3 and 4 are partial operational waveform diagrams of the detection circuit 142 of FIG. 2. Please refer to Figure 2 to Figure 4. As can be clearly seen from FIG. 3, the detecting circuit 142 receives the oscillation signal Shvosc and the error signal Sdet, and the detecting circuit 142 is oscillating. The rising edge and the falling edge of the signal Shvosc are respectively sampled with the error signal Sdet, wherein the samples of the first flip-flop 202 and the second flip-flop 204 are represented by symbols A and B, respectively. When A=0 and B=0. The sampling contents A and B are then generated via the non-OR gate 206 and the logic 1 detection signal Svpon is output.

In addition, it can be clearly seen from FIG. 4 that the detecting circuit 142 performs sampling for each of the rising edge and the falling edge of the oscillation signal Shvosc and the error signal Sdet, wherein the first flip-flop 202 and the second flip-flop 204 When the sampling contents are represented by symbols A and B, respectively, A=0 and B=1. The sampling contents A and B are then generated via the non-OR gate 206 and the logic 0 detection signal Svpon is output.

The corresponding relationship between the sampling content, the truth table of the detection signal and the working state is shown in Table 1.

On the other hand, although Table 1 is the first PMOS transistor SW1 and the second PMOS transistor SW2 as embodiments, those skilled in the art can change the design of the detection circuit 142 based on actual design or application requirements, so that Control circuit 140 can correspondingly control more than two PMOS transistors having different channel widths.

Based on the above, the control circuit 140 uses a digital detection mechanism to detect The signal on the domain, therefore, the circuit design of the present invention is simpler than the conventional analog detection mechanism, and does not increase the additional power consumption, but also reduces the manufacturing cost.

In summary, in the present invention, the control circuit generates a detection signal by sampling the error signal at least twice in the time domain according to the oscillation signal, and then switching the first PMOS transistor by detecting the signal and the error signal. And the second PMOS transistor can be switched by the error signal, and the first PMOS transistor can have a relatively wide channel width with respect to the second PMOS transistor. Therefore, the voltage level outputted by the voltage pump circuit can be appropriately adjusted without excessive voltage chopping, thereby solving the problems described in the prior art.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

In addition, any of the objects or advantages or features of the present invention are not required to be achieved by any embodiment or application of the invention. In addition, the abstract sections and headings are only used to assist in the search of patent documents and are not intended to limit the scope of the invention.

10‧‧‧Voltage pump circuit

110‧‧‧Voltage source module

112‧‧‧Oscillator

114‧‧‧ or gate

116‧‧‧ Clock Generator

118‧‧‧Positive voltage pump

120‧‧‧Return circuit

120_1~120_5‧‧‧ PMOS transistor

130‧‧‧ comparator

140‧‧‧Control circuit

142‧‧‧Detection circuit

144‧‧‧First switch control unit

146‧‧‧Second switch control unit

GND‧‧‧ ground terminal

Sdet‧‧‧ error signal

Shvosc‧‧‧ oscillation signal

Sosc‧‧‧ clock signal

Svpon‧‧‧Detection signal

SW1‧‧‧First PMOS transistor

SW2‧‧‧Second PMOS transistor

T_PUMP‧‧‧ voltage output

Vdrive‧‧‧ drive voltage

Vfdbk‧‧‧ feedback voltage

Vpump‧‧‧ output voltage

Vref‧‧‧reference voltage

Claims (10)

A voltage pump circuit having a voltage output terminal, the voltage pump circuit comprising: a voltage source module comprising a positive voltage pump, the voltage source module configured to provide a driving voltage; a feedback circuit, The voltage output terminal is coupled to the voltage output terminal and provides a feedback voltage associated with the voltage output terminal; a comparator coupled to the feedback circuit and the voltage source module to compare a reference voltage with the feedback voltage to generate an error a first PMOS transistor having a source coupled to the driving voltage and a drain coupled to the voltage output terminal; a second PMOS transistor having a source coupled to the driving voltage and a drain coupled to the first PMOS transistor a voltage output terminal; and a control circuit coupled to the voltage source module, the comparator, the first PMOS transistor and the second PMOS transistor, the control circuit configured to be based on an oscillation signal in the time domain Sampling the error signal to generate a detection signal, switching the first PMOS transistor by the detection signal and the error signal, and switching the second PMOS transistor by the error signal, thereby stabilizing The voltage output The voltage level. The voltage pump circuit of claim 1, wherein the voltage source module comprises: an oscillator for generating the oscillation signal; and a gate for receiving the oscillation signal and the error signal; And generating a signal according to the oscillation signal or the error signal a clock signal; and the positive voltage pump generates the driving voltage according to the clock signal. The voltage pump circuit of claim 1, wherein the feedback circuit comprises: a PMOS transistor string coupled between the voltage output terminal and a ground terminal. The voltage boost circuit of claim 3, wherein the drain of each of the PMOS transistors in the PMOS transistor string is coupled to its own gate. The voltage boost circuit of claim 1, wherein the inverting input of the comparator is coupled to the reference voltage, and the non-inverting input of the comparator is coupled to the feedback voltage. The voltage boost circuit of claim 1, wherein the first PMOS transistor has a relatively wide channel width relative to the second PMOS transistor. The voltage boost circuit of claim 6, wherein the first PMOS transistor and the second PMOS transistor have channel widths of 90 micrometers and 10 micrometers, respectively. The voltage pump circuit of claim 1, wherein the control circuit comprises: a detecting circuit for receiving the oscillation signal and the error signal, wherein the detecting circuit is configured according to a rising edge and a falling of the oscillation signal The edge is respectively sampled with the error signal; a first switch control unit switches the first PMOS transistor according to the detection signal and the error signal; and a second switch control unit switches the first signal according to the error signal Two PMOS transistors. The voltage boosting circuit of claim 8, wherein the detecting circuit comprises: a first flip-flop, the input end receiving the detecting signal, and the clock input end receiving the oscillation signal; a second flip-flop, the input end of which receives the detection signal, the inverting clock input terminal receives the oscillation signal; and a non-OR gate, the first input end and the second input end are respectively coupled to the first positive and negative ends And the output of the second flip-flop, the output of the non-gate is outputting the detection signal. The voltage pump circuit of claim 1, wherein the first PMOS transistor is turned off when the control circuit determines that the voltage level of the voltage output terminal is within a predetermined chopping range.