TWI470628B - Programmable matrix array with chalcogenide material - Google Patents

Description

Programmable matrix array with chalcogenide material

This case is a partial continuation of U.S. Patent Application Serial No. 10/459,632 (filed on June 11, 2003). This case is also a partial continuation of US Patent Application No. 11/032,792 (filed on January 11, 2005). This case is also a partial continuation of US Patent Application No. 11/158,619 (the application date is June 21, 2005). U.S. Patent Application Serial No. 10/459,632, incorporated herein by reference. U.S. Patent Application Serial No. 11/032,792, incorporated herein by reference. U.S. Patent Application Serial No. 11/158,619, incorporated herein by reference.

SUMMARY OF THE INVENTION The present invention is generally directed to a programmable integrated circuit device, and more particularly to a programmable matrix array having a programmable connection of phase change materials having a transistor coupled by a drive intersection.

In general, the phase change material can be electrically connected between the first structural state (in which the material is generally amorphous) and the second structural state (in which the material is generally crystalline). Stylized. The term "amorphous" as used herein, refers to a structural state that is relatively out of order or less confusing than a single crystal. The term "crystalline" as used herein refers to a structural state that is more ordered than a non-crystalline state. Phase change materials exhibit different electrical characteristics depending on their state. For example, in its crystalline state, the material exhibits a lower resistivity in a more ordered state than a less ordered state of its amorphous form. Each material can be associated with a corresponding logical value. For example, a lower resistive crystalline state can be associated with a logic "1" and a higher resistive amorphous state can be associated with a logic "0."

Materials which can be used as phase change materials include alloys of elements of Group VI of the Periodic Table. The elements of these Group VI are referred to as chalcogen elements and contain the elements Te and Se. Alloys containing one or more chalcogen elements are referred to as chalcogenide alloys. An example of a chalcogenide alloy that can be used as a phase change material is the alloy Ge ₂ Sb ₂ Te ₅ (also known as GST225). An example of a chalcogenide alloy particularly useful as a threshold switching material is Si ₁₄ Te ₃₉ As ₃₇ Ge ₉ X ₁ , where X can be element In or element P.

The phase change material can change state by applying an electrical signal. The electrical signal can be a voltage or current that crosses the phase change material. The electrical signal can be in the form of one or more electrical pulses. As an example, the amount of material can be programmed from its higher resistance reset state (less amorphous) by applying an electrical pulse (eg, a current pulse) called a set pulse. It has a lower resistance set state (less amorphous and more crystalline). While not wishing to be bound by the theorem, it is believed that the set pulse is sufficient to change at least a portion of the amount of memory material from a less ordered amorphous state to a more ordered crystalline state. The amount of material can be programmed from the low resistance set state back to the high resistance reset state by applying an electrical pulse (eg, a current pulse) called a reset pulse that is stronger than the set pulse. While not wishing to be bound by the theorem, it is believed that the reset pulse is sufficient to change the volume of at least a portion of the memory material from a more ordered crystalline state to a less ordered amorphous state. It will be appreciated that other forms of energy (not limited to optical energy, such as from a laser), including thermal, electromagnetic or mechanical energy (e.g., acoustic energy), may also be used to alter the state of the amount of material.

Phase change materials can be used to form phase change memory. Typically, phase change memory systems are arranged in an array of phase change memory cells having rows and columns associated with word lines and bit lines, respectively. Each memory unit includes a memory component. The memory unit can further include an access device (also referred to in the art as an insulating device or steering element). The access device can be coupled in series with the body element. Examples of access devices include, but are not limited to, diodes, transistors, and threshold switching elements. The threshold switching element can also be referred to as a threshold switcher. The threshold switching element can be made of a chalcogenide material. The threshold switching element can be made of an S-type threshold switching material. An example of the use of a throttling switching element as an access device is disclosed in U.S. Patent No. 3,573,757, the disclosure of which is incorporated herein by reference.

In a memory array, each memory cell can be coupled between a different word line (also referred to as a row line or an X line) and a different bit line (also referred to as a column line or a Y line).

The memory cells can be selected to be a read operation by applying a suitable voltage to the individual word lines and appropriate current or voltage pulses to the individual bit lines. In response to forcing a current into the bit line, the voltage reaching the bit line depends on the resistance of the storage element, that is, the logic value stored in the selected memory cell.

For general memory usage, the logic values stored in the memory cells can be evaluated by the memory's sense amplifier, regardless of the standard or embedded. Typically, the sense amplifier includes a comparator for receiving a bit line voltage, or an associated voltage, and a suitable reference voltage. As an example of the current that is forced into the selected row, if the bit line driven by the read current reaches a voltage higher than the reference voltage in the case of a relatively low resistance and high resistance, the bit can be Decided to correspond to a stored logical value "0", and conversely, if the bit line voltage is less than the reference voltage for a cell with lower resistance, the bit can be determined to correspond to the stored The logical value is "1".

Even if the lines to be interconnected can be at the same level (by using cross-under (eg poly or N+)), such as a product of a programmable logic device, by providing interconnection to the user's specifications Standard logic (typically via X-Y grid) achieves a random logic design. This X-Y cell is conceptually similar to the X-Y cell of the memory array and is composed of X lines (corresponding to, for example, columns or word lines) and a plurality of Y lines (corresponding to, for example, rows or bit lines). The X-ray typically crosses the Y line (above or below). The X-rays can be oriented in a first direction, and the Y-lines can be oriented in a second direction that is different from the first direction. The X line can be substantially perpendicular to the Y line. The X line can be actually spaced apart from the Y line. The X line can be insulated from the Y line, however, it is possible for the X line to be pre-wired to the Y line, for example via a shorting contact. When interconnecting logic (instead of a memory element of a memory array), the X-Y cell can be more random in space and is less irregular in length than the X-Y cell of the body array.

In a memory array, the impedance between the X and Y lines is preferably very high, such as an open circuit, until the selected device is enabled, such as by column selection or row selection, or column selection and Lines choose both. This selection may require lowering or raising the X and/or Y line. Selecting a particular X line reduces the impedance between the memory element and the corresponding X line, and the path of the impedance does not need to go to the selected X line, but instead replaces, for example, the path to ground. When the path within the unit is to ground, a selection memory can be used, where the gate is controlled by the X-ray. If the path within the unit is to the X-ray, the selection means can be, for example, a diode or a threshold switching element. The particular type of impedance of the threshold switching element can be reduced when the voltage across the component equals or exceeds the threshold voltage. The component is turned on so that the voltage across the component can quickly return to a hold voltage that is less than the threshold voltage. The threshold switching element can remain conductive until the current flowing through the element drops below the holding current.

Conversely, the X-Y cells of the wires used to interconnect logic (eg, in a programmable logic array) may have relatively linear resistance (rather than a piecewise linear resistance) between the lines. For logic devices (eg, programmable logic arrays), the resistance at the junction (open circuit) can be relatively high, while the resistance at the junction (short circuit) can be relatively low.

Determining the appropriate connection between the logic gate and the X and Y lines at the intersection in the electronic function can be programmed in different ways. One stylized technique for selectively determining connections is mask programming. This is done by the semiconductor manufacturer during the wafer fabrication process. Examples of mask programmable devices include mask programmable gate arrays, mask programmable logic arrays, and mask programmable ROMs. In the case where the mask is programmable, the CLOSED connection can be an actual short between the X and Y lines at the point of intersection (eg, by using contacts or vias), while the OPEN connection can be It is an actual open circuit (wherein the wires may be separated by an insulator such as hafnium oxide or tantalum nitride). This approach is characterized by high layout efficiency and performance, but high processing costs and time delays for becoming the first article product due to the use of custom masks and layouts in different customer products, and this It needs to be generated and applied before the customer's specific product is completed.

Compared to the mask programmable device, the field programmable device is programmed after manufacture. Examples of field programmable devices include Programmable ROM (PROM), Electrically Erasable ROM (EEPROM), Field Programmable Logic Array (FPLA), Programmable Logic Array (PAL) ), Complex Programmable Logic Device (CPLD), Field Programmable Gate Array (FPGA).

The field programmable device utilizes a programmable connection at the intersection of the X-ray and the Y-line to program the device after manufacture, and the stylization can be made by the manufacturer to the customer specification, or after receipt by the OEM, Or by the end customer in the field (even if it is periodically updated, for example via the Internet, it can update the connection or correct the errors found in the field).

For field programmable devices (such as Field Programmable Logic Arrays (FPLA)), a programmable connection can be made so that the relatively high resistance between the lines represents the OPEN connection between the lines, while the relatively low resistance Represents a CLOSED connection between lines. Products with relatively low resistance for CLOSED connections can be faster because of their improved voltage margin. If the stylized connection of the interconnected wires is low (as with interconnected wires and devices), the margins and speeds can also be improved. Programmable connections with higher resistance for OPEN connections can have lower leakage and better voltage margins, since those connections that are intended to be OPEN connections can have voltage differences between the lines (when applying various Level or logic state to the driver and/or receiver line). That is, any resistor between the lines flows current and increases battery drain while reducing the voltage margin.

In larger logic arrays with more X-Y interconnects (and thus more intersections), the power lost by the intersection of the OPEN attempts is a larger problem. For non-masked, programmable field programmable devices, whether or not combined with logic or other electronic functions, a programmable connection is required that provides relatively low resistance in the CLOSED connection and relative in the OPEN connection. High resistance. Preferably, the programmable connection should also add a small amount of capacitance to the interconnected wires without altering the wafer fabrication process as much as possible.

A programmable connection to a field programmable device (Field Programmable Logic Array (FPLA)) can be a volatile or non-volatile connection (the difference is whether the device must be reprogrammed at each power recovery) ). For example, when the computer is turned off, the desired logical pattern in the field programmable logic chip can be stored on the hard disk. Once the power supply is turned back on, after a delay, the logic interconnect pattern can be reloaded into the architectural memory component of the interconnect between the control logic gate and other functions. This volatility mode stores the state of the programmable connection at each intersection of the static random access memory (SRAM) that drives the n-channel intersection point transistor, as shown in Figure 1.

Figure 1 shows an example of a programmable connection using a conventional SRAM technique to drive the gate of an n-channel transistor QI at an intersection. The p-channel pull-up transistors Q2 and Q4 provide a high logic level close to the power supply, while the n-channel pull-down transistors Q6 and Q8 are pulled in a normal CMOS mode to a lower power supply. . Here, the p-channels Q2 and Q4 are also coupled to the SRAM such that the node N2 or N4 can be high and the other is low. Line PX can select the SRAM via transistor Q12 so that data can be written into the architectural bits from line PY (where the data can be supplied and driven by the processor). Output node N2 drives the gate of transistor QI to be conductive when the gate of QI is very high, or non-conducting when the gate is driven (by stylized SRAM) to a low or off state. The transistor QI is coupled between the Y wire and the X wire.

Programmable connections can be characterized by: capacitance and resistance at voltage and temperature ranges of interconnected lines in their worst case, and lower resistance (when "on") provide less delay With a preferred voltage and voltage margin. It is especially desirable to be low during the transition of the coupled line from high to low or from low to high. Higher resistance (when "off") (line uncoupled) provides lower leakage and battery drain, as well as improved voltage margins by reducing line and driver voltage drops due to leakage.

In the SRAM-type programmable connection example version in Figure 1, the source-to-drain "on" resistance system is for the voltage on the coupled X and Y lines (which is less than the power supply to the driving gate). Lower, this is due to the fact that the resistance from the source to the drain of the n-channel transistor tends to increase as the source and drain voltages approach the gate voltage. Therefore, in some of the more complex versions, the n-channel transistor QI can have a particularly low threshold voltage Vt, or the power supply in the architecture control SRAM can be higher than the logic interconnect region, even when X and Y are When high, the N2 line is high enough and the QI is on.

Alternatively, the n-channel transistor QI can be parallel to the p-channel with its gate driven by node N4. This full multiplexer approach provides lower resistance, but for each matrix switcher, it can have larger capacitance and increased die area.

In a further example, to make this mode non-volatile, the SRAM of Figure 1 can be replaced by an EPROM, EEPROM, or flash memory transistor that is properly loaded to drive the n-channel interconnect transistor QI. Or the SRAM can be mirrored in a non-volatile memory such as FeRAM. Stylized non-volatile memory can be implemented by a particularly high voltage or current for non-volatile components. However, this approach increases program complexity.

Furthermore, both SRAM or alternative non-volatile memory require a significant area on the substrate to control the interconnect transistor. In addition, the interconnecting transistor of the coupling wire uses the upper region of the substrate stack (and forms the wafer).

Connections in a field programmable device (eg, FPLA) can also be made non-volatile by using an antifuse in the X-Y interconnect, as shown in Figure 2A, which is shown coupled to the X-ray and Anti-fuse 10 between the Y lines. This product (eg, FPLA and FPGA) desirably reduces the area and layer of the wafer dedicated to programming the programmable connection by stabilizing the semiconductor active device (by removing the SRAM) and interconnecting the programmatic SRAM ( For example, PX and PY) are used in each switch. This can also be achieved by forming an intersecting-point transistor as a thin film layer between the interconnect layers, thereby removing the relevant substrate by SRAM (or other non-volatile alternatives such as flash memory, FeRam, or EEprom) Stylized intersection area of the transistor.

The antifuse 10 is connected as an OPEN before being programmed. The OPEN connection is characterized in that the amount of leakage has a maximum voltage between the coupled X-Y lines. The antifuse can be achieved by using an insulating breakdown material that is collapsed to provide a conductive path (which is applied across the material by applying a sufficiently high voltage).

Once the antifuse is programmed into a lower resistance state, it is difficult to easily reverse it. Therefore, it is difficult to test the system before shipment or in the field (either by the OEM manufacturer or by the customer) because it is impractical to return a stylized anti-fuse. Similarly, subsequent changes in the field (such as remote connections via a modem or the Internet) may not be possible to reduce repair and update costs, since the antifuse is punctured once low. The resistance state may not be able to recover (unlike the unrealistically high current that reversibly affects the reliability). If the high resistance is required after the cross-connect is programmed into a low resistance state, the wafer must be replaced instead of being programmed.

The antifuse 10 can be formed as a metal-metal antifuse, as shown in FIG. 2B, comprising a first metal layer 12A, a second metal layer 12B, a dielectric layer 14, and a collapse layer 16. The metal layers 12A, 12B may be made of an alloy of tungsten, titanium, and tantalum. The collapse layer 16 can be made of amorphous germanium.

The manufacturer of the device can find errors in the FPLA operations/functions after stylization (in the factory and shipping to the customer), which can be corrected (if the stylization is repliable), which may therefore allow for example, via remote dial-up or Internet access downloads to reprogram the logic corrections. Alternatively, the wafer can be removed from the field and reprogrammed by inserting the adapter card into the computer.

However, although the choice of this SRAM or its non-volatile reprogrammable equivalent is possible, the choice of this anti-fuse based approach is not possible. Instead, the department must be removed and replaced, perhaps a substantial expense for the manufacturer and inconvenient for the customer.

Furthermore, since the non-recoverable link is only programmed in one direction, such as an anti-fuse based FPGA, the array that the customer wants to use can only be indirectly tested, for example, by a The main array side of the interconnect fuses, stylized unused but representative anti-fuse. However, the actual (untested) link by the customer may not be successful, as the link or intersection actually used may be defective because it was not tested before being shipped or used. If personalization is done after assembly, the intersection that is found to be unprogrammable will require the unit to be returned to the factory or even replaced at the final device.

These discards can be very costly and require undesired manufacturing and field use processes that do not conform to the preferred zero defect process and use. Compared to the more testable SRAM-based approach, the size and complexity of non-recoverable fuse-based or anti-fuse methods can be limited to relatively small interconnects in order to increase "yield" and reduce defects in the field. The array.

Furthermore, non-SRAM based approaches can add processing steps after the steps of manufacturing logic to be interconnected, and those additional processing steps can significantly increase cost. Customers prefer lower cost and lower power, more testable non-volatile storage, suggesting that this additional processing step for SRAM is preferably offset by reduced wafer size and processing steps.

Therefore, there is a need for a programmable matrix array that uses non-volatile, programmable connections that are recyclable both in the factory and in the field.

One aspect of the invention is a programmable connection comprising a non-volatile, programmable resistive material, such as for use in a control circuit to drive a transistor coupled between an X-ray and a Y-line (or another A phase change memory material of a type of controllable interconnect device. This programmable connection can be programmed by controlling the state of the transistor (or other form of controllable interconnect). The state of the transistor can be controlled by changing the state of the phase change material.

The phase change memory material can be coupled between a selection device (eg, a chalcogenide or S-type threshold switch, a transistor, or a diode) between address lines (eg, CX lines and CY lines) and stylized The memory material can be implemented by boosting the voltage between the address lines to a threshold voltage that exceeds the selection device and the phase change material, and then passing sufficient current through the phase change material for the state change. The current limit can be increased by increasing the source-drainage of the transistor in series with the bond, and the gate of the transistor is biased to be slightly conductive for normal operation and to be heavily conductive to program.

To further reduce the power at the unused intersection points, the crash layer can be connected in series with the memory material and the selection device between the address lines. The collapse layer can be used as part of a combined memory component or selection device or can be formed as part of a crash device (eg, an anti-fuse). The collapse layer can be formed from a dielectric material. The collapse layer can be configured to be serially coupled between the selection device and the power supply or current supply. When a crash layer is included, it must be crashed before the phase change material can be programmed. Thus, due to the collapsed layer, the initial stylization to the CLOSED connection (eg, the on-site ("on") intersection point transistor) may, for example, not only require resetting the phase change material to its high resistance state, but also by voltage or The current penetrates or collapses the collapsed layer, creating a current path.

The programmable connection can be tested by stylizing the phase change material to a set state and then to a reset state. It should be noted that only those stylized connections that may be CLOSED (initial or later) may require a breakdown of the crash layer (at the factory or during initial customer testing). For example, if a customer knows that some intersections of general-purpose FPLAs will probably not be used in some applications, the corresponding crashable layer of the stylized connection need not be punctured. Since the crash layer allows the stylized connection to have a higher impedance until it is chiseled, it reduces leakage while remaining generally resilient to each X-Y interconnect for later staging (if needed). The dielectric (if considered an anti-fuse) is thus made reversible in the field.

Permanently connected interconnects can also be used for other logical connections to reduce the number of programmable connections, further reducing leakage and testing requirements. Alternatively, similarly connected SRAM programmable connections (or one or more other existing alternatives familiar to those of ordinary skill in the art) as shown in Figure 1 may be connected in parallel to the phase change disclosed herein. Stylized connections, or use of phase changeable stylized connections on the same wafer, such as those required for faster stylization.

The collapse layer can have a sufficiently high resistance that there is no significant increase in leakage or battery consumption for those stylized connections with a collapsed layer (not selected or chiseled).

Advantageously, a programmable phase change memory element, a selection device (eg, a chalcogenide threshold switch), and a collapse layer (optional) in parallel with the selection device can be fabricated as a thin film layer, such as on a wire (eg, Between CX and CY, as shown below). As such, the wafer size and/or more basic wafer area can be reduced for logic while still being recoverable for improved test capabilities or field repair/changes. The selection device itself may comprise a collapse layer in series with the selection device active material (eg, a threshold switching material). The crash layer can be crashed in stylized connections that are expected to be used for a given application.

Another embodiment of the present invention is an integrated circuit comprising: a plurality of first conductors; a plurality of second conductors; and a plurality of programmable connections, each of the programmable connections being coupled to the plurality of first Between one of the wires and one of the plurality of second wires, each of the programmable connections includes a controllable interconnection device coupled between the first and second wires, such as an interconnect Crystal. The state of the interconnecting transistor can be controlled by a control circuit that includes a phase change memory component in series with the selection device. For example, the interconnect transistor can be a MOS transistor with a control gate. The control gate can be coupled directly or indirectly to the control circuit. The selection means can for example be a transistor, a diode, or a threshold switching element. In order to reduce power, a breakdown layer can be additionally coupled in series between the memory component and the selection device. The crash layer can be punctured only on those stylized interconnects that need to be programmed.

Another embodiment of the present invention is an integrated circuit comprising: a first wire; a second wire; and a controllable interconnection device coupled between the first and second wires, the interconnection The device has a control gate for controlling the state of the interconnect device; and a control circuit including a phase change memory component (coupled between a first node and a control node, the memory component Including a phase change memory material) and an active component (coupled between the control node and a second node, the control node is coupled to the control end of the interconnect device).

Another embodiment of the present invention is an integrated circuit comprising: a first wire; a second wire; and a controllable interconnection device coupled between the first and second wires, the interconnection The device has a control gate for controlling the state of the interconnect device; and a control circuit including a first phase change memory component (including a phase change memory material) and an active component (series coupled Connected to the memory component, the control terminal of the interconnect device is coupled to a node between the memory component and the active component. A transistor can be added in series to limit current consumption during normal operation (not when stylizing control bits).

Another embodiment of the present invention is an integrated circuit comprising: a first wire; a second wire; a controllable interconnection device coupled between the first and second wires; One of the states of the interconnect device controls the circuit, which includes a chalcogenide material. The integrated circuit can be a programmable matrix array. The integrated circuit can be a programmable logic array. The chalcogenide material can comprise a phase change material. The chalcogenide material can comprise a threshold switching material. The chalcogenide material can be a substantially non-phase change material.

Another embodiment of the present invention is an integrated circuit comprising: a first wire; a second wire; a controllable interconnection device coupled between the first and second wires; coupled to the An SRAM device of an interconnect device that includes a chalcogenide material.

Another embodiment of the present invention is an electrical device comprising: a first wire; a second wire; a controllable interconnection device coupled between the first and second wires; a control circuit, A control signal is provided to the interconnect device to control the state of the interconnect device, the control circuit including at least one phase change memory component and/or at least one threshold switch component. The controllable interconnect device can be a transistor such as a MOS transistor or a bipolar transistor. The MOS transistor can be an n-channel transistor. The controllable interconnect device can be a three terminal silicon controlled rectifier. The controllable interconnect device can be a three-terminal threshold switching element, such as a three-terminal chalcogenide threshold switching element. The controllable interconnect device can be any type of controllable impedance device. The electrical device can be an integrated circuit. The electrical device can be a programmable matrix array. The electrical device can be a programmable logic device.

Another embodiment of the present invention is a programmable matrix array comprising: a plurality of first wires; a plurality of second wires; a plurality of controllable interconnect devices, each interconnect device coupled to a corresponding first Between a wire and a corresponding second wire; and a plurality of control units, each control unit controls the state of a corresponding interconnecting device, each control unit comprising a chalcogenide material.

Another embodiment of the present invention is a programmable matrix array comprising: a plurality of first wires; a plurality of second wires; a plurality of controllable interconnect devices, each interconnect device coupled to a corresponding first Between a wire and a corresponding second wire; and a plurality of control units, each control unit controls the state of a corresponding interconnecting device, each control unit comprising a phase change memory component and/or a threshold switching component.

Another embodiment of the present invention is a programmable logic device comprising: a plurality of first wires; a plurality of second wires; a plurality of controllable interconnect devices, each interconnect device coupled to a corresponding first Between a wire and a corresponding second wire; and a plurality of control units, each control unit controls the state of a corresponding interconnecting device, each control unit comprising a chalcogenide material. The chalcogenide material can comprise a phase change material. The chalcogenide material can comprise a threshold switching material. The threshold switching material can be a substantially non-phase change material.

Another embodiment of the present invention is a programmable logic device comprising: a plurality of first wires; a plurality of second wires; a plurality of controllable interconnect devices, each interconnect device coupled to a corresponding first Between a wire and a corresponding second wire; and a plurality of control units, each control unit controls the state of a corresponding interconnecting device, each control unit comprising a phase change memory component and/or a threshold switching component.

Another embodiment of the present invention is a method of operating a programmable logic device, the device comprising an X-ray, a Y-line, and a controllable interconnecting device coupled between the X-ray and the Y-line And a control circuit for controlling the state of the controllable switching element, the control circuit comprising a chalcogenide device, the method comprising: providing the controllable interconnection device; providing the control circuit, the control circuit comprising the chalcogen a device for causing the interconnect device to be in a first state by placing the chalcogenide device in a first state; and causing the interconnect device to be in a second state by placing the chalcogenide device in a second state Second state.

Figure 3 shows an embodiment of an electrically programmable matrix array 100 of the present invention. The programmable matrix array 100 can be used in a programmable logic device. The matrix array includes a first set of wires X1 through X4 (also referred to as X-rays). The X line can be a column line or a word line. The matrix array includes a second set of wires Y1 to Y4 (also referred to as Y-lines). The Y line can be a row line or a word line. In the example shown (not for limitation), there are four X lines and four Y lines. However, in general, it may be one or more X-rays, and may be one or more Y-lines. In one or more embodiments, there may be a plurality of X lines and a plurality of Y lines. In one or more embodiments of the invention, the X and Y lines may be address lines. In one or more embodiments of the invention, there may be more or fewer X lines, even one or zero X lines. For example, in one embodiment of the invention, a ground or power supply can be used in place of the wires. In one or more embodiments, there may even be more or fewer Y lines, even one or zero Y lines.

In the embodiment shown in Figure 3, each X-ray intersects the Y-line at an angle (not above or below). The angle is approximately 90 degrees (i.e., the X line is approximately perpendicular to the Y line). However, it may also be other angles. In one or more embodiments of the invention, the X lines are oriented in one direction and the Y lines are oriented in the other direction. The point at which the X-ray and the Y-line intersect (above or below) is called a cross-over points or cross-points. In one or more embodiments of the invention, it is also possible that the X-rays do not intersect the Y-line.

Embodiments of matrix array 100 include a plurality of programmable connection CPSs. Each of the programmable connection CPSs is coupled between an X-ray and a Y-line.

It should be noted that the present invention includes an embodiment having a first wire, a second wire, and a stabilizable connection coupled between the first and second wires. The first and second wires may meet each other at certain angles. The angle can be about 90 degrees or can be other angles. The first wire can be oriented in a first direction and the second wire can be oriented in a second direction. Alternatively, the first wire may not meet the second wire. For example, the first wire can be adjacent only to the second wire. Likewise, the first wire and the second wire may be parallel to each other. The first wire may be an X wire, and the second wire may be a Y wire.

Similarly, the present invention includes an embodiment having a plurality of first conductors, a plurality of second conductors, and a plurality of programmable connections, wherein each of the programmable connections is coupled to a corresponding one of the first conductors Between one of the corresponding ones of the second wires. The first wire may or may not intersect the second wire.

Figure 4A shows an embodiment of a programmable connection of the present invention showing a programmable connection CPS. The programmable connection CPS includes an NMOS transistor QI coupled between an X line and a Y line. The X line may be, for example, one of X1 to X4 shown in FIG. 3, and the Y line may be, for example, one of Y1 to Y4 shown in FIG. Each of the programmable connections CPS further includes a control circuit 240 coupled to the gate of the MOS transistor QI. Control circuit 240 controls the state of transistor QI. When the signal applied from the control circuit to the gate is a high voltage, the NMOS transistor is turned on to couple the X line to the Y line. However, when the control circuit 240 applies a low voltage to the gate of the QI, the NMOS transistor QI is turned off to interrupt the connection of the X line to the Y line. In the embodiment shown in FIG. 4A, control circuit 240 is coupled to interconnect transistor QI. In one or more embodiments of the invention, control circuit 240 may not be coupled between the X and Y lines. The NMOS transistor QI can be replaced by a PMOS transistor. In particular, the NMOS transistor QI can be replaced by any type of controllable interconnect device. The controllable interconnection means can be, for example, a transistor such as a MOS transistor or a bipolar transistor. The controllable interconnect can be a controllable 矽 rectifier (typically referred to as an SCR). The controllable interconnect can be a three-terminal threshold switching element (such as a chalcogenide three-terminal threshold switching element). The controllable interconnect can be any type of controllable switch. Examples of controllable switches include transistors (such as MOS transistors or bipolar transistors) and controllable 矽 rectifier (SCR) devices. The controllable switch can be a three-terminal switch. One of the terminals may be a control terminal that controls a conductive path between the other two ends.

The controllable interconnect device can include a control terminal such that the conductive path of the entire device is controlled by the control terminal. Thus, in one embodiment of the invention, the controllable interconnect device can include first, second, and third ends. The conductive path can be between the first and second ends, and the third end can be used to control the conductive path. For example, the third control terminal can be used to control the electrical characteristics (eg, its resistance) of the conductive path. The control terminal controls the amount of current flowing between the first and second ends by changing the conductive path.

Figure 4E shows an example of a controllable interconnect device as a three-terminal device. The controllable interconnect device includes a first end 200A coupled to the X line, a second end 200B coupled to the Y line, and a third control end 200C coupled to the control circuit 240. The device 200 can have a conductive path (eg, a current path) between its first end 200A and its second end 200B. In one embodiment of the invention, the control terminal 200C can be used to control the state of the conductive path of the device 200 between the first end 200A and the second end 200B. For example, control terminal 200C can be used to control the electrical characteristics of the conductive channel. For example, control terminal 200C can be used to control the resistance (or conductivity) of the conductive path of device 200 between terminals 200A and 200B. Interconnect device 200 can be a controllable impedance device such that the impedance (e.g., resistance or conductivity) of the conductive path can be modified. The state of the resistor between the X and Y lines may correspond to the resistance of the interconnect device. For example, a relatively high resistance may correspond to a conductive connection, and a relatively low resistance may correspond to a turn-off connection.

In one embodiment of the invention, the apparatus 200 shown in FIG. 4E can be, for example, a three-terminal switch. In an embodiment of the invention, the interconnect device 200 can be a transistor (such as a MOS transistor or a bipolar transistor). In one embodiment of the invention, interconnect device 200 can be a controllable germanium rectifier (SCR). If the device 200 is a MOS transistor, the first end 200A can be the source (or drain) of the transistor, and the second end 200B can be the drain (or source) of the transistor. The third control terminal 200C can be the gate of the transistor. Figure 4A shows an example of the controllable interconnect device being an NMOS transistor.

It will be appreciated that in one or more embodiments of the invention, separate control terminals are not required to control the conductive pathways of the controllable interconnect device. For example, separate control terminals are not required to control certain types of energy (eg, thermal, electrical, mechanical, optical, or electromagnetic energy).

In NMOS transistor QI and PMOS transistor, the gate terminal is an example of a control terminal that can be used to control the current between the source terminal and the drain terminal. Specifically, in each of the programmable connections, a controllable interconnect device can have a first end coupled to a corresponding X line and a second end coupled to a corresponding Y line, wherein The current between the first and second ends is controlled.

It should be noted that the controllable interconnect device can be a circuit that includes one or more electrical components. The circuit can include two or more electrical components that are electrically coupled to each other.

Another embodiment of the invention is shown in Figure 4B. In this embodiment, the voltage regulator 260 is coupled to the control circuit 240. The voltage regulator receives the power supply voltage Vcc as an input and provides a regulated voltage Vcc (REG) to the control circuit as an output. The regulator can be implemented, for example, by using a (Widlar) Band-gap regulator (or other alternative familiar to those skilled in the art). The output voltage can be independent of fluctuations in the power supply and the controllable TC (temperature coefficient). The output voltage versus temperature can be suitably programmed using a familiar technique (optimizing both voltage and TC, which is designed for general use and stylization) to conform to appropriate control circuitry 240. demand.

For control circuits that use chalcogenide materials in memory elements and/or selection devices (eg, threshold switching elements), proper operation is maintained depending on the particular voltage applied across the memory cells and/or the threshold switching elements. For example, below the threshold voltage. The voltage regulator is useful to ensure that the voltage applied across the chalcogenide device is regulated. A regulated voltage (e.g., Vcc (REG)) can be used in series between the voltage supply and the component or memory of the control circuit 240.

Likewise, a voltage regulator can be used to provide a reduced and controlled voltage to the logic of the PLA (or FPLA or FPGA). That is, the logic drive and receive signals from the X-ray and/or Y-line can be driven by Vcc (REG) from the voltage regulator, which can be a reduced level (relative to Vcc to the wafer).

Another embodiment of the present invention is shown in FIG. 4C in which charge pump 280 is coupled to control circuit 240. Likewise, a pumped voltage can be supplied to the logic. The charge pump receives a voltage such as Vcc as an input and provides a pumped voltage Vpumped (which is greater than Vcc) as an output. The resulting voltage delivered to control circuit 240 or logic can also be adjusted, and one or both of them can be pumped, regulated, or conditioned pumped (regulated pumped) voltage driven.

Another embodiment of the present invention is shown in FIG. 4D, in which charge pump 280 provides a voltage Vpumped to regulator 260, which provides an adjusted pumped voltage Vpumped (REG) to control circuit 240. Likewise, a pumped and/or regulated voltage can be provided to the logic. The charge pump is useful when the required voltage is high compared to the voltage that can be supplied by the wafer voltage supply. For example, during the stylized control circuit 240, it is desirable to be able to use a stylized voltage that is higher than the normal operating voltage.

Likewise, it is also desirable to be able to couple the voltage applied as the output of control circuit 240 to the X and/or Y line that is greater than the voltage supplied to drive the logic gate. For example, if the high level of the gate from the control circuit 240 to the QI is Vcc (logic) + Vt (transistor QI) + Von (transistor QI), then the transistor QI will be turned on (for the NMOS, the gate voltage When high, for the driver in the X and / or Y line, the QI transistor can be turned on Q1 in the full logic swing range.

An embodiment of the programmable connection of the present invention is shown in Figure 5A. Figure 5A shows an NMOS transistor QI coupled between an X line and a Y line. The X and Y lines can belong to the first programmable matrix array.

Referring to the embodiment of the present invention shown in FIG. 5A, the control circuit 240 includes a CY line, a CX line, and a control unit 242 coupled between a CY line and a CX line. The control unit 242 includes a memory element M and a threshold switching element T, and the memory element M is connected in series with the threshold switching element T. The line CZ is coupled between the node NZ and the gate of the transistor QI. The memory element M is coupled between the CY line and the node NZ. The threshold switching element T is coupled between the node NZ and the CY line. The memory element and the threshold switching element are opposite in position such that the memory element is coupled between the node NZ and the CX line, and the threshold switching element is coupled between the CY line and the node NZ. In one or more other embodiments, the CX and CY lines are interchangeable. (In an additional embodiment of the invention, it will be appreciated that the threshold switching element T may be replaced by a transistor or a diode. The transistor may be a MOS transistor. Likewise, an additional embodiment of the invention It can be understood that the memory element M can be replaced by a transistor or a diode. The transistor can be a MOS transistor.

The phase change memory element M comprises a phase change memory material. The memory component can further include one or more electrodes for providing an electrical signal to the memory material. The phase change material can be any phase change material that is familiar to those skilled in the art. The phase change material can be a chalcogenide material. One example of a chalcogenide material that can be used as a phase change material is Ge ₂ Sb ₂ Te ₅ . This alloy is also known as GST 225. Other examples of phase change materials that can be used as memory materials are discussed in U.S. Patent Nos. 5,166,758, 5,296,716, 5,341,328, 5,359,205, 5,406,509, 5,414,271, 5,534,711, 5,534,712, 5,536,947, 5,596,522, 5,825,046, and 6,087,674, all of which will It is incorporated herein by reference.

It should be noted that for the various embodiments described herein, additional embodiments of the present invention may be implemented by any type of programmable resistive memory element (which is between at least one of the first and second resistive states) The stylized, whether volatile or non-volatile, is formed in place of the phase change memory element M. Likewise, the phase change material can be replaced by another type of programmable resistive material that is not a phase change material.

The threshold switching element T includes a threshold switching material. The threshold switching element T can further include one or more electrodes for providing an electrical signal to the threshold switching material.

In one or more embodiments of the invention, the threshold switching material can be a chalcogenide material. Any chalcogenide threshold switching material can be used in the present invention. One or more chalcogenide thresholding materials cannot be readily crystallized (possibly with some crystallization) with additional energy, while one or more chalcogenide thresholding materials cannot be completely crystallized with additional energy. In one or more embodiments of the invention, the threshold switching material (eg, chalcogenide threshold switching material) can be a substantially non-phase change material.

One example of a chalcogenide alloy that can be used as a threshold switching material is Si ₁₄ Te ₃₉ As ₃₇ Ge ₉ X ₁ , where X can be element In or element P. In one or more embodiments of the invention, the threshold switching material can be an S-type threshold switching material. In one or more embodiments of the invention, the S-type material can be a chalcogenide material. In one or more embodiments of the invention, the S-type material may not be a chalcogenide material. The threshold switching material can be in series with the memory material in the CY line and the CX line.

The threshold switching element T is an example of an access device. In other embodiments of the invention, the threshold switching element T can be replaced by another form of access device (e.g., a transistor or a diode). Similarly, in other embodiments of the invention, the threshold switching element T can be replaced by some other form of active device.

The order in which the transistors QI to X and the Y line are coupled may be reversed. The gate of the transistor QI is coupled to the node NZ between the memory element M and the threshold switching element T. The order of the memory element M and the threshold switching element T can be reversed, or the order of the lines CX and CY can be reversed. In the embodiment shown, the line CY is coupled to a fixed voltage, to a ground potential, to an unregulated voltage (eg, an unregulated power supply), or to a regulated voltage (eg, via Adjusted power supply) is possible. Line CX can be coupled to a fixed voltage, to a ground potential, to an unregulated voltage (eg, an unregulated power supply), or to a regulated voltage (eg, a regulated power supply).

It should be noted that the pair (X, Y) may belong to a first matrix array (such as shown in Figure 3). The pair (CX, CY) may belong to a separate second matrix array that is part of the control circuit 240. The CX and CY lines can be used to program control unit 242 such that the output control signal is generated on line CZ, which controls the state of the controllable switching element between the individual interconnect X and Y lines. Therefore, the pair (CX, CY) can belong to one of the larger CX-CY matrix arrays (as shown in Figure 15A). Additional examples of CX-CY arrays are shown in Figures 30A, 30B, and 30C. Figure 15A shows a control circuit 240 comprising a CX-CY matrix array having four CX lines CX1 through CX4 and four CY lines CY1 through CY4. In one or more embodiments of the invention, there is at least one CX line and at least one CY line. In one or more embodiments of the invention, there are a plurality of CX lines and a plurality of CY lines. In an embodiment of the invention, the CX line can be coupled to a low voltage or ground. In one embodiment of the invention, the CY line can be coupled to a low voltage or ground. In one or more embodiments of the invention, the CX line and the CY line may be address lines.

In the embodiment shown in Figure 15A, the CX lines are oriented in a first direction and the CY lines are oriented in a second direction (different from the first direction). The CX line can be perpendicular to the CY line. The CX line can intersect the CY line at some non-vertical angles. In one or more embodiments, the CX line meets the CY line (not above or below). Likewise, in one or more embodiments, the CX line does not have to intersect the CY line. For example, a CX line can be adjacent to only one CY line (which is possible when the substrate is at the same height). In the embodiment shown, one or more CX lines meet (above or below) one or more CY lines. In the embodiment shown in FIG. 15A, each memory element M is coupled in series with a corresponding threshold switcher T. The control node NZ can be coupled to an individual control terminal of a controllable switch (coupled between an X line and a Y line).

An embodiment of the invention showing a possible relationship between the control CX-CY matrix and the X-Y matrix of controllable switching elements is shown in Figure 15B. Figure 15B shows a four-by-four matrix control unit 242 (with CX-CY line). Each control unit 242 provides a corresponding output line A to P. Each of the output lines A to P is coupled to a corresponding gate A to P of a corresponding transistor QI (which is coupled between the corresponding X and Y lines of the X-Y matrix). The size of the X-Y array and the size of the CX-CY array are not limited to any particular size.

In the embodiment of control unit 240 shown in FIG. 15A, the control circuit is in the form of an array of control units 242. Each control unit 242 includes a memory element M in series with a threshold switching element T. The threshold switching element can also be referred to as a threshold switcher. In one or more embodiments of the invention, the threshold switching element T can be replaced by another type of access device (such as a transistor or a diode) or a series transistor or diode switching element T. . Moreover, in one or more embodiments of the invention, a memory element coupled between the CX line and the CY line can be used without an access device to form the control unit. In one or more embodiments, the memory element M can be connected in series with the switching element T. In one or more embodiments, the memory element M can be connected in series with the switching element T and a controllable current source, such as a transistor (for example, a p-channel transistor whose gate is controlled by a current mirror or regulator) control). In these embodiments, the transistors may be connected in series and/or in parallel with the memory elements and/or the threshold switching elements.

Referring to the embodiment illustrated in Figure 15B, it should be noted that the X-Y matrix 125 in conjunction with the control unit 240 can be used to form a stylable array, such as the array 100 shown in FIG. Similarly, the X-Y matrix 125 in conjunction with the control unit 240 can be used with programmable logic devices.

In one or more embodiments of the invention, the control signals are available from nodes other than node NZ. In one or more embodiments, additional control signals can control additional transistors that are coupled across the X and Y lines.

Referring again to FIG. 5A, the control node NZ is coupled to the gate of the transistor QI via a wire CZ. Therefore, the voltage at node NZ is applied to the gate of transistor QI and controls the state of the transistor, thus controlling the resistance of QI from source to drain. The voltage at node NZ is represented by Vnz. As shown in the embodiment, the voltage at node NZ is applied to the gate of transistor QI, and the voltage at node NZ can also be represented by Vgate.

When Vnz is high, the NMOS transistor QI is turned on, thereby generating CLOSED connected between the X line and the Y line. When Vnz is low, the NMOS transistor QI is turned off, thereby causing OPEN to be connected between the X line and the Y line. If a PMOS transistor is used instead of an NMOS as the junction-connecting transistor, the PMOS transistor will turn on when Vnz is low, and the PMOS transistor will turn off (OPEN connection) when Vnz is high.

It should be noted that the transistor QI can be replaced by another type of controllable interconnect device. In one embodiment of the invention, the controllable interconnection means preferably includes first and second ends whereby the current path within the apparatus is between the first and second ends. The interconnect device can also include a control terminal that controls the current path (e.g., the impedance of the channel) such that more or less current can flow between the first and second ends. Therefore, the first end of the interconnect device can be coupled to the Y line (or X line), the second end of the interconnect device can be coupled to the X line (or Y line), and the control end of the interconnect device can be Is coupled to node NZ. It should be noted that one of the interconnectable devices that can be used (instead of MOS transistors) is a bipolar transistor or an SCR device (controllable 矽 rectifier).

The memory material of the memory device M or the selection device T may be connected in series with one or more breakdown layers. It can be done in several different ways. The memory element M can be formed with (or not) a breakdown layer. Similarly, the threshold switching element T can be formed (or not) with a breakdown layer. When the memory component is formed as a collapsed layer, the collapsed layer is preferably connected in series with the memory material. Similarly, when the threshold switcher is formed with a collapse layer, the collapse layer is preferably connected in series with the threshold switching material.

Figures 5B through 5K show additional embodiments of the control circuit of the present invention. FIG. 5B shows an embodiment of the control circuit 240 of the present invention including a control unit 242 that includes a memory element MW (not formed by a breakdown layer) and a threshold switcher TW (not formed by a collapse layer). Figure 5C shows an embodiment of the control circuit 240 of the present invention comprising a control unit 242 comprising a memory element MB (formed as a collapse layer) and a threshold switcher TW (not formed by a collapse layer). Figure 5D shows an embodiment of the control circuit 240 of the present invention comprising a control unit 242 comprising a memory element MW (not formed by a collapse layer) and a threshold switcher TB (formed by a collapse layer). Figure 5E shows an embodiment of the control circuit 240 of the present invention comprising a control unit 242 comprising a memory element MB (formed as a collapse layer) and a threshold switcher TB (formed as a collapse layer).

As used herein, the memory component "M" may (or may not) contain a crash layer, the memory component "MW" does not include a crash layer, and the memory component "MB" contains a crash layer. Similarly, the threshold switcher "T" may (or may not) contain the crash layer, the threshold switcher "TW" does not contain the crash layer, and the threshold switcher "TB" contains the crash layer.

Thus, the breakdown layer can be connected in series with the memory material and/or the series of the threshold material by incorporating the collapse layer into the memory element and/or the threshold switch. This can be done, for example, in the electrode or in series with the electrode as an additional layer. Alternatively, it is possible to introduce the breakdown layer into the control circuit 240 by adding separate crash devices (whose series memory elements and/or threshold switches) (e.g., anti-fuse). FIG. 5F shows an embodiment of the control circuit 240 of the present invention including the control unit 242. The control unit 242 includes a memory element MW (without a collapse layer) of the crash device B connected in series between the CY line and the node NZ. The control unit 242 further includes a threshold switcher TW (without a collapse layer) coupled between the node NZ and the CX line. Figure 5G shows an embodiment of the control circuit 240 of the present invention comprising a control unit 242 comprising a crash device B in series with a threshold switch TW (without a collapse layer) between the node NZ and the CX line. The same control unit 242 further includes a memory element MW (without a collapse layer) coupled between the CY line and the node NZ. FIG. 5H shows an embodiment of the control circuit 240 of the present invention including the control unit 242. The control unit 242 includes a crash device B in which the memory element MW is connected in series between the CY line and the node NZ. The same control unit 242 further comprises another crash device B of the serial threshold switch TW. In the various embodiments of the invention shown in Figures 5F, 5G, and 5H, the memory element MW (without the collapse layer) can be replaced by a threshold switch TB (with a collapse layer). Similarly, the threshold switcher TW (without a crash layer) can be replaced by a threshold switcher TB (with a crash layer).

The collapse layer can be any dielectric or insulating material known in the art. For example, the dielectric material can comprise any oxide, nitride, oxynitride, or a combination thereof. The dielectric material can be an oxide of aluminum or an oxide of cerium. The dielectric material can be a nitride of aluminum or a nitride of germanium. Examples include niobium nitride, SiO2, Si3O4, and Al2O3. In one embodiment, the collapse layer may be formed of a material comprising the elements bismuth, nitrogen, and hydrogen. In another embodiment, the collapse layer may comprise a material comprising about 30-40% atomic percent, 40-50% nitrogen, and more than 30% hydrogen. The collapse layer can comprise an amorphous shape. For example, an amorphous crucible collapse layer can be used for the antifuse.

In the present invention, the thickness of the collapse layer is not limited to any particular thickness. In one or more embodiments, the thickness of the collapsed layer is between about 10 angstroms (Angstroms) and 200 angstroms as the desired support voltage is required to dig through the collapsed layer. In one or more embodiments, the thickness of the collapse layer is between about 20 angstroms and 100 angstroms. In one or more embodiments, the thickness of the collapse layer is between about 40 angstroms and 60 angstroms. In one or more embodiments, the collapsed layer has a thickness of about 50 angstroms. The thickness used is varied according to the situation: the choice of operating power supply range and limits for preventing transient currents, which is desirable before the collapse layer or selection device is triggered.

The material used for the collapse layer and the thickness of the collapse layer may be selected such that the voltage across the collapse layer is about 6 volts or less (the voltage for the power supply is preferably 4 volts or less). The material used for the collapsed layer and the thickness of the collapsed layer can be selected such that after collapse of the collapsed layer (cracking into a short or low resistance), the breakdown layer has a resistance of about 2000 ohms or less.

The collapse layer can have a high melting point and low chemical reactivity. The resistivity of the collapsed layer can be between about 1012 and 1017 ohm-cm. Niobium nitride is preferably used to improve the integrity. For example, Al-20 of 20-40 angstroms can be used due to its higher melting point and offset in reduced device characteristics (eg, reset current). The diluted HF liquid can desirably remove the original oxide depending on whether it is done in the case of donein-situ or deposition between the layers. Depending on the desired breakdown voltage, those of ordinary skill in the art can design thicknesses and materials. Desirable variations of this layer of material and adjacent electrodes for different applications will be apparent to those of ordinary skill in the art. Conversely, a fuse can be used in place of a collapsed layer or antifuse, using techniques familiar to those of ordinary skill in the art.

Referring to the embodiment shown in Figures 5A through 5H, the collapse layer can be used to limit (almost eliminate) leakage through or beyond control unit 242 before any collapse layer collapses. If there is a crash layer (and before the crash layer collapses), the voltage of the node NZ, the state of the transistor QI, and the X-ray can be determined by appropriately placing the breakdown layer (relative to the CY line, the CX line, and the node NZ). The state of the connection with the Y line. For example, as shown in Figures 5C and 5F, the collapse layer can be placed between the nodes NZ and CY lines. As shown in Figures 5D and 5G, the collapse layer can be placed between the node NZ and the CX line.

In an example, assume that, as in Figure 5C, the collapse layer is between node NZ and the CY line. In one embodiment of operating the control circuit, the CX line can be a high voltage during normal logic operation and the CY line can be low voltage (or ground). If this is the case, the majority of the voltage across the collapsed layer will drop, causing the voltage at node NZ to be high and the transistor QI to be normally turned on so that when the collapsed layer is in an unfrozen state, between the X and Y lines The connection maintains CLOSED.

As another example, assume that as in Figure 5D, the collapse layer is between the node NZ and the CX line. Similarly, in one embodiment of operating the control circuit, the CX line can remain high during normal logic operation while the CY line can remain low (or ground) during normal logic operation. If this is the case, the majority of the voltage across the collapsed layer will drop such that the voltage Vnz at node NZ should be normally low and the transistor QI should be normally turned off so that when the crash layer is in an unfailed state, The connection between the Y line and the X line maintains OPEN.

Of course, it will be understood that in one or more embodiments of the operational control circuit of the present invention, the voltage applied to the CX line and the CY line is reversed such that the CX line can be low voltage (or ground) during normal logic operation. The CY line can be high voltage during normal logic operation. In this case, when the collapse layer is between NZ and CY (as shown in Figure 5C), the voltage at node NZ can be a low voltage (and the connection OPEN). Similarly, when the collapse layer is between NZ and CX (as shown in Figure 5D), the voltage at node NZ can be a high voltage (and the connection CLOSED between X and Y).

Thus, the selection of the connection between the X and Y lines with normal OPEN or normal CLOSED can be determined by placing the collapse layer relative to the node NZ, CX line, and CY line. Similarly, the choice of a connection such as normal OPEN or normal CLOSED can be made by applying an appropriate voltage to the CX and CY lines during normal logic operation. For a particular application, it is desirable that the transistor QI can be normally turned off, while the connection between the X and Y lines can be normally OPEN.

Referring to the embodiment of the control circuit shown in FIG. 5A, if there is no breakdown layer or if all the breakdown layers have collapsed, the voltage at the node NZ, the state of the transistor QI, and the connection between the X-ray and the Y-line. The state can be controlled by staging the memory element M between its low resistance set state and its high resistance reset state.

Referring to the embodiment shown in FIG. 5A, for this case, as an example, the crash layer is not added, or all the added crash layers have collapsed. In this case, the voltage at node NZ can be controlled by programming the memory element M back and forth between its low resistance set state (eg, set state) and its high resistance reset state (eg, reset state). An example of a method of staging memory component M between its set and reset states is to apply a programmed voltage Vp across the control lines (CX and CY) of the selected target control bit to be programmed. The stylized voltage Vp should be sufficient to trigger the threshold switching element T to its conducting state. A suitable current can be applied via the memory element M for programming the memory element M to a selected state. For example, the state of the memory component can be controlled by controlling the intensity and/or duration and/or trailing edge of the applied current pulse.

The programmable voltage Vp can be selected to be greater than the sum of the threshold voltage of the threshold switching element T and the threshold voltage of the memory element M. Thus, as an example, Vp can be selected to be greater than Vth(T) + Vth(M), where Vth(M) is the threshold voltage of the memory component in its high resistance or reset state. Vp can be greater than the general logic operating voltage Vcc such that a charge pump can be used to generate a voltage Vp that is higher than Vcc.

When, for example, no crash layer or all crash layers have collapsed, there are many different ways of operating the control circuit 240 shown in Figure 5A.

In one or more embodiments of the invention, the resistance of the threshold switching element in its off state (without any collapsed layers) may be greater than the resistance of the memory element in its reset state (without any collapsed layers). For example, in one or more embodiments of the invention, the resistance of the threshold switching element in its off state (without any collapsed layers) may be approximately 10 to 20 times greater than the memory element in its reset state ( There is no breakdown layer of resistance.

During normal logic operation (eg, when the memory component is not programmed), the threshold voltage Vth(T) of the threshold switching element can be designed to be less than the voltage difference between the CX line and the CY line. In addition, during normal logic operation (where Vth(T) is the threshold voltage of the threshold switching element and Vth(M) is the threshold voltage of the memory element in its high resistance or reset state), Vth(T)+Vth The sum of (M) can be designed to be larger than the voltage difference between the CX line and the CY line. These operating conditions can be expressed by the following equation: Vth(T)<| VCX-VCY |<Vth(T)+Vth(M)

Where | VCX-VCY | represents the magnitude of the voltage difference between the voltage on the CX line and the voltage on the CY line during normal logic operation.

In one example, during normal logic operation, the CX line can be held at a voltage of about Vcc + Vh(T) + Vt (n channel), where Vh(T) is the holding voltage of the threshold switching element T, and Vt (n channel) is The threshold voltage of the n-channel transistor QI. The CY line can be maintained at approximately zero voltage (eg, ground). Therefore, the voltage difference between the CY and CX lines can be expressed as Vcc + Vh(T) + Vt (n channels). That is: | VCX-VCY |=Vcc+Vh(T)+Vt(n channel)

Therefore, the operating condition (1) can be expressed as: (1') Vth (T) < Vcc + Vh (T) + Vt (n channel) < Vth (T) + Vth (M)

Where Vth(T) is the threshold voltage of the threshold switching element and Vth(M) is the threshold voltage of the memory element in its high resistance or reset state.

If the operating condition (1') is satisfied, then the voltage across the CX and CY lines (Vcc + Vh(T) + Vt (n channel)) should be sufficient to turn on the threshold switching element when the memory element is in its set state. T. In addition, the voltage at node NZ should be approximately Vcc + Vt (n channels). This voltage should be sufficient to keep the transistor QI conducting (and the connection CLOSED between the X and Y lines) during full logic swing.

However, when the memory element is in its reset state, the magnitude of the voltage across the CX and CY lines (less than Vth(T) + Vth(M)) is insufficient to turn on the threshold switching element T. Therefore, the threshold switching element T is turned off so that its resistance is high. In this embodiment, since the resistance of the threshold switching element T in its off state is assumed to be much larger than the resistance of the memory element M in its reset state, most of the voltage drop is over the threshold. The component T is switched and the voltage at node NZ is low (eg, close to 0V or ground). In this case, the transistor QI is turned off and the connection between the X and Y lines is OPEN.

In another embodiment of the present invention, it should be understood that the resistance of the threshold switching element in its off state (no collapse layer) can be designed to be smaller than the resistance of the memory element in its reset state (no collapse layer) ). As an example, it should be understood that the resistance of the threshold switching element in its off state (no collapse layer) can be designed to be about 100K ohms (ie, 100000 ohms), and the resistance of the memory component in its reset state can be designed. It is about 10 M ohms (ie, 10,000,000 ohms), and the resistance of the memory element in its set state can be designed to be about 10 K ohms (ie, 10,000 ohms). Referring again to the embodiment shown in Figure 5A (and assuming, for example, that there is no crash layer or all crash layers have crashed), there may be one or more methods of operation. As an example, during normal logic operation, the threshold voltage Vth(T) can be designed to be greater than the voltage difference between the CX line and the CY line. That is, it can have the following operating conditions: Vth(T)>| VCX-VCY |

If the voltage on the CX and CY lines satisfies the operating condition (3), the threshold switching element will be in its high resistance off state regardless of the state of the memory element M. In one embodiment of the method of operating the control circuit, a high voltage can be applied to the CX line and a low voltage (or ground) can be applied to the CY line. When the memory component is in its reset state, most of the voltage drops across the memory component M (since in this embodiment, it is assumed that the reset resistance of the memory component is designed to be higher than the threshold switching component. Shutdown state resistance). Therefore, the voltage at the node NZ is high, the transistor QI is turned on, and the connection between the X and Y lines is CLOSED. However, when the memory component is in its set state, most of the voltage drops across the threshold switching element T, so that the voltage at node NZ is low, transistor QI is off, and between X and Y lines. The connection is OPEN.

Similarly, the memory elements can be programmed by applying a stylized voltage Vp across the lines. The size of the stylized voltage Vp can be greater than Vth(M) + Vth(T).

It should be noted that the above-described operational methods and the operational conditions as indicated by relationships (1), (1'), (2), and (3) are merely examples of operational methods and examples of operational conditions. Of course, there may be other operating methods and operating conditions.

As noted above, it should be noted that in one embodiment of the invention, the resistance of the threshold switching element in its off state (without any collapsed layer) may be greater than the memory element in its reset state (without any collapse layer). )The resistance. If this is the case, it is possible to operate the control circuit 240 shown in Figure 5A such that during normal logic operating conditions, the memory component M is in its set state (again assuming no crash layers or all crash layers have been When the crash occurs, the threshold switching element T is turned on. This occurs when, for example, during normal logic operating conditions, the magnitude of the voltage across the CX and CY lines is greater than the threshold voltage of the memory element M (ie, when |VCX-VCY |>Vth(T)) situation. When the threshold switching element T is turned on, it is desirable to limit the current flowing through the series connection of the threshold switcher T and the memory element M. In one or more embodiments of the invention, it is possible to reduce this current by increasing the current limiting transistor in series with the threshold switcher T and the memory element M. One such embodiment of the invention is shown in Figure 5K, in which transistor Q19 is connected in series with memory element M in series between node NZ and line CY. FIG. 5K shows an embodiment of the control circuit 240 of the present invention. The control circuit 240 includes a control unit 242 that includes a transistor Q19, a memory element M, and a threshold switching element T. The transistor Q19, the memory element M, and the threshold switching element T are all coupled in series between the CX line and the CY line. The gate of the transistor Q19 is coupled to the bias voltage CTB.

Transistor Q19 limits the current flowing through memory element M (except during stylization). This can be done by setting the gate of transistor Q19 such that the transistor is only slightly turned on during normal logic operation. During stylization, the gate can be set such that transistor Q19 can be fully turned on to properly increase the current that is effective for staging memory element M. After the stylization is completed, the transistor can be returned to a slight turn-on.

Another embodiment of the invention is shown in Figure 5L. In the embodiment shown in FIG. 5L, the control unit 242 includes a transistor Q19, a memory element M, and a threshold switching element T. The memory element M and the threshold switching element T are coupled in series between the line CX and the node NZ, and the transistor Q19 is coupled between the node NZ and the line CY. The bias voltage CTB is coupled to the gate of the transistor Q19. In the embodiment shown in FIG. 5L, when the memory element M is programmed to its low resistance setting state, the threshold switching element T can be turned on and can be connected to the transistor Q19 (which can be slightly turned on). The current is limited, and the voltage at node NZ is pulled to the voltage on line CX. If the memory element M is programmed to its high resistance reset state, the unrestricted high resistance reset memory element M connected in series with the unthresholed high resistance threshold switching element may have a current limit The transistor Q19 (which is slightly turned on) has less leakage so that the voltage at node NZ can be closer to the voltage of line CY. Therefore, by staging the memory element M, the voltage applied to the gate of the transistor QI can be controlled, and when the memory element M is in its low resistance setting state, it can be limited by the transistor Q19. Leaked.

The same operations and results are shown in a further embodiment of the invention, as shown in Figure 5M. Here, the threshold switching element T in FIG. 5L is deleted, so that the control unit 242 includes the transistor Q19 of the serial memory element M. The conceptual operation is the same as that of the above 5L, but the leakage through the memory element M can be greater than that without the threshold switching element T, so that when the transistor Q19 is slightly turned on, the transistor Q19 is required during normal operation. Drive more leakage current for a good margin. Similarly (because the threshold switching element T does not have the serial memory element M as shown in FIG. 5L), in order to ensure that the voltage across the memory element M remains below its threshold voltage Vth(M) (except during stylization) (To ensure that the memory component that is programmed to its reset state remains in its reset state), the magnitude of the voltage applied between line CX and line CY can be limited to a lower voltage (relative to the 5L) The embodiment of the figure) wherein the threshold switcher T is also connected in series with the memory element M.

Another embodiment of the present invention is shown in Figure 5N, in which the memory element M in Figure 5M is replaced by a threshold switching element T. In this embodiment of the invention, control unit 242 includes a transistor Q19 that is coupled in series with switching element T. The transistor Q19 is coupled between the node NZ and the line CY. The gate of the transistor Q19 is coupled to the bias voltage CTB. The gate of the bias transistor Q19 can be biased such that the transistor Q19 is slightly turned on for a general logic operating system. If the threshold switching element T is in its untriggered high resistance turn-off state, then there will be sufficient A voltage pulled up by node NZ.

During stylization, the gate of transistor Q19 can be set to a voltage that can more fully conduct the crystal Q19 to ensure that the threshold current Ith(T) of the threshold switching element is exceeded during the stylization. The voltage between lines CY and CX during stylization may be increased to ensure that more than a threshold voltage Vth(T) crosses the threshold switching element T at least briefly (e.g., more than about 10 nsec (nanosecond)). Exceeding the threshold voltage Vth(T) will trigger the threshold switching element T to its lower resistance conducting state such that the voltage at node NZ will be closer to the voltage of line CX (less close to the voltage of line CY). To return the state of the threshold switching element T from its conducting state to its high resistance off state (more voltage drops across the device), the voltage between the CX and CY lines can be reduced to near zero volts (so that, for example, less than The holding current Ih(T) flowing through the threshold switching element. Alternatively, the power supply can be turned off and then turned on.

When the power is restored after the power is turned off or the battery is charged, the resulting control architecture bit can be reloaded.

In order to program the threshold switching element T into its conducting state after the system is powered up, the voltage difference between the lines CX and CY can be increased to exceed the magnitude of the voltage difference used for normal operation. If additional current is required (other than the current normally supplied by transistor Q19) to trigger the threshold switching element T to the conducting state, the bias voltage on the gate of Q19 can be increased to reduce the transistor Q19 from the source to the drain. The resistance.

For the embodiment of the control circuit 240 shown in FIG. 5N, if the threshold switching element T is not triggered after applying a higher voltage between CX and CY after power-up, the threshold switching element T remains in its high resistance off state, and transistor Q19 pulls the voltage at node NZ to a voltage close to line CY. If the threshold switching element T is triggered by stylization after startup, the threshold switching element T remains in its high resistance off state, and the threshold switcher T pulls the voltage of the node NZ close to the line CX. Voltage. The voltage of the node NZ and the state of the transistor QI can be controlled by the state of the switching element T (on or off).

In the various embodiments shown in the 5K, 5L, 5M, and 5N diagrams, a collapse layer can be connected in series with the memory element M and/or the threshold switching element T and/or the transistor Q19. Similarly, a collapse layer can be incorporated into memory element M and/or threshold switching element T and/or transistor Q19. A crash device (such as an anti-fuse) or a crash layer can reduce leakage until the device or layer collapses.

For one or more of the embodiments shown in the 5K, 5L, 5M, 5N diagrams, the control circuit 240 can include a plurality of control units 242 formed in an array, as shown in FIG. 30A. The bias voltages CTB applied to the respective gates of the corresponding transistors Q19 can be combined to use the wafer area more efficiently.

In one or more embodiments of the invention, the transistor can be connected in series with a memory element or a threshold switching element. Figure 5I shows an embodiment of the invention comprising a control unit 242 comprising a memory element M in parallel with a transistor Q17. The control unit 242 further includes a threshold switching element T, and the threshold switching element T is connected in series with the parallel connection of the memory element M and the transistor Q17. In another embodiment of the invention, the PMOS transistor can be replaced by an NMOS transistor or some other controllable interconnect device. The current flowing through the transistor Q17 can be set such that the total current flowing through the parallel connection of the transistor Q17 and the memory element M is greater than the holding current Ih(T) of the threshold switching element T. Then, once turned on, the threshold switching element T can remain turned on until the power supply is removed and/or the current drops below the holding current Ih(T) of the threshold switching element.

With the transistor in parallel with the memory element, the threshold switching element T can be turned on after the magnitude of the voltage between the cycles CX and CY becomes greater than the threshold voltage Vth(T). If the threshold voltage Vth(T) is less than the normal operating voltage and the memory element M is in its low resistance setting state, the threshold switching element T will switch to conduction at startup. Otherwise, the voltage between CX and CY can be increased during stylization.

The use of a transistor of a parallel memory element (as shown in Figure 5I) helps to reduce the current flowing through the memory element when the threshold switching element T is turned on and the memory element M is in the set state. When the memory component is programmed, the gate of transistor Q17 can be taken to a higher voltage, thereby reducing the current flowing through transistor Q17 and allowing higher currents (which are required by the program memory component) to flow through Memory element M. The gate can be set to a higher voltage (e.g., near the threshold voltage of the transistor) such that the current flowing through the memory element M is sufficient to remain above Ih(T) and keep the threshold switching element T conducting. In another embodiment of the invention, the transistors can be connected in parallel with the switching elements such that the parallel connections are more leaky (compared to the series coupled memory elements of their reset states). This example is shown in Figure 5J, in which transistor Q18 is coupled in parallel to the threshold switching element T. In the embodiment of the present invention shown in FIG. 5J, the control circuit 240 includes a control unit 242. The control unit 242 includes a memory element M, a threshold switching element T, and a transistor Q18. The transistor Q18 is connected in parallel with the switching element T. The memory element M is connected in series with the parallel connection of the threshold switching element T and the transistor Q18. In another embodiment of the invention, the NMOS transistor Q18 can be replaced by a PMOS transistor.

With a transistor (eg, transistor Q18) connected in parallel with the switching element T, the threshold switching element T can be bypassed and the memory element M can be directly programmed (eg by changing the voltage on the gate) The crystal is energized Q18), and the control of the gate of Q18 can include a decoder.

If the voltage to CX increases, the voltage drop from the gate of transistor QI to the source or drain of transistor QI can be accommodated, such that transistor QI can tend to remain conductive (over line X and / or a wide range of voltages of Y). Furthermore, depending on whether the OPEN state or the CLOSED state is more frequent for the customer's pattern between the C and Y lines, the voltage applied to lines CX and CY can be reversed to reduce leakage in control circuit 240. Similarly, if the threshold switching element T is connected to a negative voltage, by making the voltage on the line CY negative (instead of grounding), the voltage margin of the transistor QI is turned off (when the voltage of the node NZ is normal) When the operation period is low).

In various embodiments of the invention shown in FIG. 5I, or 5J, a crash device and memory element M and/or a threshold switching element T and/or a transistor (eg, a transistor source or drain) may be used. ) in series. Similarly, a collapse layer can be incorporated into the memory element M and/or the threshold switching element T and/or the transistor (e.g., the contact transistor source or drain).

In the various embodiments shown in Figures 5A through 5N, the order of the memory element M and the threshold switching element T (and any transistor) is interchangeable. For example, referring to FIG. 5A, the memory element M can be coupled between the nodes NZ and CX, and the threshold switching element T is coupled between the nodes NZ and CY. A change in the relative position of the memory element and the threshold switching element may require a change in the relative voltage applied to CX and CY (for proper operation of the control circuit).

Moreover, for embodiments in which the present invention includes a threshold switching element, the cyce life can be extended for the threshold switching element by: 1) providing a heat sink adjacent to the threshold switching element such that the threshold switching element During operation, the resulting thermal environment minimizes temperature rise (heating). For example, this can be achieved by using a high thermal conductivity film close to the threshold switching element layer. These films may comprise one or more groups selected from the group consisting of W, Al, and Cu. These membranes may also be used as device electrodes or (optionally) separated by a barrier membrane electrode from a threshold switching element. The barrier film of these options can be relatively thin to aid in the processing topology while minimizing thermal resistance. The operation of the threshold switching element in the bidirectional mode also improves durability. For example, at startup, the threshold switching element voltage can be reversed by temporarily reversing (but limiting current) the voltages to lines CX and CY, such that the memory elements are not reprogrammed. The threshold switching element can be triggered in both directions to further improve durability.

As described above (and as shown in Figures 15A and 15B), the control circuit can be formed as an array of control units. Another example of an array of control units 242 is shown in Figure 30A. Figure 30A shows a control circuit 240 comprising an array of three by three control units 242. Control circuit 240 includes CX control lines CX1 through CX3, CY control lines CY1 through CY3, and control unit 242. Each control unit 242 can take the form of any of the embodiments shown in Figures 5A through 5N and variations of these embodiments. Corresponding CZ output lines CZ1 to CZ9 are coupled to corresponding control units 242 of the control circuit array 242. Although shown as a three by three array, the size of the array is not limited to any particular size. For example, there may be only at least one CY line and at least one CX line. As noted above, it should be noted that there may be a plurality of CX lines and a plurality of CY lines. In one or more embodiments of the invention, the CX line and the CY line may be address lines.

Each of the output lines CZ1 to CZ9 of the control circuit 240 can be coupled to a gate of a corresponding interconnect transistor QI. Figure 30B shows a three by three array 130 of X-Y matrices having three X lines (X1 to X3) and three Y lines (Y1 to Y3). The interconnect transistor QI is coupled between the corresponding X line and the corresponding Y line. Each of the output lines CZ1 to CZ9 of the control circuit 240 provides a control signal to the corresponding input lines CZ1 to CZ9 of the gate of the corresponding interconnect transistor QI of the X-Y array 130. Figure 30C provides an example of a control circuit 240 that includes an array of control units 242, wherein each control unit 242 is a control unit of the embodiment shown in Figure 5A. The X-Y array 130 in combination with the control array shown in Figure 30B can be used in a programmable logic array.

Figures 8A through 8H show structures S1 through S8, respectively. These structures S1 through S8 are examples of structures that can be used to construct control units (e.g., as shown in Figures 5A through 5N) that incorporate phase change memory materials and/or threshold switching materials. In each of Figures 8A through 8H, layer 300 may represent a phase change material (eg, a chalcogenide phase change material) or it may represent a threshold switching material (eg, chalcogenide threshold switching material or S-type threshold switching) material). Nodes N20, N10 may represent CY and CZ lines, respectively. Alternatively, nodes N20, N10 may represent CZ and CX lines, respectively. When layer 300 represents a phase change material, then nodes N20, N10 may, for example, represent the CY line and the CZ line, respectively, as shown in Figures 5A through 5N. When layer 300 represents a threshold switching material, then nodes N20, N10 may, for example, represent CZ lines and CX lines, respectively, as shown in the examples of Figures 5A through 5N. The relative positions of the memory elements and the threshold switching elements can also be exchanged such that when layer 300 represents a threshold switching material, nodes N20, N10 can represent the CY line and the CZ line, respectively. Similarly, when layer 300 represents a memory material, nodes N20, N10 may represent CZ lines and CX lines, respectively.

In Figure 8A, structure S1 consists essentially of layer 300 coupled between nodes N10 and N20. In Figure 8B, structure S2 consists essentially of layer 300 coupled between nodes N10 and N20 (but not directly connected to each other). This embodiment further includes a first electrode (or contact layer) 310A coupled between the layer 300 and the node N10 and a second electrode (or contact layer) 310B coupled between the layer 300 and the node N20. Each of the electrodes 310A and 310B is shown as a single layer. However, each electrode may be formed in multiple layers, and each layer may comprise a plurality of sub-layers. Further, although two electrodes 310A and 310B are shown, it is possible to use only a single electrode (310A or 310B). It should be noted that the electrodes can be used in common for the common joint between the memory element and the threshold switch or collapse layer.

In general, electrodes 310A and 310B can be formed from any electrically conductive material. Examples of conductive materials include, but are not limited to, n-type doped polysilicon, p-type doped polysilicon, p-type doped strontium carbon alloy and/or mixture, titanium-tungsten, tungsten, tungsten germanide, molybdenum, Titanium nitride, titanium carbonitride, titanium aluminum nitride, titanium niobium nitride, and carbon.

In Figures 8C through 8H, structures S3 through S8 each comprise a collapse layer 380 of series layer 300. The structures S5 to S8 include a breakdown layer 380 and first and second electrodes 310A, 310B. Additional layers or electrodes may be added to each side of the collapse layer 380 and/or layer 300. It should be noted that layer 300 can be a phase change material or a threshold switching material.

Figures 8I through 8N show different embodiments of possible arrangements of vertically stacked layers, which represent a series connection of memory element M and threshold switching element T disposed between the CY line and the CX line. In the illustrated embodiment, layer CY represents the CY line, layer CX represents the CX line, layer CZ represents the CZ line, layer 300M represents the layer of phase change material, layer 300T represents the layer of the threshold switching material, and layer 380 represents the collapse layer. And layers 310A, B represent layers of electrically conductive material (which may act as electrodes or contact layers). As noted above, it should be noted that the layer 300M of phase change material may be replaced by a layer of some other type of programmable resistive material (which may not be a phase change material). In each of the examples shown in FIGS. 8I through 8N, phase change material 300M is a series of threshold switching material 300T. In the various embodiments shown in Figures 8I through 8N, additional embodiments may be formed by placing additional electrodes or contact layers directly above or below the CZ line. Each electrode and contact layer can be formed of any electrically conductive material.

In one or more embodiments of the invention, the phase change memory material or the threshold switching material may be replaced by a transistor to implement the embodiments described herein. Furthermore, the transistor can be added to a structure that already contains a phase change memory material and a threshold switching material (with or without one or more collapse layers). The transistor can be connected in series with a phase change and a threshold switching material. Alternatively, the transistor can be connected in parallel or in a phase-switching material.

Alternative embodiments of the invention are shown in Figures 6A through 6E. FIG. 6A shows an embodiment of control circuit 240 that includes a ground node, a CY line, a CX line, and a control unit 244. Control unit 244 includes a PMOS transistor Q20 that is in series with phase change memory element M. The phase change memory element M is coupled between the node NZ and the ground. The transistor Q20 is coupled between the CX line and the node NZ. The node NZ is coupled to the gate of the n-channel transistor QI, and the transistor QI is coupled between the X line and the Y line. The memory element M may (or may not) comprise a collapse layer of a series phase change memory material. In another embodiment, the ground node can be replaced by other ungrounded voltages.

In the embodiment shown in FIG. 6B, control unit 244 includes a memory element MW (without a collapse layer) and a transistor Q20. In the embodiment shown in FIG. 6C, control unit 244 includes a memory element MW (with a breakdown layer) and a transistor Q20. In the embodiment shown in FIG. 6D, control unit 244 includes a memory element MW (without a collapse layer) in series with a crash device B (eg, an anti-fuse) between ground and node NZ. The control unit 244 further includes a transistor Q20 connected in series with the memory element MW and the crash device B. The crash device B can be an anti-fuse. In Figure 6D, the crash device B can be placed between the memory component MW and ground. In the embodiment of FIG. 6E, the control unit 244 includes a memory element MW, a crash device B, and a transistor Q20. In this embodiment, the memory device MW is coupled between the ground and the control node NZ, and the crash device B is coupled in series with the transistor Q20 between the node NZ and the line CX. In another embodiment of the invention, a breakdown layer can be incorporated into the transistor, such as by bonding a breakdown layer over the contacts or within the source of the transistor Q20.

In an alternative embodiment of the invention, the transistor Q20 shown in Figures 6A through 6E may be replaced by an NMOS transistor. In addition, the ground contact GROUND can be replaced by a non-grounded voltage. In addition, the relative positions of the memory elements and the transistors Q20 are interchanged such that the memory elements are coupled between the line CX and the node NZ, and the cell system is coupled between the node NZ and ground (or other voltage).

Referring to the embodiments of FIGS. 6A to 6E, the voltage Vnz of the node NZ can be maintained normally high or normally low (by the state of the connection between the Y line and the X line by using a collapse layer or a crash device). Can be kept as normally CLOSED or normally OPEN). If a crash layer or crash device is used without crashing, the voltage Vnz of node NZ is maintained in a particular state, regardless of the state of the memory component, until the collapse layer or crash device (eg, anti-fuse) collapses (eg, by voltage) Overstress method).

As an example, referring to the embodiment shown in FIG. 6D, for general logic operation, the potential of line CX can be maintained at a positive voltage, and the potential of the CY line can be sufficiently maintained below the voltage of the CX line to maintain the transistor. The Q20 is slightly turned on. Since the crash device B is in a high-resistance non-crash state, all voltage drops between the CX line and the GROUND substantially pass over the crash device, so that as long as the crash layer remains unbroken, the voltage at the node NZ can be pulled high enough to remain The junction connects the transistor QI to conduct and the connection between the Y and the X line CLOSED regardless of the state of the memory element MW.

As shown in Fig. 6E, by placing the crash device B between the transistor Q20 and the node NZ, the voltage of the node NZ is kept low enough that the transistor QI remains off and the connection between the X and Y lines OPEN. Similarly (refer to FIG. 6D), the voltage of the node NZ can be made normally low by exchanging the transistor Q20 with the memory element MW and the crash device B connected in series and making the Q20 an N-channel device (interconnected power) The crystal QI is turned off and the connection between the lines X and Y is OPEN). In this case, as long as the crash layer does not collapse, the transistor QI will be off and the connection between lines X and Y will be OPEN.

Referring again to FIG. 6D, after the crash device B collapses, the voltage of the node NZ can then be controlled by programming the memory element MW back and forth between its reset and set states. When the memory element MW is in its low resistance setting state, since the unprogrammed bias current flowing through the transistor Q20 is weak, the voltage of the node NZ is pulled low. By turning off the transistor QI, this results in an OPEN connection between the Y line and the X line. If the memory element MW is programmed to its high resistance state, the bias current flowing through the transistor Q20 pulls the voltage of the node NZ high and creates a CLOSED connection between the Y line and the X line.

The bias current flowing through transistor Q20 can be adjusted by changing the magnitude of transistor Q20 and the bias voltage between lines CY and CX (except during the stylized mode). The bias current can be adjusted to: if the memory component M is in its high resistance reset state, it can pull the voltage of the node NZ high enough to conduct the crystal Q20; and when the memory component is tied to its low resistance When the state is set, it can pull the voltage of the node NZ low enough to turn off the transistor QI. If desired, the ground potential GROUND shown in Figure 6D can be replaced with a negative voltage (less than ground) to provide additional margins.

In a further alternative, the memory element MW is interchangeable with the transistor Q20. In this case, during normal logic operation, the voltage of line CX can be made equal to the power supply voltage Vcc supplied to the logic. When the memory element MW is in its reset state, the gate of the transistor QI can be approximately equal to the power supply voltage supplied to the logic. However, when the voltages of lines X and Y are pulled close to the voltage of the gate of transistor QI, transistor QI will be turned off. In order to enable the rails Y and X to rail to rail, the voltage of the line CX can be equal to (or even greater than) the threshold voltage Vt (n channel) of the transistor QI, compared with the voltage of the logic voltage VCC. Positive, so that the transistor QI remains on (while the connection between the X and Y lines remains CLOSED) (the full range of voltages occurring on the X and Y lines).

In the embodiment shown in FIGS. 6A-6E, the memory element M (or the collapse layer to be collapsed in the memory element MB or in the crash device or the anti-fuse B) is to be shifted ( Shift) CY to conduct the crystal Q20 and increase the CX as needed to provide sufficient stylized voltage and current to achieve sufficient strength and duration for staging the memory component and/or for crashing the collapse layer period. Similarly, the ground can be made negative relative to the selected memory element M, and/or other grounds can be boosted to increase the stylized unselected memory element M (or collapse-crash layer) limit. For example, if V/2 or V/3 is a general voltage across the memory element M when it is not desired to be programmed, the CX can be increased and/or grounded to reduce the voltage across the memory element M. V/2 or V/3 is increased to V, while the voltage across other unselected memory elements M is maintained at less than V/2 or V/3 during stylization (by boosting ground to series is boosted) Memory element of the CX line M).

Another embodiment of the invention is shown in Figure 6F. Figure 6F shows control circuit 240, including control unit 244, CX line, and CY line. Control unit 244 includes a memory element M of series NMOS transistor Q22. The memory device M is coupled between the CX line and the node NZ, and the transistor Q22 is coupled between the node NZ and the voltage Vcc. In the embodiment shown in FIG. 6F, the memory element M can be formed without a collapse layer or with a collapse layer.

Another embodiment of the invention is shown in Figure 6G. The 6GG display control circuit 240 includes a control unit 244. The control unit 244 includes a memory element M, a transistor Q22, and a transistor Q24. The memory device M is coupled between the CX line and the node NZ, and the transistor Q22 is coupled between the node NZ and the voltage Vcc. The transistor Q24 is coupled between the node NZ and the voltage Vcc and its gate is also coupled to Vcc. Transistor Q24 can be used to read memory element M and separate from transistor Q22 (using a stylized memory element). The transistor Q24 can have a long channel and a narrow width to continuously provide a low leakage current. Transistor Q22 is preferably turned off during reading and is typically turned on during writing (e.g., stylized). During reading, if the memory element M is reset, the transistor Q24 can supply a bias current to properly pull the memory element (and the gate of the transistor Q24) up so that the transistor QI is turned on. The transistor Q24 bias current is low enough that when the memory device is in its set state, the gate of the transistor QI is extremely low and the transistor QI is off (and the connection is OPEN). The voltage Vcc can be higher than the highest level of the line X and the line Y. Line X can be coupled to transistor QI (eg, to its source) or can be (additionally) coupled to line CX. Alternatively, the gate of transistor QI can be pumped to a level above voltage Vcc or to a level above the highest level of line X or line Y. Next, the transistor QI can be biased to conduct and provide a low current over a wide range of voltages. During the writing, the transistor Q22 is turned on. The gate of transistor Q22 can be adjusted or the voltage Vcc can be adjusted such that when the memory component is programmed to its reset state, the current flowing through the memory component is higher than when the memory component is programmed to its set state. Current flowing through the memory component. Alternatively, when the memory component is programmed to its set state, the gate of transistor Q22 can be slowly lowered (eg, greater than about 100 nsec), while when the memory component is programmed to its reset state, The gate of transistor Q22 can be rapidly reduced (e.g., greater than about 10 nsec).

It should be noted that the control circuit can be formed as an array of control units as shown in Fig. 31A. Figure 31A shows a control circuit 240 comprising an array of three by three control units 244. Control circuit 240 includes control lines CX1 through CX3, control lines CY1 through CY3, and control unit 244. Each control unit 244 can take the form of any of the embodiments shown in Figures 6A through 6G and variations of these embodiments. Corresponding CZ output lines CZ1 through CZ9 extend from respective control units 242 of control circuit array 244. Although shown as a three by three array, the size of the array is not limited to any particular size. For example, there may be only at least one CY line and at least one CX line. In one or more embodiments of the invention, there may be a plurality of CX lines and a plurality of CY lines.

Each of the output lines CZ1 to CZ9 can be coupled to a gate of a corresponding interconnect transistor QI. For example, referring to FIG. 31B, the output lines CZ1 to CZ9 of the control circuit 240 can be coupled to the corresponding gate input lines CZ1 to CZ9 of the corresponding transistors QI of the X-Y matrix 130. Figure 31C provides an example of a control circuit 240 that includes an array of control units 244, wherein each control unit 244 is a control unit of the embodiment shown in Figure 6A.

Additional embodiments of the invention are shown in Figures 7A through 7H. Another embodiment of the programmable connection of the present invention is shown in FIG. 7A, which shows a control circuit 240 including an address line CYN (which may be a first bit line) and an address line CYP (which may be The second bit line), the address line CX (which may be the first word line), and the control unit 246. The control unit 246 includes a first memory element M (M1), a second memory element M2 (M), a transistor Q30, and a transistor Q32.

In the embodiment shown in FIG. 6G, the memory element M can be formed without a collapse layer or with a collapse layer. The first memory component M (M1) is coupled between the node (eg, ground) and the node NZ, and the second memory component M (M2) is coupled between the node NZ and the CX line. The control unit 246 further includes an NMOS transistor Q30 (whose source-to-drain coupling is passed over the memory element M (M1)) and a PMOS transistor Q32 (which is coupled across the memory element M (M2)). The gate of the NMOS transistor Q30 is coupled to the CYN line, and the gate of the PMOS transistor Q32 is coupled to the CYP line. In addition to the stylization period, the CYP can be biased to the same voltage as the voltage coupled to the memory element M2 at CX. The CYN can be biased to the same voltage as the voltage coupled to the memory element M1, such as shown here. In addition to the writing period, transistors Q30 and Q32 can be turned off.

The gate of the transistor QI is driven by the voltage Vgate of the control node NZ (the gate of the control node connected to the QI). When M1 is programmed by conduction of the crystal Q32 and CX is increased, or M2 is programmed by conducting the crystal Q30 and raising CX, one of the resistors may be high and the other may be low. The voltage at node NZ is determined by the voltage across the two memory elements M1 and M2 (e.g., between line CX and ground) and by the resistance of memory elements M1 and M2. For example, if the voltage of line CX is high, the voltage at node NZ will be equal to the voltage of line CX multiplied by RATIO, where RATIO = (resistance of M1) / (resistance of M1 + M2). If memory element M1 is programmed to high resistance and M2 is programmed to low resistance, the voltage of NZ is high, causing transistor QI to be conductive and connected to CLOSED. If memory element M2 is programmed to high resistance and M2 is programmed to low resistance, the voltage of NZ is low, causing transistor QI to be off and connected to OPEN.

The embodiment of FIG. 7B shows a memory element MW (MW1) (without a collapse layer) coupled between ground and node NZ and a memory element MW (MW2) coupled between the node NZ and the CX line. In this embodiment, control unit 246 includes memory components MW1 and MW2 and transistors Q30 and Q32. The embodiment of FIG. 7C shows a memory element MB (with a collapse layer) coupled between ground and node NZ and a memory element MW (without a collapse layer) coupled between the node NZ and the CX line. In this embodiment, control unit 246 includes memory elements MB and MW and transistors Q30 and Q32. The embodiment of Figure 7D shows a memory element MW (without a collapse layer) coupled between ground and node NZ and a memory element MB (with a collapse layer) coupled between the node NZ and the CX line. In this embodiment, control unit 246 includes memory components MW and MB and transistors Q30 and Q32.

The embodiment of FIG. 7E shows the first memory element MB (MB1) (with a collapse layer) coupled between the ground and the node NZ and the memory element MB (MB2) coupled between the node NZ and the CX line. (There is a crash layer). In this embodiment, control unit 246 includes memory elements MB1 and MB2 and transistors Q30 and Q32. Here, the state of NZ (high or low) is indeterminate at startup. Therefore, the CYN can be biased such that the transistor Q30 or Q32 is slightly turned on, such that the voltage of the node NZ is low or high, respectively (and if the voltage of the node NZ is low, the corresponding junction is connected to the transistor QI). For shutdown). Alternatively, you can choose an alternate startup state. However, after booting, the memory element MB1 or the memory element MB2 can be programmed at each intersection. Alternatively, the breakdown layer of memory element MB1 or memory element MB2 can be collapsed and the memory elements can be programmed (the memory is at the high or low resistance desired for the correct voltage of node NZ) without the need for stylized memory. One or both of the body elements MB1 or MB2 until the state needs to be restored (the increase is later attributable to the leakage of the control unit 246).

The embodiment of Fig. 7F shows a collapse device for connecting the memory element MW (MW1) between the ground and the node NZ and a second memory element MW (MW2) coupled between the node NZ and the CX line. In this embodiment, control unit 246 includes memory components MW1 and MW2, transistors Q30 and Q32, and crash device B.

The embodiment of FIG. 7G shows the first memory element MW (MW1) coupled between the ground and the node NZ, and the second memory element MW (MW2) of the crash device B connected in series between the node NZ and the CX line. . In this embodiment, control unit 246 includes memory components MW1 and MW2, transistors Q30 and Q32, and crash device B.

The embodiment of FIG. 7H shows a crash device in which the first memory element MW (MW1) of the first crash device B is connected in series with the node NZ (without a collapse layer) and a second connection between the node NZ and the CX line. The second memory element MW (MW2) of the crash device (no collapse layer). In this embodiment, the control unit 246 includes memory elements MW1 and MW2, transistors Q30 and Q32, a first crash device B, and a second crash device B. Here, as well, for the 7E picture, the state of NZ (high or low) is indeterminate at startup. Thus, the CYN can be biased such that transistor Q30 or Q32 is slightly turned on such that all unprogrammed MW pairs are in a low state or a high state, respectively. Alternatively, an alternative activation state is preferred. However, after startup, the crash device B of the series memory element can be collapsed, and then additional current in the transistor Q30 or Q32 can be turned off for general operation. Subsequently, if it is necessary to reply to this state, other collapse layers can be cut through, and the memory elements MW1 or MW2 connected at the intersection can be programmed.

Some intersections between the C and Y lines in the matrix array (eg, due to faster write speeds or lower resistances to drive the output) may be hard-wired via a programmable connection or Coupling. It is also possible to use several different types of programmable connections to a single integrated circuit or a single programmable matrix array.

If a specific application or market segmentation does not require a substantial portion of the phase change programmable connection, then the crash layer can be cascaded to select devices or loads, and only those crashable layers that the customer temporarily needs for a stylized connection can be It was crashed and tested at the factory to better ensure that both states are functional. Minimizing the number of crashed crash layers (or anti-fuse in this manner) will minimize power supply bucking. Thereafter, if required in the relevant location, those layers of the crash that were not crashed at the factory can then be collapsed in the relevant location and thus made conductive so that the stylized connection can be programmed to a low resistance state or Reprogrammed to the desired state.

Embodiments herein can also be used in contact mask programmable applications. One or more crash layers that can be used for contact mask stylization can be made in the control circuit, or part of a programmable connection, and thus can be used for all or part of the mask programmable connection or Can be used for later crashes in the farm. The collapse layer can then be collapsed by masking via, for example, using a contact mask. Other ways of simultaneously damaging the layer in the intermediate step of processing the wafer may be, for example, via the use of electrical stress or lasers to selectively collapse the collapsed layer of the selected intersection.

Similarly, for the embodiments of FIGS. 7A to 7H, the memory element M can be replaced by the threshold switcher T, the memory element MW can be replaced by the threshold switch TW, and the memory element MB can be replaced by The threshold switch TB is replaced and a volatile connection is made (programmed when starting/recovering the power). Then, after the breakdown layer is punctured (by the above-described technique for the memory element M), the transistor across the threshold switching element T is turned off, and the transistor across the threshold switching element T is turned on. Open the circuit and increase CX (if needed) to program the threshold switching element T to "on" to a low voltage. Then, since the line CX is greater than the threshold voltage Vth(T), the threshold switching element T is turned on, and as long as there is sufficient current flowing through the threshold switching element T that is triggered to be turned on (ie, the current is greater than the holding current Ih(T)) , it remains conductive. If desired, the transistors that turn off the threshold switching element T in parallel can be turned on slightly to ensure that sufficient current flows through the threshold switching element T that is triggered to conduct. Once one of the series of threshold switching elements T is triggered to be turned on, while the other is turned off, NZ will be pulled into Vh(T) of the node connecting the threshold switching element T that is turned on ( Of course, Vh(T) is the holding voltage of the threshold switching element). This will then control the transistor QI connected to NZ. If more margins are desired (for example, to eliminate Vh(T) drop), the node can be increased in voltage relative to the logic (so the gate of QI is not more conductive for CLOSED, or more difficult for OPEN to turn off) ). The endurance of the threshold switch (e.g., T) can be increased by lowering the thermal resistance at the location of T (e.g., by using a tungsten electrode on one or more sides of T).

It should be noted that the control circuit can be formed as an array of control units as shown in Fig. 32A. Figure 32A shows a control circuit 240 comprising an array of three by three control units 246. Array 32A includes control unit 246 and further includes three pairs of CYP/CYN (CYP1/CYN1, CYP2/CYN2, CYP3/CYN3) coupled to control unit 246. The array further includes three CX lines (CX1, CX2, and CX3) coupled to control unit 246. Each control unit 246 can take the form of any of the embodiments shown in Figures 7A through 7H and variations of these embodiments. Corresponding output lines CZ1 through CZ9 extend from respective control units 246 of control circuit array 240. Although shown as a three by three array, the size of the array is not limited to any particular size. For example, there may be at least one pair of CYP/CYN lines and at least one CX line. In one or more embodiments of the invention, the array can include a plurality of CYP/CYN line pairs and a plurality of CX lines. In one or more embodiments of the invention, the CYP/CYN pair and the CX line can be address lines. In one or more embodiments of the invention, the CX line can intersect the corresponding CYP with the corresponding CYN line.

Each of the output lines CZ1 to CZ9 shown in FIG. 32A can be coupled to the gate of the corresponding interconnect transistor QI. Referring to FIG. 32B, each of the output lines CZ1 to CZ9 may be coupled to corresponding gate input lines CZ1 to CZ9 of the corresponding transistor QI of the X-Y matrix 130. Control circuitry 240 in conjunction with array 130 can form a programmable matrix array that can be used as part of a programmable logic array. Figure 32C shows an embodiment of an array of control units 246. In other embodiments of the present invention, the memory element M may be replaced in part or in whole by the threshold switching element T and/or the anti-fuse crash device, as described in the embodiments herein, including the use of series and/or The transistor is biased and programmed.

The current-voltage (or "I-V") characteristic curve associated with the threshold switching element (also referred to herein as a threshold switcher). The I-V curve illustrates the relationship of the current flowing through the threshold switching material as a function of the voltage across the material.

An example of an I-V characteristic curve for a chalcogenide threshold switching element is shown in Figure 9A. Figure 9A shows the I-V plot in the first quadrant (positive voltage and current) and the third quadrant (voltage and current are negative). Although only the first quadrant is illustrated below, the third quadrant of the I-V diagram can be applied analogously (voltage and current are negative in a similar relationship).

The I-V characteristic curve IV includes a "off state" branch 450 and a "on state" branch 460. The off state branch 450 corresponds to a branch in which the current flowing through the threshold switching element (also referred to as the threshold switch) increases slightly as the voltage applied across the threshold switching element increases. This branch exhibits a small positive slope and appears to be close to the horizontal line (in the first and third quadrants of Figure 9A), which is characterized by high resistance.

The on state branch 460 corresponds to a branch in which the current flowing through the threshold switch increases significantly as the voltage applied across the threshold material increases. The slope of the on state branch 460 is greater than the slope of the off state branch 450. This is a characteristic of a threshold switching element having a dynamic on-resistance lower than the resistance of the off state. In the example shown in Figure 9A, the on-state branch appears to have a large slope in the I-V diagram and appears to be a substantially vertical line (in the first and third quadrants of Figure 9A), which appears in this region Relatively low dynamic resistance. The dynamic resistance of the on-state branch 460 can be about 1000 ohms, while the off-state branch 450 can have a resistance of about 100,000 ohms to about 200,000 ohms or even more.

The off state 450 and the on state 460 branches shown in Figure 9A are for illustrative purposes, and are not limiting. Regardless of the actual slope, the on-state branch 460 exhibits a steeper slope than the off-state branch 450. When the current flowing through the threshold switching element and a point on the off state branch 450 of the voltage system I-V curve across the threshold switching element, the threshold switching element is said to be in an off state. When the current flowing through the threshold switching element and a point on the conduction state branch of the voltage system I-V curve crossing the threshold switching element, the threshold switching element is said to be in an on state (also referred to as a trigger or threshold state). .

The switching nature of the threshold switcher can be explained with reference to Figure 9A. When no voltage is applied across the switch, the threshold switch is in an off state and no current flows. This case corresponds to the origin of the I-V diagram shown in Fig. 9A (current = 0, voltage = 0). When the current flowing through the threshold switching element increases with the voltage across the threshold switching element (the voltage Vth(T) is reached, referred to as the threshold voltage of the threshold switching element), the threshold switching element remains in the state. The current on the vertical axis (corresponding to the threshold switching voltage Vth(T)) is called the threshold switching current Ith(T).

The threshold switching element switches from the off state branch 450 of the I-V curve to the on state branch 460 when a voltage applied across the threshold switching element equals or exceeds the threshold voltage Vth(T). This switching event occurs unexpectedly, and is illustrated by a dashed line in Figure 9A. Depending on the switching and the load impedance between the forced voltage and the threshold switching element, the voltage across the threshold switching element can drop significantly and/or the current flowing through the threshold switch increases and changes for the change in device voltage. It is more sensitive (hence, branch 460 is steeper than branch 450). In the embodiment shown in the I-V curve of FIG. 9A, it can be seen that when the voltage across the threshold switching element reaches or exceeds the threshold voltage Vth(T), the voltage across the threshold switching element suddenly changes from the threshold voltage. Vth(T) returns to a lower voltage Vh(T), which is referred to as the holding voltage of the threshold switching element. The current Ih(T) corresponding to the holding voltage Vh(T) is referred to as the holding current of the threshold switching element.

The threshold switch remains in the on state branch 460 as long as the current flowing through the threshold switching element is at or above the holding current Ih(T). If the current flowing through the threshold switching element drops below the holding current Ih(T), the threshold switcher normally returns to the off state branch 450 of the I-V diagram, and needs to apply a threshold voltage greater than or equal to The voltage of Vth(T) (or the current flowing through the threshold switch is greater than or equal to the threshold switching current Ith(T)) to resume operation of the on-state branch 460. If the current is only briefly (less than the recovery time of the chalcogenide material) is reduced below Ih(T), then when the current flowing through the threshold switching material is restored (which is above or above the holding current Ih(T) When, the conduction state of the threshold switch can be maintained and/or restored.

It is readily understood by those of ordinary skill in the art that similar switching behavior occurs in the third quadrant of the I-V diagram shown in Figure 9A. For example, the applied voltage (whose absolute intensity is greater than the absolute intensity of the negative threshold voltage of the third quadrant) causes switching from the off state branch 450 to the on state branch 460.

It should be noted that the current-voltage characteristic curve shown in Fig. 9A is an example of the S-type current-voltage characteristic curve. In one or more embodiments of the invention, a threshold switching element that exhibits S-type current-voltage characteristics can be used. The threshold switching element can be formed from a chalcogenide material. However, the threshold switching element may not be formed of a chalcogenide material. A threshold switching element with (or without) a collapse layer can be formed. It will be appreciated that in one or more embodiments of the invention, other forms of threshold switching elements may be used (even if S-type characteristics are not apparent).

Figure 9A shows the IV characteristics of a threshold switching element that does not have a crash layer or has a crash layer but has been collapsed. Figure 9B shows the IV characteristics of the threshold switching element of the collapse layer with tandem threshold switching material. Curves 450 and 460 represent the off state and the on state branch of the I-V curve (as described above) after the collapse layer has been collapsed.

The voltage Vb shown in Figure 9B represents the voltage required to collapse the collapsed layer when a collapse layer is placed in series with the threshold switching material. The value of Vb can be a value that is about or greater than the breakdown voltage of the collapse layer itself. In Fig. 9B, the voltage Vb is greater than the threshold switching voltage Vth(T) of the threshold switching element. When the breakdown layer is a good insulating layer, the current flowing through the threshold switching element with the collapse layer can be ignored. Therefore, the current-voltage (I-V) curve can be along the X-axis to the voltage Vb until the voltage Vb is reached.

After the voltage across the threshold switching element reaches or exceeds Vb, the collapse layer is collapsed (ie, it is punctured or shorted). Dashed line 480 indicates that the threshold switching element will then follow branches 450 and 460 of the threshold switching element without the collapse layer (unless the collapse layer or threshold switching element is again broken, it becomes an open state). Of course, the state in the embodiments herein can be reversed by breaking (making it an open circuit) memory component, a threshold switcher, and/or a crash device.

Figures 10A and 10B illustrate current-voltage (I-V) characteristics of a chalcogenide phase change memory element that does not have a collapse layer (i.e., a MW device) or has a collapsed layer but has collapsed. Fig. 10A corresponds to the I-V characteristic of the reset state of the memory element, and Fig. 10B corresponds to the I-V characteristic of the set state of the memory element.

Figure 10A corresponds to the I-V characteristics of the chalcogenide phase change memory element (in its reset state). In FIG. 10A, the I-V diagram includes a first branch 550 and a second branch 560. The first branch 550 corresponds to a higher resistance branch, wherein the current flowing through the device increases only slightly as the voltage across the device increases. The second branch 560 corresponds to a dynamically lower resistance branch, wherein as the voltage increases, the current flowing through the device increases significantly. When the current flowing through the device is at a point on the first branch 550 of the voltage across the device, the device is said to be in its high resistance or reset state. The device can remain in its high resistance or reset state until the voltage across the device reaches or exceeds the threshold voltage Vth(M). The voltage Vth(M) represents the threshold voltage of the memory element in its reset state. The threshold current Ith(M) represents a current corresponding to the threshold voltage Vth(M).

The memory element switches from the first branch 550 to the second branch 560 when the voltage across the memory element reaches or exceeds the threshold voltage Vth(M). The voltage across the memory component will then fall back (sudden jump back) to the smaller hold voltage Vh(M) (plus the current multiplied by dV/dI (dynamic resistance of region 560)). The current Ih(M) is a holding current of the memory element M in its reset state, and is a current corresponding to the holding voltage Vh(M).

At the second branch 560, the memory components become more conductive. In the second branch 560, if sufficient energy is applied to the memory component, the device can be programmed from a reset state to its low resistance set state. Therefore, the memory element can be maintained in the low resistance setting state even after any applied energy is removed.

When the memory component is tied to the low dynamic resistance branch 560, if the current is dropped below the holding current Ih(M) before the device is programmed to the set state, the device will return to the first branch 550 (which Keep in a high resistance reset state). The device will remain in the first branch 550 until another voltage having an intensity at the threshold voltage Vth(M) (or above) is applied across the memory element.

The threshold voltage Vth(M) can be varied, for example, by about 1 to 4 volts by changing the alloy and/or thickness of the memory material, and depending on the alloy and electrode used, the value of the holding voltage Vh(M) can be about 0.5 volts (of course, other values can be used). Further, the resistance value of the first branch 550 may be about 100,000 ohms or more (corresponding to the resistance of the high resistance reset state) depending on the alloy and the applied reset current. The value of the dV/dI of the dynamic resistance of the second branch 560 can be about 1000 ohms (corresponding to the resistance of the lower dynamic resistance state). The values of the threshold voltage Vth (M), the holding voltage Vh (M), and the holding current Ih (M) may be, for example, the size of the contact with the phase change material and the composition of the phase change material. The I-V characteristic of the second branch 560 can be decomposed to represent Vh(M) + dV/dI times the current flowing through the memory element. It can be seen that the holding voltage Vh(M) extends from the straight line in the imaginary of the second branch 560 to the X-axis.

In order to prevent accidental programming of the memory component from its high resistance or reset state to its low resistance state or set state, it is sometimes possible to limit the voltage across the device to less than the threshold voltage Vth(M), except when the device When it is programmed from the reset state to the set state. In one or more embodiments of the present invention, the threshold voltage Vth(M) may be made larger than the operating power supply range Vcc. For example, for operating the supply voltage of about 2.7 to 3.3 volts, the threshold voltage Vth(M) can be adjusted to between about 4 volts or even higher. The voltage used to program the memory component can then be greater than the operating power supply voltage. In this case, a charge pump can be used to provide the required voltage, or another external voltage can be provided for stylization.

It should be noted that after the memory element has been switched to the second branch 560 (by the applied voltage reaching or exceeding Vth(M)), if sufficient energy is applied to the memory element, it can be stylized from the reset state. To the set state, and the memory element will then operate on branch 560B as shown in FIG. 10B. In this case, the memory element will remain in branch 560B as shown in Figure 10B until it is programmed back to its high resistance state (here, it returns to the I-V characteristic as in Figure 10A).

The current intensity required to program a memory component from its reset state to its set state can vary and can be adjusted with contact size. In one or more embodiments, the current intensity can be greater than the holding current Ih(M) but less than the current Ireset (Ireset is the current required to program the memory element from its set state back to its reset state). For example, Ireset can have a value between about 1 ma and 2 ma. In one or more embodiments, the memory component can be programmed from its reset state by applying an energy pulse that is approximately equal to or even greater than Ireset but has a slow trailing edge (eg, a trailing edge that is slower than 1usec) Its setting status.

After the memory component is programmed to its set state, the I-V characteristics will be as shown in Figure 10B. Figure 10B is an I-V curve corresponding to the set state of the memory element. The I-V curve shows branch 560B, which is similar to the second branch 560 of Figure 10A, except that it extends more directly to the origin for voltages less than Vh(M). When the device has been programmed to its set state, it will operate on branch 560B of Figure 10B. It will remain in branch 560B until it is programmed back to its reset state (regardless of how low current flows through the device).

The resistance of the memory element in its set state can be, for example, about 5000 ohms, and can be even lower when the voltage drop across the device approaches and exceeds the hold voltage Vh(M) (where the curve 560B decreases toward, for example, 1000 ohms) , the slope increases and dV/dI decreases).

The memory element will remain in its set state and will operate on branch 560B until it is programmed to return to its reset state. This can be done by applying a current pulse Ireset of sufficient strength for a sufficient time (eg, a pulse width greater than 10 nsec). The current pulse should have a relatively fast trailing edge (relative to the pulse of the memory element to be set), for example less than 10 nsec.

Therefore, when the device is operating in a set state, it should preferably be noted that the current flowing through the device is limited to a level less than Ireset (e.g., for a good margin, Ireset/2) unless the device is actually programmed. To ensure that no sudden stylization occurs, the current flowing through the device can be kept below the Isafe level, which can be about 70% of Ireset. Even Isafe can be set to about 50% (or less) of Ireset to prevent noise and transient currents. By, for example, increasing the amount of contact between the phase change material of the memory component and the conductive layer, the current required to reset the device can be increased to improve the marginal prevention of sudden stylization.

The phase change memory component can be programmed by a voltage that is generally higher than the power supply. By using a charge pump, a relatively high voltage can be supplied externally or on-chip to produce a higher voltage than the power supply, and a regulated or unregulated crystal load is used.

The memory element can be programmed from a set state to a reset state by, for example, a current pulse having an intensity of about 1.5 ma, a pulse width of about 10 nsec or more, and a trailing edge of less than about 10 nsec. The memory element can be programmed from a reset state to a set state using a pulse having a rear edge (e.g., 500 nsec or longer) that is similar to the intensity and width of the reset pulse but longer than the reset pulse. Alternatively, the memory element can be reset by a set pulse, which can have a smaller intensity than the reset pulse (eg, about 1 ma) and a longer length than the reset pulse (eg, about 200 nsec or longer). The state is programmed to the set state. The set pulse can have a slow trailing edge. The set pulse can also have a fast trailing edge (eg, less than about 10 nsec), but the intensity is less than the reset pulse. The intensity, width and trailing edge of the set and reset stylized pulses can be adjusted to match the composition of the phase change alloy used, which can be a chalcogenide alloy. After characterization (using techniques familiar to those of ordinary skill in the art), such values can be adjusted to conform to the composition of the alloy.

In one or more embodiments, the current pulses used to program the device to its set state may have less intensity and contrast than current pulses used to program the device to its reset state. Large width. For example, a current pulse to program the device to its set state can have an intensity of about 1 ma and a width of about 200 nsec. In another embodiment, when the device is set, a reset pulse can be applied followed by a set pulse (using a slow trailing edge, such as greater than 500 nsec or 1 usec (microsecond), depending on the choice of alloy).

As noted above, similar stylization techniques can be used to program memory elements containing crash layers (eg, MB devices). Figures 10C and 10D show current-voltage I-V curves of memory elements formed by a collapsed layer of memory material in series. Dotted line 580 indicates that the device initially formed with the collapsed layer can be converted into a device in which the collapsed layer is collapsed, and then behaves like a device without a collapsed layer, as shown by the I-V curves of Figures 10A and 10B (relatively Increase resistance without an embodiment of a collapsed layer or antifuse).

The breakdown voltage Vb shown in Figures 10C and 10D represents the voltage required to collapse the collapsed layer when the layer is in series with the memory material. The breakdown voltage Vb may be approximately equal to or greater than the breakdown voltage of the collapse layer itself. In the 10C and 10D diagrams, the voltage Vb is shown to be greater than the threshold voltage Vth(M) of the memory element.

If the phase change memory component is formed as a collapsed layer of series memory material, the memory component has a very high reactance to current flow until the voltage across the memory component reaches or exceeds voltage Vb.

After the collapse layer is collapsed and becomes conductive (by applying a voltage equal to or exceeding the intensity of Vb), a memory component (eg, an MB-type device) with a collapsed layer behaves like a memory component without a collapsed layer (eg, MW) Device) and return to the dV/dI portion of the I-V curve. The state of the memory after the crash layer is collapsed may be based on the stylized state of the dV/dI portion of the curve (branch 560 of Figure 10C or branch 560B of Figure 10D), especially if Ireset is in a crash operation More than enough pulse width (eg more than 10nsec). Otherwise, if the crash current or width is less than the program required to program the memory component to the set or reset (or trigger the threshold switcher), the state of the bit can be determined by the state of the previous process. For example, during wafer processing or packaging, heat above 400 C and a normally low cooling rate can cause the memory components to be in a set state.

For example, after a high current collapse operation of 2ma, if the current is reduced after the collapse (which is slower than the crystallization threshold) (eg, slower than 500nsec for GST225), the current MW can be set. Device (there is no complete crash layer). Or, for a peak current, which is greater than 10 nsec above Ireset and decreases at a fast trailing edge rate (eg, by reducing the peak breakdown current below Isafe at 10 nsec after the crash), the collapse layer may instead collapse The current MW-like device is then reset to the initial state. Thereafter, the device can continue to be maintained and operate like a MW device unless a long insulating layer is regenerated.

Figure 11 provides an example of a current-resistance I-R curve for a chalcogenide phase change memory element, showing the resistance of the device as a function of the intensity of the current pulses applied through the device. Current pulses applied to points on the curve may have a pulse width of about 250 nsec, and each having a rising edge and a trailing edge of less than 10 nsec. The width of the current pulse can be selected to exceed the desired setting and the reset pulse width (optionally about 1 usec, depending on the alloy, if desired) to show the effect of changing only the resistance below the current intensity. In Fig. 11, the applied current intensity is shown on the X-axis, and the resulting resistance measured during the reading after the termination of the write pulse is shown on the Y-axis. Here, the memory flows through the device by applying a voltage of about 0.2 V (the voltage selected here is less than the holding voltage to reflect a setting or reset resistance that is greater than the dV/dI resistance above Vh). The current of the component, which can be measured (during reading). However, the selection can be changed for the reading voltage of the measuring resistor to more closely match the application of the device.

When the device matures and then wears out and deteriorates, the memory component can be programmed to a low resistance or set state range (the example shown here is about 0.5 ma to 1 ma) which can vary with the size of the contact opening across the die. And can drift with repeated write cycles. Therefore, when the memory components are programmed, properly concentrating the pulse current intensity within this optimal range may require feedback, possibly a binary search that is programmed with a current and then the resulting resistance. Then, the set resistance can be measured and written in place of the write strength until a satisfactory low set resistance is obtained. Likewise, higher reset resistors (with feedback) can be programmed using techniques familiar to those of ordinary skill in the art.

Alternatively, this feedback method (the requirement associated with reading a bit after stylization) can be programmed by staging the bit with the same current strength (sufficiently exceeding the current required to determine reset to high resistance), The resulting resistance is selected to be high or low by using a fast or slow trailing edge rate to terminate the write pulse, respectively, and is minimized or avoided.

For example, as shown in the example I-V curve, the current Ireset (which can have a resistance of about 100,000 ohms or more) that the memory component can be programmed into its reset state can be measured at the factory and found to be 1.6ma. . The fuse or antifuse is used in the factory process for setting and resetting the reset (and setting) stylized intensity and pulse width and trailing edge can be adjusted to match the composition of the alloy (due to manufacturing). The fuse can be a phase change material. However, other alternatives such as laser fuse or oxide (or oxide-nitride) antifuse may preferably avoid changes in laser heat, such as from packaging or soldering. For example, the setting of the reset current strength can be sufficiently high (eg, 1.6 ma) to ensure that sufficient current is reliably programmed to program all of the phase transitions on a given die to a sufficiently high resistance. Feedback techniques can also be used to further increase the current used in the field. Even with more margins for subsequent drift or degradation (but with reduced loss of write cycle tolerance), the current used can be even higher (eg 2ma or greater to reset a bit), and The trailing edge can be slower to set a bit (where higher intensity).

This required write current can be measured at the probe and can be adjusted on the wafer to be sufficiently high compared to the worst bit measured. This current can be further adjusted to be higher using techniques familiar to those of ordinary skill in the art to provide sufficient marginal reflection program characteristics that are related to data retention and that vary with operation. And by preferably using a slow or fast trailing edge to determine the resistance state after stylization, the same current can be used to program the two states.

For example, for a die where the maximum Ireset required to be programmed to a sufficiently high resistance (ie, 200000 ohms) is 1.6 ma, then for all phase change programmable connections on the sample wafer, 2ma or even 3ma has both stylized settings and reset states throughout the life of the product. Then, after writing and being rewritten, the bits can be determined by reading. Alternatively, if a field failure is experienced, the controller can be written to the controller by the crystal, using even higher write current intensities to dynamically increase the current in the field for further reprogramming attempts.

Then, regardless of its previous state, by applying a 3ma pulse for at least 20nsec (to ensure a width margin) and a fast trailing edge of less than 10nsec, the phase change memory component can be written to a reset state with a resistance greater than, for example, 200000 ohms. . To write the intersection point to a lower set state resistance, for example less than 10,000 ohms, regardless of its previous state, the same 3ma intensity and 20nsec pulse width and a slower fast trailing edge can be applied, for example from peak to off peak (peak to off) ) is greater than 1 microsecond after the edge rate. Alternatively, for a faster stylization to a set state, the trailing edge may slowly drop to less than half of the Ireset (e.g., 0.5 ma for the example device of Figure 11), and then quickly cut off the current. This set-slope technique is more fully appreciated by reference to U.S. Patent No. 6,487,113, the disclosure of which is incorporated herein by reference.

Another embodiment of the invention is shown in Fig. 16. Figure 16 shows an embodiment of a control circuit 240 for controlling the state of the junction to connect the transistor QI. The control circuit 240 shown in Fig. 16 includes a control unit 248, a bit line BL, a bit line bar BLB, and a word line WL. Control unit 248 includes threshold switching elements T1, T2 and NMOS transistors Q41, Q42. The NMOS transistor system is interleaved. The gate of Q41 is coupled to the drain of Q42 at node NZ2, and the gate of Q42 is coupled to the drain of Q41 at node NZ1. The sources of the transistors Q41 and Q42 are coupled to the word line WL. It should be noted that the control circuit 240 of FIG. 16 includes a pair of bit lines including a bit line BL and a bit line bar BLB. The threshold switching element T1 is coupled between the bit line BL and the node NZ1, and the threshold switching element T2 is coupled between the bit line bar BLB and the node NZ2. The node NZ2 is coupled to the gate of the transistor QI such that the voltage at the node NZ2 controls the state of the transistor NZ2. It should be noted that the control unit 248 has two legs or sides. For example, the first leg (or side) is coupled to the bit line BL and includes the threshold switching element T1 and the transistor Q41, and the second leg (or side) is coupled to the bit line bar BLB and includes The switching element T2 is thresholded and the transistor Q42.

Control unit 248 can be programmed to a first state or a second state. For example, both the transistor Q41 and the threshold switching element T1 are turned on while the transistor Q42 and the threshold switching element T2 are both turned off, and the control unit 248 can be programmed to the first state. In this state, the voltage at node NZ1 can be relatively low, while the voltage at node NZ2 can be relatively high. Due to the node NZ2 coupled to the gate of the transistor QI, the transistor QI can be turned on so that the connection between the X and Y lines can be CLOSED.

Similarly, both the transistor Q42 and the threshold switching element T2 are turned on while the transistor Q41 and the threshold switching element T1 are both turned off, and the control unit 248 can be programmed to the second state. In this state, the voltage at node NZ1 can be relatively high, while the voltage at node NZ2 can be relatively low (if word line WL is low). Since the node NZ2 is coupled to the gate of the transistor QI, the transistor QI can be turned off, and the programmable connection can be in the OPEN state.

As a further embodiment of the present invention, in order to reduce current consumption, the control unit 248 may be programmed, wherein when the transistor Q41 is turned on and the transistor Q42 is turned off, the threshold switching element T1 is turned off and the switching element T2 is restricted. To be conductive. It must then be provided to ensure that sufficient leakage occurs in transistor Q42 (and transistor Q42) when turned off, so that the current flowing through the turned-on threshold switching element is maintained at the holding current Ih(T) (eg, by parallel Slightly turned on or by consuming the channel of the portion of transistor Q41 and transistor Q42).

Control unit 248, shown in Figure 16, can be used to drive an intersection point transistor coupled between X and Y. As shown in Fig. 16, the node NZ2 is coupled to the gate of the transistor QI. The drain of the QI can be connected to the Y line, and the source of the QI can be connected to the X line. When node NZ2 is high, the voltage Vgate on the gate of transistor QI is also high and transistor QI is conductive, such that the connection between X and Y is CLOSED. For example, when the transistor QI is turned on, if the X line is connected to the driver of the low state, the driver also drives the Y line to the low state through the transistor QI. Conversely, if the driver is in a high state, the driver can drive the X line to the high state and can drive the Y line to the high state until the QI is turned off. If the general high level of node NZ2 is about the same as the high level of logic, transistor QI can be turned off. For this case, line Y will be driven into the high level threshold voltage Vt (n channel) on the X line.

Control unit 248, shown in Figure 16, can operate in different ways. According to an embodiment of the invention, for an integrated circuit or wafer, the voltage Vcc can be selected as the maximum operating voltage. In one embodiment, it can be 3 volts. In one or more embodiments, the threshold switching elements T1, T2 can be designed to have a threshold voltage Vth(T) between 2Vcc/3 and Vcc. In one or more embodiments, the threshold switching elements T1, T2 can be designed to have a holding voltage Vh(T) between Vcc/3 and 2Vcc/3. In some embodiments, with the threshold voltage and hold voltage thus selected, all unselected word lines can be biased to Vcc/3. In some embodiments, all of the unselected bit lines BL and bit line bars BLB can be biased to 2Vcc/3. The selected word line WL can be biased by a voltage less than the unselected word line voltage. The logic portion of the wafer with the interconnect to be coupled can operate over a voltage range of Vcc/3 to 2Vcc/3. (It should be noted that in an alternate embodiment of the invention, voltage Vcc may be replaced by voltage V above or below Vcc. For example, V may be pumped up from Vcc).

In one embodiment, the selected cell can be written by biasing the word line WL of the selected cell to 0 volts. To write a 1, the word line BL of the selected cell can be biased to Vcc while the word line BLB of the selected cell is held at 2Vcc/3. To write a 0, the word line BLB of the selected cell can be biased to Vcc while the word line BL of the selected cell is held at 2Vcc/3.

The interleaved NMOS transistors Q41, Q42 may have a threshold voltage Vt less than Vcc/3 (eg, by a voltage between the gate and the source). The threshold voltage of the transistors Q41, Q42 can be higher to ensure that the threshold current of the drain flowing into the shutdown transistor is substantially smaller than the threshold switching from the drain of the shutdown transistor in a specific temperature range. The positive pull-up current of the components T1, T2. That is, the leakage current of the threshold switching elements T1, T2 spanning less than 0.1 volt may be greater than the leakage of the shutdown transistor Q41 or Q42. In some embodiments, the substrate may be biased or biased to a negative value relative to the negative voltage applied to the word line WL to avoid unreasonably high body effects when the word line is low. The high bulk effect reduces the threshold voltage and causes excessive sub-limit transistor leakage in the turn-off transistor.

Detailed embodiments of possible write operations are provided in the discussion that follows. However, the invention is not limited to the specific embodiments. These examples do not limit the scope of the invention.

It should be noted that the unselected cells may have a word line of Vcc/3, a bit line BL of 2Vcc/3, and a bit line BLB of 2Vcc/3. In an embodiment, selecting and writing to a cell may first bias the word line WL to 0 volts. Then, to write a 1, the bit line BL of the selected cell can be biased to Vcc while maintaining the bit line BLB of the selected cell at 2Vcc/3. To write a 0, the bit line bar BLB of the selected cell can be biased to Vcc while maintaining the bit line BL of the selected cell at 2Vcc/3.

Therefore, the word line W is initially biased to about Vcc/3, and the bit line BL and the bit line bar are biased to about 2 Vcc/3. In addition, the unit is initially tied to the 0 state, and the switching unit T1 and the transistor Q41 are turned on and the switching unit T2 and the transistor Q42 are turned off. Since the NMOS transistor Q41 is turned on, the voltage difference between the source and the drain is close to 0 and the voltage at the node NZ1 is low (about Vcc/3). Since the NMOS transistor Q41 is turned on, there is also a high capacitance coupling between the gate of the NMOS transistor Q41, its drain, and between the channel and the source. Since the threshold switching element T2 and the transistor Q42 are turned off, the voltage at the node NZ2 is high (about 2 Vcc/3).

To write a 1 to the cell, the word line WL is set to 0 and the bit line BL is made Vcc, while the word line bar BLB is held at 2Vcc/3. Vcc volts have been applied across the threshold switching element T1. This voltage is greater than the threshold voltage Vth(T) of its threshold switching element, such that the threshold switching element T1 is turned on and becomes a more conductive state. The voltage drop across the threshold switching element T1 is maintained at a voltage Vh(T) (Vh(T) can be between Vcc/3 and 2Vcc/3 such that the voltage at node NZ1 is high, approximately Vcc-Vh (T ), which is greater than Vcc/3). The high voltage of the node NZ1 is applied to the gate of the transistor Q42, thereby turning on Q42.

The voltage across the threshold switching element T2 is about Vcc/3 such that the threshold switching element T2 remains off and T1 conducts. Therefore, the interleaved coupling latch formed by the transistors Q41, Q42 switches state by turning on the NMOS transistor Q42 with a low source impedance gate voltage, and this will turn off the NMOS transistor Q41 (due to when the transistor Q42 The node NZ2 is pulled down to 0 volts during turn-on, as its gate voltage is increased by the threshold switching element T1.

Next, as the bit line is lowered, the bit line BL decreases the voltage across the threshold switching element (instead of lowering the node NZ1 when the bit line is reduced).

After the threshold switching element is turned off, when the bit line BL voltage drops, the capacitive divider action of the capacitor is reduced by Vcc minus the holding voltage of the threshold switching element T1 to lower the node NZ1. Preferably, the capacitance across the threshold switching element T1 can be substantially less than the parasitic capacitance of the transistor and node NZ1. Preferably, the holding voltage Vh(T) of the threshold switching element can be adjusted to be sufficiently smaller than 2Vcc/3 to allow the capacitive coupling of the capacitance of the node NZ1 to be reduced by the bit line BL to 2Vcc/ 3. Thus, after the bit line BL returns to 2Vcc/3, the node NZ1 remains greater than the word line WL potential by Vcc/3 (deselection after writing). If node NZ1 remains greater than word line WL potential by Vcc/3 and Vt (transistors Q41, Q42) is less than Vcc/3, transistor Q42 is guaranteed to remain conductive.

Since the node NZ1 is pulled up and started by subtracting the holding voltage of the threshold switching element from Vcc during the writing period, the bit line is lowered from Vcc to 2Vcc/3 (due to the voltage system crossing the threshold switching element T1) From its hold voltage drop Vcc/3), the voltage across the threshold switching element T1 drops below its holding voltage and turns off, because when the bit line BL falls, the node NZ1 remains relatively unchanged (due to the capacitance mainly From node NZ1, it is "on" the transistor Q42).

Reducing the bit line by 2Vcc/3 causes the node NZ1 to subtract the holding voltage of the threshold switching element by more than 2Vcc/3 due to the coupling of the capacitance of the node NZ1 to the bit line BL. Preferably, node NZ1 is not less than Vcc/3, providing a coupling of capacitance by ensuring that the threshold switching element is sufficiently less than 2Vcc/3. Likewise, the hold voltage of the threshold switching element can be less than 2Vcc/3 such that as the word line voltage increases, the voltage from word line WL to node NZ1 remains greater than Vcc/3. Here, when the word line is deselected back to Vcc/3, the coupling of the capacitor lowers the margin (the voltage between the node NZ1 and the word line keeps the transistor Q42 turned on). Therefore, when the word line is deselected, for example, to Vcc/3, the ratios Vt(T) and Vth(T) of the capacitor are preferably adjusted so that the transistor Q42 remains turned on. Even if transistor Q42 is turned off, node NZ2 is lower than node NZ1, so before node NZ2 is boosted to conduct current crystal Q41 (after deselection), node NZ2 is sufficiently boosted to turn transistor Q42 back on.

After the word line WL is brought back to Vcc/3, there is a high capacitance coupling between the gate of the NMOS transistor Q42 and its drain due to the NMOS transistor Q42. Thus, node Q42 is coupled to a value that is preferably greater than 2 Vcc/3 and less than Vcc. The holding voltage of Vcc and the threshold switching element is adjusted for the parasitic capacitance ratio to prevent the voltage between the node Q42 and the word line WL from being less than the threshold voltage plus the turn-on voltage, wherein during the reading, the turn-on voltage is at the word line. Switching from Vcc/3 to 0 is sufficient to maintain the cell state. If transistor Q42 remains on when word line WL returns to Vcc/3, node NZ2 is also brought up to Vcc/3, following and remaining approximately equal to the word line being at Vcc/3 because during standby and read. During the transition of the zigzag line, transistor Q42 remains conductive. When the word line WL is inversely selected, the edge decay and the transistor Q42 should be turned off, the node NZ2 can be temporarily kept smaller than Vcc/3, and gradually charged up to Vcc/3 by the threshold switching element T2 (or at the node) After the NZ1 is charged by the device T1, once the transistor Q42 becomes the word line WL plus the threshold voltage of the transistor Q42, it is pulled up).

To write 0 to node NZ1 (where the cell was previously in the 0 state and has a low voltage at node NZ1 (as compared to node NZ2)), the word line of the selected cell is pulled down to 0 volts. NMOS transistor Q31 remains on and node NZ1 follows, pulled down to 0 volts. Since the NMOS transistor Q41 is turned on, the gate of the NMOS transistor Q41 has a high capacitance coupling between its gate, the channel, and the source. Therefore, when the word line voltage drops, node NZ2 drops from 2 Vcc/3 coupling to near Vcc/3.

To write 0, the bit line bar BLB is brought up to Vcc, and the bit line BL is held at 2 Vcc/3. The current threshold switching unit T1 has a 2 Vcc/3 application spanning it and remains off. The threshold switching unit T2 has a 2 Vcc/3 application spanning it and it also remains off. Therefore, none of the threshold switching units T1, T2 are turned on.

Next, the bit line bar BLB is brought back to 2 Vcc/3. Since the NMOS transistor Q41 is turned on, the gate of the NMOS transistor Q41 has a high capacitance coupling between its gate, the channel, and the source. Therefore, the node NZ2 maintains a value close to Vcc/3, which is the value of the node NZ2 before the bit line bar BLB is raised to Vcc. Next, the word line WL is brought back up to Vcc/3. Similarly, since the NMOS transistor Q41 is turned on, the gate of the NMOS transistor Q41 has a high capacitance coupling between its gate, the channel, and the source. Therefore, the node NZ2 is coupled to up to 2 Vcc/3, keeping the NMOS transistor Q41 turned on and the node NZ1 being brought up to Vcc/3, following the word line potential.

For the case where the cell system was previously in the 1 state, the write 1 or 0 is symmetrically similar to the aforementioned procedure.

The worst case of the write condition would exist that the turn-on voltage for the unselected cells can be increased by repeatedly writing another bit to the same row. In this case, the same row in which the bit is tied to the bit line is repeatedly written to the same state. For this repeated write process, the bit line is repeatedly pulled from 2 Vcc/3 to Vcc and then returned to 2 Vcc/3 after writing. For example, it takes half the time (compared to 2Vcc/3) that the average voltage on the bit line of Vcc will be 2.5Vcc/3 (the voltage of other bits not written). Since this is the effective pull-up voltage for this line, through this line, the threshold switching unit charges node NZ1 (or node NZ2, if the transistor is not actively driven to be low by the turned-on transistor). Therefore, the threshold switching units T1, T2 pull up the "off" node on the bit line to the average voltage, and the node NZ1 is pulled to 2.5Vcc/3 on the unwritten bit, because The node impedance is greater than the write cycle time.

The line is "hammered" for a long time, so that the inner node is high enough to be tolerated by the unwritten bit, and the opposite state is written to one of the repeatedly written rows, instead of The unit selected during repeated writing. Here, since there is a high gate voltage, the driving on the conducting current crystal Q42 is large, so that when the bit line bar is a bit line pulled to Vcc, more current is forced through the bit line. Stick to the node NZ2. In order to minimize the increase in current that must pass through the threshold switching elements T1, T2 in the worst case, the duty cycle can be minimized, and preferably does not exceed a given percentage, such as 50%. Otherwise, Vcc can be increased or the maximum threshold voltage can be lowered such that the ratio of the turn-on voltage (the voltage at node NZ1 minus the threshold voltage minus the word line voltage) to the maximum and minimum values during the write period is reduced, To ensure that no excessive current is required to pass through the threshold switching unit to overcome the on-resistance. Similarly, the minimum turn-on voltage is selected by increasing Vcc and/or decreasing the threshold voltage such that when the word line is pulled to ground, the transistor is conductive, sufficient for the conductive crystal holding node to reasonably approach the word line voltage To prevent the possibility of bit flipping (if there is a mismatch between nodes NZ1 or NZ2 within the positioning element).

Similarly, the holding voltage Vh(T) and the voltage Vcc can be adjusted so that the minimum voltage (Vonmin) is maintained even when there is significant parasitic capacitance on the node NZ1 or feedthrough capacitance from the threshold switching unit. And is appropriate. That is, to increase Vonmin, Vh(T) can be lowered and/or Vcc can be increased to minimize the drain-source turn-on voltage for the "on" transistor, and the opposite of the cell when the word line is lowered. The crystal does not tend to conduct and "flip" the bit, resulting in a bit interference situation.

For cases with fewer margins, when the word line is deselected to Vcc/3, the bit has been written and node NZ2 (driven by the shutdown transistor) is not high enough to prevent reading or writing interference. In order to minimize the source-to-drain voltage for the conducting current crystal during the transition of the word line from Vcc/3 to 0, a controlled relatively slow edge rate (eg, a current source) can drive the word line to convert at least 50% or more, Thus, the transistor is turned on with more Von before driving the word line to ground at a faster dV/dt rate.

During writing, the current entering the selected row can be sensed to be driven from 2Vcc/3 to Vcc. If the current does not increase after a short period of time (eg, 10 nsec), or decreases after the current increases, the write period can be terminated. This similarly minimizes the write cycle time and reduces the bit line in addition to the time to deselect the voltage. To reduce the write current, Ron of the transistors Q41, Q42 can be increased (by adjusting the width or length of the transistors Q41, Q42). If Ron (transistor) is smaller than Rdyn (preventing switching elements T1, T2), the unit will be easier to write with less current. Similarly, if Rdyn (preventing switching elements T1, T2) is low, causing a drop in the peak write current to be low, the voltage margin can be raised.

In the embodiment shown in FIG. 16, when the node NZ2 is low (and the node NZ1 is high), the word line WL can be at or below the low level of the logic portion (so the word line WL can be smaller than the Y line or the X line). The level of the line). Next, the transistor QI will remain off for the high or low level of the X and Y lines (the connection can remain OPEN).

To increase the margin of causing the threshold switching element T1 or T2 when not desired, the driver can be driven to the bit line BL and the bit line bar BLB by means of a regulator (made on or off the wafer). Voltage. This regulator can be a bandgap regulator that provides a relatively tightly controlled voltage even if the operating voltage Vcc changes with temperature. This regulated voltage can also provide a level for logic to ensure a better match to the drive from the control unit to the interconnect transistor QI. Any of the embodiments described herein can similarly use a regulator to control voltage into the control unit and/or logic. Thus, in any of the embodiments presented, the operating voltage (eg, Vcc) can be adjusted and replaced with a regulated operating voltage (eg, Vcc (REG)).

Another embodiment of the invention is shown in Figure 17. Figure 17 shows control unit 248, which includes transistors Q41, Q42 and threshold switching elements T1, T2. To further facilitate stylization, transistor Q61 (with control line PX1/PY1) can be coupled to node NZ1 as shown in FIG. It will be appreciated that an additional transistor with additional control lines PX2/PY2 can be coupled to node NZ2. Those skilled in the art can add other additional circuitry to control the normal operation and the increased bias on the transistor during stylization.

Another embodiment of the invention is shown in Figure 18. Figure 18 shows a control unit 248 comprising transistors Q41, Q42 and threshold switching elements T1, T2. The current flowing through the transistors Q41 and Q42 can be coupled to the second current limiting capacitor by adding a first current limiting transistor Q71 (the source and the drain are coupled between the threshold switching unit T1 and the bit line BL). The crystal Q72 (the source and the drain are coupled between the threshold switching unit T2 and the bit line bar BLB) is limited. This shows the transistors Q71 and Q72 added in Fig. 18. In another embodiment, the transistors Q71, Q72 can be swapped by the switching elements T1, T2.

Another embodiment of the invention is shown in Figure 19. Control unit 248 includes transistors Q41, Q42 and threshold switching elements T1, T2. In order to better ensure the balance of the nodes NZ1 and NZ2, the capacitors C1 and C2 can be symmetrically added to the nodes NZ1 and NZ2. An example of an additional capacitor is shown in the embodiment of control unit 248 of Figure 19, which includes capacitors C1 and C2.

Another embodiment of the invention is shown in Figure 20. Control unit 248 includes transistors Q41, Q42 and threshold switching elements T1, T2. The node NZ2 is coupled to the gate of the N-channel transistor QI1. Moreover, in an embodiment, node NZ1 is coupled to the gate of the P-channel transistor. The transistors QI1 and QI2 are coupled in parallel between the corresponding X-ray and Y-line. The composition shown in Figure 20 is referred to as the "full mux" mode to control the connection between the X and Y lines. When transistors QI1, QI2 are programmed to CLOSED, full drive can be generated between the X and Y lines (regardless of the relative voltage of the X and Y lines).

It should be noted that the embodiment of FIG. 16 (only one node NZ2 is coupled to the n-channel transistor QI coupled between the X and Y lines) can be made to be more equivalent to the embodiment of FIG. 20 ( The drive spans the X and Y lines) by adjusting the relative voltage in the control unit section. Typically, the high level control cell region can be selected to have a higher voltage than the high level in the logic (programmable interconnect region) up to Vt (n channel transistor). As an example, when at 2Vcc/3 (or 2Vcc(REG)/3), the bit line BL and the bit line bar BLB can be at a higher voltage of 1 volt.

An alternate embodiment of the programmable connection of the present invention is shown in FIG. Control circuit 240 includes control unit 248 and word line WL, bit line BL, and bit line bar BLB. Control unit 248 includes transistors Q41, Q42, threshold switching units T1, T2, and phase change memory elements M1, M2. In the illustrated embodiment, the memory element M1 is in series with the threshold switching element T1. Similarly, the memory element M2 is connected in series with the threshold switching element T2. The series combination of M1 and T1 is in series with the transistor Q41. Similarly, the series combination of M2 and T2 is in series with the transistor Q42. In one embodiment, the phase change memory component can comprise a chalcogenide material, such as Ge2Sb2Te5. The memory elements M1, M2 can be written to a low or high resistance state using the techniques described herein. Furthermore, the write period can be terminated by a slow trailing edge to reduce the resistance (eg, slowly recover the bit line and/or word line to the deselected level, for example, with a trailing edge rate greater than 500 nsec). Similarly, the write cycle can be terminated with a fast trailing edge to increase the resistance (eg, restore the bit line and/or word line to a deselected level at a fast trailing edge rate, such as faster than 10 nsec). It should be noted that the transistor Q61 shown in FIG. 17 and/or the current limiting transistors Q71 and Q72 shown in FIG. 18 and/or the resistors C1 and C2 shown in FIG. 19 can be combined with the 21st. The embodiment shown is shown to create additional embodiments.

In the embodiment of Fig. 22, the threshold switching element is not included. Figure 22 shows an embodiment in which control unit 248 includes transistors Q41, Q42 and phase change memory elements M1, M2. Memory elements M1 and M2 are used separately (without additional threshold switching elements), and the use of fast trailing edge rates maintains the phase change memory elements in a relatively high resistance state. It should be noted that the transistor Q61 shown in FIG. 17 and/or the current limiting transistors Q71 and Q72 shown in FIG. 18 and/or the resistors C1 and C2 shown in FIG. 19 can be combined with the 22nd. The embodiment shown is shown to create additional embodiments.

Where the phase change memory element is in series with the threshold switching element (e.g., in FIG. 21), the phase change memory material can only increase the resistance of the threshold switching element by terminating the period at a slow trailing edge rate. However, the phase change memory elements M1, M2 associated with the threshold switching elements T1, T2 are written to the appropriate state such that the state remains off and the components can be successfully "written", One of them is to terminate the trailing edge rate slowly, while the other is to terminate the trailing edge rate.

For high performance operation, during normal operation, the phase change memory elements M1, M2 can be held in a low or low resistance state and can be written as a power-down, so the cell state remains powered on. (power up). Alternatively, during normal operation (by using a fast trailing edge during read and write), the phase change memory element can be held in a high resistance or reset state (with a high threshold state), then the unit One side is written to the low resistance state and turned off.

Using these phase change memory elements as a load (without additional threshold switching elements) or in series with additional threshold switching elements allows the control unit to be programmed so that the control unit remains in the state after being turned off. If only the load is used instead of the threshold switching element, the state of the memory elements M1, M2 can be either at the factory (by deposition or rapid cooling) or at the time of probing (by staging to a non-crystalline high resistance weight) The set state (with high threshold voltage) is initialized.

When used in conjunction with the threshold switching elements T1 and T2, the threshold voltages Vth(M) of the memory elements M1, M2 may be added to the threshold voltages Vth(T) of the threshold switching units T1 and T2, respectively. In one or more embodiments, the total threshold voltage of the series connection of the threshold switching unit and the memory element can be less than or equal to the sum of the individual threshold voltages.

Referring to the control unit 248 of FIG. 21, an embodiment of the method of programming the memory element M1 or M2 is to apply a voltage (which is greater than the sum of the threshold voltages of the threshold switching elements) and the threshold voltage of the memory element. It can be applied to the two legs of the control unit 248 (i.e., the bit line BL and the bit line bar BLB). The memory elements and corresponding threshold switching elements are switched to conduct low resistance branches of their individual I-V diagrams. Then, if one leg is slowly lowered and the other leg is faster, or there is less voltage across the leg, when it is turned off (for example, by lowering the voltage of the bit line BL), the control unit The state of 248 may have one leg (having a low resistance memory component, such as M1) and another leg (having a high resistance memory component, such as M2).

Then, when the power is turned on, the lower resistance side will be charged faster than the threshold voltage Vt (n channel) of the corresponding transistor Q41 or Q42. The transistor that is first charged to a high gate will be turned on. With this technique, the interleaved connector can be turned on when the power is turned on.

Another embodiment of the invention is shown in Figure 23. In addition to the non-volatile memory component as a load, control unit 248 includes NMOS transistors Q41 and Q42 and PMOS transistors Q51 and Q52 that are interleaved. Referring to the embodiment shown in Fig. 23, in another embodiment of the present invention, it will be understood that each of the memory elements M1 and M2 may be replaced by a temporary switching element. Similarly, in another embodiment of the invention, the first threshold switching element can be in series with the memory element M1 and the second threshold switching element can be connected in series with the memory element M2.

It is necessary to provide a positive programming means for the non-volatile memory elements M1, M2 shown in Fig. 23, a transistor Q61 having a programmatic line PY1 and PX1, and an electric with programmed lines PY2 and PX2. Crystal Q62 can be coupled as shown in the embodiment of the control unit (shown in Figure 24). Next, when PX1 (or PX2) is selected to be high, PY1 can positively force current through memory element M1 by transistor Q61 (or for memory element M2, by Q62 to memory) Element M2 is stylized to the opposite state). Similarly, transistors Q61 and Q62 can be used to facilitate the stylization of the states of the interleaved transistors Q41 and Q42.

Similarly, as shown in Fig. 25, transistors Q71 and Q72 may be added to connect the memory elements M1 and M2 in series to bias the bit line BL and the bit line bar BLB. To better ensure that power is turned on in a suitable state, the gates of transistors Q71 and Q72 can be kept low (by power-on logic) up to Vcc, and any regulators are well established after power is turned on. Then, the voltages to the gates of transistors Q71 and Q72 can be rapidly reduced (eg, less than 1 nsec), respectively, such that memory element M1 or M2 (one of which is programmed to low resistance and the other is programmed) The lower resistance of one of the highest resistance drives the side of the SRAM interleaved or the other side is high (significantly faster than the other), so the latch power is turned on to be programmed before the power is turned off. Preferred state. In the embodiment shown in FIG. 25, each of the bit lines BL and the bit line bars BLB can be coupled to Vcc or to a regulated Vcc (referred to as Vcc (REG)).

In a further alternative, during writing, Vbias can be pulled to ground, or relatively fully conductive and/or higher or lower to adjust the applied current during writing. At the trailing edge of the write cycle (quench), the transition at Vbias (or in deselecting PX1 and PX2) can be fast to write to a higher resistance, or can be slower to write to Lower resistance.

During normal operation, Vbias can be positioned such that transistors Q71 and Q72 are slightly conductive and are suitable for pull-up lines BL and BLB. That is, if Vcc or Vcc(REG) applied to the portion during normal logic operation is about 2 volts and the transistor threshold voltage Vt (p channel) is, for example, about 0.6 volts, Vbias for general logic operation. It can be positioned at approximately 1.3 volts (and capacitively coupled to a positive power supply to better track the 2 volt power supply). Vbias can be adjusted. Also, Vcc can be adjusted with a bandgap regulator and then Vbias is coupled to the resulting Vcc (REG).

In one or more embodiments, the bit line BL can be coupled to the first voltage V1, and the bit line bar BLB can be coupled to the second voltage V2, wherein V1 can be different from V2 (eg, during writing). It can also be different from Vcc or Vcc (REG).

The control units, control circuits, and programmable connections described herein are beneficial for more than just FPGAs, but also include embedded memory applications that incorporate FPGA-coupled interconnects. Embodiments herein can be implemented in conjunction with embedded memory using volatile or non-volatile memory cells. For example, for an embedded memory using an array of non-volatile memory (in the form of a phase change memory, having a thin film threshold switching element), the threshold switching element can be made to be used as a phase A memory selection device, and also a control unit for a portion of the interconnectable interconnect, as shown in the embodiments herein.

Embodiments implemented for FPGAs can provide phase change or chaal procedures that allow for the addition of a compact, more efficient array of memory cells, with fewer additional programs. Moreover, the illustrated procedure for implementing an FPGA-coupled interconnect can advantageously allow for the addition of a low cost cache buffer to a non-volatile flash using phase change memory. For embedded memory implemented in thin film memory, such as phase change memory selected with a threshold switcher, active phase isolation devices are not required in or below the memory cells or arrays due to phase change (embedded) memory arrays. Therefore, the control unit and the intersection switch can be placed under the phase change memory array.

Embodiments of the volatile or non-volatile control unit herein may be written from a processor off-chip and its memory, or by/from a non-volatile embedded crystalline memory cell (memory cell) On-chip (for example, a command to power on or use an on-chip microprocessor via an input/output interface for an external user). Similarly, when the power is turned off, the data in the volatile control unit (the state thereof) can be loaded into the non-volatile embedded memory (out-of-chip or on-chip).

In some embodiments, the control unit including the threshold switching unit can be smaller and has less added cost than a conventional 4-cell or 6-transistor SRAM control unit. Size reduction can reduce the cost of SRAM memory, whether applied to a separate standard memory or embedded memory on a logic or processor chip, which provides other functions such as a microprocessor or digital signal processor. Dimensional reduction also provides increased memory capacity while maintaining a reasonable size for the wafer, as specified by package size and die yield limits.

Another embodiment of the invention is shown in Figure 26. The programmable connection shown in Figure 26 includes a control circuit 240 that includes a control unit 246, a bit line BL, a bit line bar BLB, and a word line WL. The control unit 246 includes transistors Q41, Q42 and a load LD1 of the series transistor Q41 and a load LD2 of the series transistor Q42. The transistor Q41 is alternately coupled to the transistor Q42.

In one or more embodiments, the load LD1 and/or LD2 may comprise a chalcogenide material. In one or more embodiments, the load LD1 and/or LD2 may comprise a phase change memory material. In one or more embodiments, the load LD1 and/or LD2 may include a threshold switching material. In one or more embodiments, the threshold switching material can be a chalcogenide material.

In one or more embodiments, the threshold switching material can be an S-type material. In one or more embodiments, the load LD1 and/or LD2 may comprise phase change memory elements. In one or more embodiments, the load LD1 and/or LD2 may include a threshold switching element. In one or more embodiments, the load LD1 and/or LD2 may comprise a phase change memory element of a series of threshold switching elements.

In another embodiment of the present invention, the NMOS transistors Q41, Q42 shown in FIG. 26 may be replaced by PMOS transistors that are interleaved. In another embodiment of the invention, the NMOS transistors Q41, Q42 shown in Figure 26 may be replaced by interleaved bipolar transistors (or even any other form of transistor).

In another embodiment of the present invention, the transistor Q61 can be coupled to the node NZ1 as shown in FIG. In another embodiment of the present invention, the transistor Q71 can be coupled in series to the load LD1, and the transistor Q72 can be coupled in series to the load LD2. This is shown in Figure 28.

In one or more embodiments of the programmable connection of the present invention, the control unit can be formed to include two interleaved inverters. In an embodiment, the inverters may be identical to each other. The output of the first inverter can be coupled to the input of the second inverter. The output of the second inverter can be coupled to the input of the first inverter. One of the outputs of the interleaved inverters can be used to provide an output signal to control the interconnect transistors. In one or more embodiments of the invention, two interleaved inverters may form a circuit having two stable states and may be a bistable circuit. The two interleaved inverters form a latch. One or both of the inverters comprise a chalcogenide material. One or both of the inverters comprise a phase change material. One or both of the inverters contain a threshold switching material. One or both of the inverters comprise a phase change material of a series of threshold switching materials. One or both of the inverters comprise phase change memory elements. One or both of the inverters include a threshold switching element. One or both of the inverters comprise phase change memory elements of the series threshold switching elements. One or both of the inverters comprise a first threshold switching element in series with the second threshold switching element. One or both of the inverters comprise a first phase change memory element in series with a second phase change memory element. The first inverter can include a first transistor coupled in series with the first load. The second inverter can include a second transistor coupled in series with the second load. The first transistor can be staggered to the second transistor. The first transistor can be a MOS transistor, such as an NMOS transistor or a PMOS transistor. The first transistor can be a bipolar transistor. The first load and/or the second load may comprise a chalcogenide material. The first load and/or the second load may comprise a phase change material. The first load and/or the second load may comprise a threshold switching material. The first load and/or the second load may comprise a phase change material of the tandem threshold switching element. The first load and/or the second load may comprise phase change memory elements. The first load and/or the second load may comprise a threshold switching element. The first load and/or the second load may comprise phase change memory elements of the series threshold switching elements. The first load and/or the second load may comprise additional transistors in series with the threshold switching elements. The first load and/or the second load may comprise additional transistors in series phase change memory elements. The first load and/or the second load may comprise an additional transistor in series with a series of threshold switching elements and phase change memory elements. The first load and/or the second load may comprise a capacitor.

In one or more embodiments of the invention, the control unit can be formed as a dynamic random access memory (SRAM) device. The SRAM device can comprise a chalcogenide material. The SRAM device can comprise a phase change material. The SRAM device can include a threshold switching material. The SRAM device can include a phase change material in series with a threshold switching element. The SRAM device can include phase change memory elements and/or threshold switching elements. The SRAM device can include a phase change memory component in series with a threshold switching element.

The SRAM device can be formed as two interleaved inverters (eg, a pair of interleaved inverters). For example, the output of the first inverter can be coupled to the input of the second inverter, and the output of the second inverter can be coupled to the input of the first inverter. The two interleaved inverters form a latch. Each inverter can comprise a transistor in series load. The transistor can be any type of transistor, such as a bipolar and MOS transistor (eg, an NMOS or PMOS transistor). An example of this type of circuit using MOS transistors is shown in Figures 16 through 28. Figures 26 through 28 show loads LD1 and LD2. Each of the loads LD1 and LD2 in FIGS. 26 and 27 may comprise a chalcogenide material and/or a phase change material and/or a threshold switching material. Each load can include a phase change memory element and/or a threshold switching element. Each load may comprise a phase change memory element in series with a threshold switching element. Each load can include an additional transistor in series with a phase change memory element. Each load may include an additional transistor in series with a threshold switching element. Each load may comprise an additional transistor in series with a series of threshold switching elements and phase change memory elements. The control unit 248, shown in Figure 29, provides an example of two interleaved inverters, each of which uses two threshold switching elements.

In one or more embodiments of the invention, the control unit can be formed as an SRAM unit as described in U.S. Patent Application Serial No. 11/158,619. The content of U.S. Patent Application Serial No. 11/158,619 is incorporated herein by reference. For example, the control unit can be an SRAM memory cell containing a chalcogenide material.

One or more embodiments of the invention may include a control circuit 240 that includes a control unit 248, as shown in FIG. Control unit 248 includes a threshold switching element T1A that is coupled in series with switching element T2A. It also includes resistors R11 and R12. Control unit 248 further includes threshold switching elements T1B and T2B. Control unit 248 also includes resistors R1B and R2B. Control unit 248 optionally includes a transistor Q61 having control terminals PX1 and PY1.

It should be noted that the control circuit can be formed as an array of control units as shown in Figure 33A. Figure 33A shows a control circuit 240 of a control unit 248 comprising a three by three array. Control circuit 240 includes control unit 248 and further includes three pairs of bit line/bit line bars (BL1/BLB1, BL2/BLB2, BL3/BLB3) interconnected to control unit 248. The array further includes three word lines (WL1, WL2, WL3) interconnected to control unit 248. Each control unit 248 can take the form of, for example, any of the embodiments shown in Figures 16 through 29 and variations of these embodiments. The corresponding CZ output lines CZ1 to CZ9 extend from the respective control units 248 of the control circuit 240. Although a three by three array is shown, the invention is not limited to any particular size. For example, it can have at least one pair of bit line/bit line bars and at least one word line. In one or more embodiments of the present invention, the control circuit array can include a plurality of bit line/bit line bar pairs and a plurality of word lines. In one or more embodiments of the present invention, the bit line/bit line bar line and the word line may be address lines.

Each of the output lines CZ1 to CZ9 can be coupled to a gate of a corresponding interconnect transistor QI. Referring to Figure 33B, respective output lines CZ1 through CZ9 from control circuit 240 can be coupled to corresponding gate output lines CZ1 through CZ9 of corresponding transistors QI of X-Y matrix 130. Control circuitry 240 in conjunction with X-Y matrix 130 can be used to form a programmable matrix array that can be used with programmable logic devices. Figure 33C shows an embodiment of a control circuit 240 that includes an array of control units 248.

Included in different types and embodiments (eg, those shown in control unit 242 of FIG. 5A-N, in control unit 244 of FIG. 6A-E diagram, in control unit 246 of diagram 7A-H, or The plurality of control units in the control unit 248 of Figures 16-19 can thus be arranged in an array. Examples of control unit arrays are shown in Figures 30A, B, C, 31A, B, C, 32A, B, C, 33A, B, and C. Each control unit can be used to control the state of an interconnected transistor (or some other type of controllable interconnect device) that can be coupled between the X and Y lines. An array of control cells can be used to control the state of the X-Y array of transistors (or some other type of controllable interconnect device), wherein each of the cell systems is coupled to a corresponding X line and a corresponding Y line. between. A control unit array incorporating an X-Y transistor array can be used to form a programmable logic device. To implement a programmable logic device, an array of control cells and an array of transistors (or other forms of controllable interconnect devices) can be, for example, alongside each other, parallel to each other, or separated (eg, metal and alloy) layers. It’s time to put it.

It should be noted that each of the control units described herein (eg, control unit 242, 244, 246, or 248 in Figures 5A-N, 6A-E, 7A-H, 16-19) ) can also be considered as a memory unit. Each control unit can be programmed between at least two perceptible states. The arrays shown in Figures 30A, B, C, 31A, B, C, 32A, B, C, 33A, B, C can be viewed as an array of memory cells. Thus, the control circuit 240 of the present invention can be formed as one or more memory cells. Specifically, the control circuit 240 of the present invention shown in the 30A, 31A, 32A, and 33A can be regarded as an array of memory cells. In one or more embodiments, the one or more memory cells comprise a chalcogenide material. In one or more embodiments, the one or more memory cells comprise phase change and/or threshold switching materials. In one or more embodiments, the one or more memory cells comprise phase change memory elements and/or threshold switching elements. In one or more embodiments, one or more memory cells comprise a phase change material in series with a threshold switching material. In one or more embodiments, one or more memory cells include phase change memory elements in series with a threshold switching element.

One type of programmable logic device is a programmable logic array (PLA). Figure 12 shows a block diagram of the PLA. As shown in the block diagram, the PLA includes a set of inputs 610, a first set of programmable connections 620, an AND array 630, a second set of programmable connections 640, an OR array 650, and a set of outputs 660.

Figure 13 is an embodiment of a PLA, which is an implementation of the block diagram of Figure 12. Figure 13 shows a PLA comprising: a set of inputs 610 comprising A, B, C; a set of programmable connections 620 consisting of CPS components (control circuits and intersections between the interconnectable interconnects) Connected to the transistor; AND array 630; a second set of programmable connections 640 (and coupleable interconnects, like 620); an OR array 650; and a set of outputs 660, including outputs Z0, Z1, Z2. The first and second sets of programmable interconnects are formed using a programmable connection CPS comprising phase change material. The displayed AND and OR gates can also have additional programmed or unprogrammed inputs and can also have inverted outputs.

By staging to a lower resistance, the connections from the logic can be made from Y to X and then from the output to the gate, as is well known to those of ordinary skill in the art. It will be apparent to those skilled in the art to apply these concepts to fabricate an FPGA or FPLA using the embodiments herein.

To minimize the standby current, only those programmable connection elements (which are temporarily needed for a given customer's type of circuit application) need to be tested and can be used for stylization. In the most extreme cases, all stylized connections at the intersections can be tested at the factory, meaning that any crash device is made electrically conductive and, if not programmed into a low resistance state, causes leakage.

The current or voltage imposed during stylization, in addition to other useful options well known to those of ordinary skill in the art, can be adjusted at the factory using additional current or voltage stylization options and can be used at the factory or in related locations. The off-chip or off-chip processor is implemented by algorithms and timing.

Therefore, leakage is reduced by using the crash layer and crashing before shipping or at the relevant location (only for those crash layers that may be normally programmed and/or actually used (other than OPEN)). If there is a need, even if it is not tested, there is a lower certain successful operation (and less leakage until it is programmed to short out the layer, while the component of the series collapse layer is in a high resistance state) Most of them can still be stylized on site.

It is noted that another example of the application of a phase change memory to a programmable logic device is shown in U.S. Patent Application Serial No. 10/459,632, the disclosure of which is incorporated herein by reference.

While the invention has been described in detail, the preferred embodiment For example, the size or parallel connection of the intersection point transistors can be increased to reduce the CLOSED resistance. Furthermore, additional features that provide further advantages are not necessary to implement the invention, and may be omitted or substituted for different features that are more advantageous for particular use. The above-described embodiments are applicable to those skilled in the art, and modifications and variations of the embodiments herein are included in the scope of protection of the invention as defined by the scope of the claims herein.

Referring to Figure 14, a portion of a system 2500 in accordance with an embodiment of the present invention is shown. System 2500 can be used with wireless devices such as personal digital assistants (PDAs), laptops or notebooks with wireless Internet access, web tablets, telephone or wireless mobile phones, pagers, instant messaging devices , a digital music player, a digital camera, or other device suitable for wirelessly transmitting and/or receiving information. System 2500 can be used with any of the following systems: a wireless local area network (WLAN) system, a wireless personal area network (WPAN) system, or a mobile communication network, although the invention is not limited thereto.

The system 2500 can include a controller 2510, an input/output (I/O) device 2520 (eg, a keyboard, a display), a memory 2530, a wireless interface 2540, a dynamic random access memory (SRAM) 2560, and each other via a bus 2550 and coupled. In an embodiment, battery 2580 supplies power to system 2500. It should be noted that the scope of the invention is not limited to embodiments having any or all of these components.

Controller 2510 can include, for example, one or more microprocessors, digital signal processors, microcontrollers, or the like. Memory 2530 can be used to store messages transmitted to (or via) system 2500. Memory 2530 is optionally used to store instructions executed by controller 2510 during operation of system 2500 and can be used to store user profiles. The instructions can be stored as digital information and, as disclosed herein, the user profile can be stored in one section of the memory as digital data and the other section as analog memory. As another example, a given session can be labeled and stored with digital information at a time, and can then be relabeled and reconfigured to store analog information. Memory 2530 can be one or more different types of memory.

I/O device 250 can be used to generate a signal. System 2500 can use wireless interface 2540 to transmit and receive messages to or from the wireless communication network using radio frequency (RF) signals. An example of wireless interface 2540 can include an antenna, or a wireless transceiver, such as a dipole antenna, although the invention is not limited thereto. Similarly, an I/O device can transmit a voltage that reflects the storage as a digital output (if stored as digital information) or it can be analogous information (if stored as analog information). One or more components of system 2500 can be beneficially combined with the embodiments described herein to implement or modify the functionality of the field by altering or optimizing the interconnections and using the gates or other logic functions therein. For example, a coupleable interconnect and/or embedded memory uses a program for generating portions of the control unit and the coupleable interconnect or programmable interconnect.

Although the above illustrates an example applied to wireless, the present invention can also be applied to non-wireless applications.

As noted above, in various embodiments of the invention, any programmable resistive element or material may be used in place of the phase change element or phase change material. The programmable resistive element or material can be any element or material that can be programmed between at least two resistive states, whether volatile (loss of state after power is turned off) or non-volatile. Programmable resistive elements or materials do not require phase change elements and/or threshold switches or materials.

While the invention has been described with reference to the embodiments of the embodiments of the invention The scope of the appended claims is intended to cover all such modifications and variations and fall within the spirit and scope of the invention.

10. . . Anti-fuse

12A. . . First metal layer

12B. . . Second metal layer

14. . . Dielectric layer

16. . . Crash layer

100. . . Array

125. . . matrix

130. . . matrix

200A. . . First terminal

200B. . . Second terminal

200C. . . Third control terminal

240. . . Control circuit

242. . . control unit

244. . . control unit

246. . . control unit

248. . . control unit

260. . . Voltage Regulator

280. . . Charge pump

310A. . . First electrode

310B. . . Second electrode

380. . . Crash layer

450. . . Branch

460. . . Branch

480. . . Branch

550. . . Branch

560. . . Branch

560B. . . Branch

580. . . Branch

610. . . Input

620. . . Programmable connection

630. . . AND array

640. . . Programmable connection

650. . . OR array

660. . . Output

2500. . . system

2510. . . Controller

2520. . . Input/output device

2530. . . Memory

2540. . . Wireless interface

2550. . . Busbar

2560. . . SRAM

2580. . . battery

2590. . . camera

A to P. . . Output line

BL. . . Bit line

BLB. . . Bit line

CPS. . . Programmable connection

CTB. . . Bias voltage

CX. . . Address line

CX1 to CX3. . . CX control line

CY1 to CY3. . . CY control line

CYN. . . Address line

CYP. . . Address line

CZ1 to CZ9. . . line

GROUND. . . Ground contact

LD1. . . load

LD2. . . load

M. . . Memory component

M1. . . Memory component

M2. . . Memory component

MB. . . Memory component

MB1. . . Memory component

MB2. . . Memory component

MW. . . Memory component

MW1. . . Memory component

MW2. . . Memory component

N2. . . node

N4. . . node

N10. . . node

N20. . . node

NZ. . . node

NZ1. . . node

NZ2. . . node

PX. . . line

PX1. . . Control line

PX2. . . Control line

PY. . . line

PY1. . . Control line

PY2. . . Control line

Q2. . . Transistor

Q4. . . Transistor

Q6. . . Transistor

Q12. . . Transistor

Q19. . . Transistor

Q22. . . Transistor

Q30. . . Transistor

Q32. . . Transistor

Q41. . . Transistor

Q42. . . Transistor

Q61. . . Transistor

Q71. . . First current limiting transistor

Q72. . . Second current limiting transistor

Q8. . . Transistor

QI. . . Transistor

QI1. . . N-channel transistor

R11. . . Resistor

R12. . . Resistor

S1 to S8. . . structure

T. . . Threshold switching element

T1. . . Threshold switching element

T1A. . . Threshold switching element

T1B. . . Threshold switching element

T2. . . Threshold switching element

T2A. . . Threshold switching element

T2B. . . Threshold switching element

TB. . . Threshold switcher

TW. . . Threshold switcher

V1. . . Voltage

V2. . . Voltage

Vcc. . . Power supply voltage

Vcc(REG). . . Adjusted voltage

Vpumped. . . Pumped voltage

Vpumped(REG). . . Adjusted pumped voltage

Vt. . . Voltage

X, Y, CX, CY, CZ. . . line

X1 to X4. . . wire

Y1 to Y4. . . wire

Z0 to Z2. . . Output

Figure 1 shows an example of a programmable connection using a conventional SRAM technique to drive the gate of an n-channel transistor QI at an intersection. Figure 2A shows a stylized connection using anti-fuse technology; Figure 2B shows an example of an anti-fuse comprising a breakdown layer; Figure 3 shows an embodiment of an electrically programmable matrix array of the present invention; 4A is an embodiment of a programmable connection of the present invention, showing a control circuit for driving an intersection point transistor; FIG. 4B is an embodiment of a programmable connection of the present invention, showing coupling to a control circuit Voltage regulator; FIG. 4C is an embodiment of a programmable connection of the present invention showing a charge pump coupled to a control circuit; FIG. 4D is an embodiment of a programmable connection of the present invention, display coupling a charge pump coupled to a voltage regulator coupled to the control circuit; FIG. 4E is an embodiment of a programmable connection of the present invention; FIG. 5A is an embodiment of the programmable connection of the present invention, showing A control circuit comprising a memory component and a threshold switching component; FIG. 5B is an embodiment of the control circuit of the present invention, comprising a memory component (without a collapse layer) and a threshold switching component (without a collapse layer) ; Figure 5C is the control of the present invention An embodiment of the circuit includes a memory component (with a collapse layer) and a threshold switching component (no collapse layer); and FIG. 5D is an embodiment of the control circuit of the present invention, including a memory component (none a crash layer) and a threshold switching element (with a collapse layer); FIG. 5E is an embodiment of the control circuit of the present invention, including a memory component (with a collapse layer) and a threshold switching component (with a collapse layer) 5F is an embodiment of the control circuit of the present invention, comprising a memory component (no collapse layer), a crash device, and a threshold switching component (no collapse layer); FIG. 5G is a control of the present invention An embodiment of the circuit includes a memory component (no collapse layer), a crash device, and a threshold switching component (no crash layer); and FIG. 5H is an embodiment of the control circuit of the present invention, including a memory Body element (no collapse layer), a first collapse device, a second collapse device, and a threshold switching element (no collapse layer); FIG. 5I is an embodiment of the programmable connection of the present invention, having a control circuit including a threshold switching element, a memory An element, and a transistor in parallel with the memory element; FIG. 5J is an embodiment of the programmable connection of the present invention, having a control circuit including a threshold switching element and a memory element And a transistor in parallel with the threshold switching element; FIG. 5K is an embodiment of the programmable connection of the present invention, having a control circuit including a threshold switching component and a memory component And a transistor in series with the memory element and the threshold switching element; FIG. 5L is an embodiment of the programmable connection of the present invention, having a control circuit including a threshold switching element a memory component, and a transistor in series with the memory component and the threshold switching component; FIG. 5M is an embodiment of the programmable connection of the present invention, having a control circuit, the control circuit including Connecting a memory component of a transistor; FIG. 5N is an embodiment of the programmable connection of the present invention, having a control circuit including a threshold cut of a transistor in series 6A is an embodiment of a programmable connection of the present invention having a control circuit including a transistor and a memory component; and FIG. 6B is a programmable connection of the present invention An embodiment has a control circuit including a transistor and a memory component (without a collapse layer); and FIG. 6C is an embodiment of the programmable connection of the present invention having a control circuit, The control circuit comprises a transistor and a memory component (with a collapse layer); FIG. 6D is an embodiment of the programmable connection of the present invention, having a control circuit including a memory component (no crash) Layer 6), a crash device, and a transistor; FIG. 6E is an embodiment of the programmable connection of the present invention, having a control circuit including a memory component (no crash layer), a crash The device and a transistor; FIG. 6F is an embodiment of the programmable connection of the present invention, having a control circuit comprising a memory component and a transistor; FIG. 6G is a Program One embodiment of the connection has a control circuit including a memory component, a first transistor, and a second transistor; FIG. 7A is an embodiment of the programmable connection of the present invention Having a control circuit, the control circuit comprising a first memory component and a second memory component, wherein each memory component is connected in parallel with a transistor; FIG. 7B is one of the programmable connections of the present invention An embodiment has a control circuit including a first memory element (without a collapse layer) and a second memory element (without a collapse layer), wherein each memory element is connected in parallel with a transistor; 7C The figure is an embodiment of the programmable connection of the present invention, having a control circuit including a first memory component (with a collapse layer) and a second memory component (without a collapse layer), wherein each The memory component is connected in parallel with a transistor; FIG. 7D is an embodiment of the programmable connection of the present invention, having a control circuit including a first memory component (no collapse layer) and a first Two memory Piece (with collapse layer), wherein each memory component is connected in parallel with a transistor; FIG. 7E is an embodiment of the programmable connection of the present invention, having a control circuit, the control circuit including a first memory a component (having a collapse layer) and a second memory component (with a collapse layer), wherein each memory component is in parallel with a transistor; FIG. 7F is an embodiment of the programmable connection of the present invention, having a a control circuit comprising a first memory component (no collapse layer), a second memory component (no collapse layer), and a crash device, wherein the first memory component and the crash device are The transistors are connected in parallel, and the second memory component is connected in parallel with a transistor; FIG. 7G is an embodiment of the programmable connection of the present invention, having a control circuit including a first memory component a (no collapse layer), a second memory component (no collapse layer), and a collapse device, wherein the first memory component is in parallel with a transistor, and the second memory component is associated with the collapse device a transistor in parallel; 7H An embodiment of the programmable connection of the present invention has a control circuit including a first memory component (no crash layer), a second memory component (no crash layer), a first crash And a second crash device, wherein the first memory component and the first crash device are connected in parallel with a transistor, and the second memory component and the second crash device are connected in parallel with a transistor; 8A is an embodiment of the device structure of the present invention, the device structure includes a phase change or threshold switching material; and FIG. 8B is an embodiment of the device structure of the present invention, the device structure including a phase change or a threshold Switching the material, a first electrode, and a second electrode; FIG. 8C is an embodiment of the device structure of the present invention, the device structure includes a phase change or threshold switching material, and a collapse layer; FIG. 8D is An embodiment of the device structure of the present invention, the device structure comprising a phase change or threshold switching material, and a collapse layer; FIG. 8E is an embodiment of the device structure of the present invention, the device structure comprising a phase change or Threshold switching materials, a first electrode, a second electrode, and a collapse layer; FIG. 8F is an embodiment of the device structure of the present invention, the device structure comprising a phase change or threshold switching material, a first electrode, and a second electrode And a collapse layer; FIG. 8G is an embodiment of the device structure of the present invention, the device structure comprising a phase change or threshold switching material, a first electrode, a second electrode, and a collapse layer; The figure shows an embodiment of the device structure of the present invention. The device structure comprises a phase change or threshold switching material, a first electrode, a second electrode, and a collapse layer; and FIG. 8I is a device structure of the present invention. In one embodiment, the device structure includes a phase change switching material and a threshold switching material; and FIG. 8J is an embodiment of the device structure of the present invention, the device structure including a phase change switching material and a threshold switching material And a collapse layer; FIG. 8K is an embodiment of the device structure of the present invention, the device structure includes a phase change switching material, a threshold switching material, and a collapse layer; and FIG. 8L is a device structure of the present invention An embodiment of the device The structure includes a phase change switching material and a threshold switching material; the eighth embodiment is an embodiment of the device structure of the present invention, the device structure comprising a phase change switching material, a threshold switching material, and a collapse layer 8N is an embodiment of the device structure of the present invention, the device structure includes a phase change switching material, a threshold switching material, and a collapse layer; and FIG. 9A is a threshold switching element (without a collapse layer) Example of a current-voltage curve; Figure 9B is an example of a current-voltage curve for a threshold switching element (with a collapse layer); Figure 10A is a current-voltage for a phase change memory element (without a collapse layer) in a reset state Example of a curve; Figure 10B is an example of a current-voltage curve of a phase change memory element (without a collapse layer) in a set state; and FIG. 10C is a current of a phase change memory element (with a collapse layer) in a reset state - An example of a voltage curve; Figure 10D is an example of a current-voltage curve of a phase change memory element (with a collapse layer) in a set state; and Figure 11 is an example of a current-resistance curve of a phase change memory element; Programmable logic array An example of a block diagram; FIG. 13 is an illustration of a block diagram of a 12th diagram using a programmable connection; and FIG. 14 is a block diagram of an electronic device including a memory, a controller, a wireless interface, Camera, SRAM, I/O, and battery; Figure 15A shows an embodiment of a control circuit comprising a four by four matrix control unit, wherein each control unit includes a memory unit in series with a threshold switching element Figure 15B shows an embodiment of the control circuit of the present invention, comprising a four by four matrix control unit, wherein each control unit provides a control signal to a corresponding interconnect transistor; Figure 16 shows the control of the present invention An embodiment of the circuit having interleaved coupled transistors, wherein each load includes a threshold switching element; and Figure 17 shows an embodiment of the control circuit of the present invention having interleaved coupled transistors, wherein each load comprises a threshold switching element; Figure 18 shows an embodiment of the control circuit of the present invention having a staggered coupled transistor, wherein each load includes a threshold switching element; Figure 19 An embodiment of the control circuit of the present invention has a staggered coupled transistor, wherein each load includes a threshold switching element; and FIG. 20 shows an embodiment of the control circuit of the present invention having a staggered coupled transistor Wherein each load comprises a threshold switching element; Figure 21 shows an embodiment of the control circuit of the present invention having a staggered coupled transistor, wherein each load comprises a memory element in series with a threshold switching element; Figure 22 shows an embodiment of the control circuit of the present invention having interleaved transistors, wherein each load comprises a memory element; and Figure 23 shows an embodiment of the control circuit of the present invention having staggered coupled power a crystal, wherein each load comprises a memory component; Figure 24 shows an embodiment of the control circuit of the present invention having a staggered coupled transistor, wherein each load comprises a memory component; and Figure 25 shows the control of the present invention An embodiment of a circuit having interleaved coupled transistors, wherein each load comprises a memory component; and Figure 26 shows an embodiment of the control circuit of the present invention, There are interleaved coupled transistors and loads; Figure 27 shows an embodiment of the control circuit of the present invention with interleaved coupled transistors and loads; and Figure 28 shows an embodiment of the control circuit of the present invention with interleaving Coupled transistor and load; Figure 29 shows an embodiment of the control circuit of the present invention comprising four threshold switching elements; Figure 30A shows an embodiment of the control circuit of the present invention, comprising an array of control units Having a CX line and a CY line; FIG. 30B shows an embodiment of the control circuit of the present invention, comprising a three by three array control unit, wherein each control unit provides a control signal to one of the X-Y arrays corresponding to each other Connected to a transistor; FIG. 30C shows an embodiment of the control circuit of the present invention, comprising an array of control units having CX lines and CY lines; and FIG. 31A showing an embodiment of the control circuit of the present invention, comprising an array Control unit having CX line and CY line; FIG. 31B shows an embodiment of the control circuit of the present invention, comprising a three by three array control unit, wherein each control unit provides a control signal to X-Y One of the columns corresponds to the interconnecting transistor; FIG. 31C shows an embodiment of the control circuit of the present invention, comprising an array of control units having CX lines and CY lines; and FIG. 32A showing one of the control circuits of the present invention For example, a control unit including an array having CX lines, CYP lines, and CYN lines; and FIG. 32B showing an embodiment of the control circuit of the present invention, including a three-by-three array control unit, wherein each control unit provides one Controlling the signal to an interconnecting transistor corresponding to one of the X-Y arrays; Figure 32C shows an embodiment of the control circuit of the present invention, comprising an array of control units having CX lines, CYP lines, and CYN lines; The figure shows an embodiment of the control circuit of the present invention, comprising an array of control units, word lines, bit lines, and bit line bars; Figure 33B shows an embodiment of the control circuit of the present invention, including three by three a control unit of the array, wherein each control unit provides a control signal to an interconnecting transistor corresponding to one of the X-Y arrays; and FIG. 33C shows an embodiment of the control circuit of the present invention, including an array of control units, Line, bit line and bit line bar.

100. . . Array

101. . . CPS programmatic connection

X1 to X4. . . wire

Y1 to Y4. . . wire

Claims (103)

An integrated circuit comprising: a first wire; a second wire; a controllable interconnection device coupled between the first and second wires; and a control circuit for controlling the interconnection device In the state, the control circuit comprises a chalcogenide material, wherein the chalcogenide material comprises a threshold switching material. The integrated circuit of claim 1, wherein the chalcogenide material comprises a phase change material. The integrated circuit of claim 1, wherein the control circuit comprises a phase change material in series with a threshold switching material. The integrated circuit of claim 1, wherein the control circuit comprises a phase change memory component. The integrated circuit of claim 1, wherein the control circuit includes a threshold switching element. The integrated circuit of claim 1, wherein the control circuit comprises a phase change memory element in series with a threshold switching element. The integrated circuit of claim 1, wherein the control circuit comprises a first phase change memory element, the first phase change memory element being in series with a second phase change memory element. The integrated circuit of claim 1, wherein the control circuit comprises a first threshold switching element, the first threshold switching element being in series with a second threshold switching element. The integrated circuit of claim 1, wherein the control circuit comprises a phase change memory element in series with a transistor. The integrated circuit of claim 1, wherein the control circuit comprises a threshold switching element, the threshold switching element being in series with a transistor. The integrated circuit of claim 1, wherein the control circuit comprises a threshold switching element, the threshold switching element being connected in series with a phase change memory element, the phase change The memory element is connected in series with a transistor. The integrated circuit of claim 1, wherein the control circuit comprises a first transistor, the first transistor being cross-coupled to a second transistor. The integrated circuit of claim 12, wherein the control circuit comprises a first threshold switching element and a second threshold switching element, the first threshold switching element being connected in series with the first transistor and the second threshold A switching element is connected in series with the second transistor. The integrated circuit of claim 13, wherein the control circuit comprises a first phase change memory component and a second phase change memory component, wherein the first phase change memory component is connected in series with the first threshold switching component. The second phase change memory element is in series with the second threshold switching element. The integrated circuit of claim 12, wherein the control circuit comprises a first phase change memory component and a second phase change memory component, wherein the first phase change memory component is connected in series with the first transistor A two phase change memory element is connected in series with the second transistor. The integrated circuit of claim 1, wherein the control circuit comprises a first inverter, the first inverter is alternately coupled to a second inverter. The integrated circuit of claim 16, wherein the first inverter comprises a first transistor and the second inverter comprises a second transistor, and the first transistor is coupled to a first load, And the second transistor is coupled to a second load. The integrated circuit of claim 1, wherein the chalcogenide material is in series with an access device. The integrated circuit of claim 1, wherein the chalcogenide material is in series with an active device. The integrated circuit of claim 1, wherein the integrated circuit is a programmable logic device. The integrated circuit of claim 1, wherein the first wire crosses the second wire. The integrated circuit of claim 1, wherein the control circuit comprises a memory list yuan. The integrated circuit of claim 1, wherein the chalcogenide material is in series with a collapse layer. The integrated circuit of claim 23, wherein the breakdown layer comprises a dielectric material. The integrated circuit of claim 1, wherein the threshold switching material is not a phase change material. The integrated circuit of claim 1 further includes a charge pump coupled to the control circuit. The integrated circuit of claim 1, wherein the controllable interconnect device component comprises a control terminal for controlling a state of the interconnect device, the control circuit being coupled to the control terminal. The integrated circuit of claim 1, wherein the controllable interconnect device comprises a transistor. The integrated circuit of claim 28, wherein the transistor system is coupled between the first wire and the second wire. The integrated circuit of claim 29, wherein the electro-crystalline system is a MOS transistor. The integrated circuit of claim 1, wherein the interconnection device is a transistor. The integrated circuit of claim 31, wherein the electro-crystalline system is a MOS transistor. The integrated circuit of claim 1, wherein the controllable interconnect device is a controllable impedance device. The integrated circuit of claim 1, wherein the interconnect device is a controllable switch. The integrated circuit of claim 1, wherein the interconnect device is a controllable 矽 rectifier. The integrated circuit of claim 1, wherein the control circuit is not coupled between the first wire and the second wire. An electrical device comprising: a first wire; a second wire; a controllable interconnection device coupled between the first and second wires; a control circuit providing a control signal to the interconnection device to control a state of the interconnection device, the control circuit including at least A phase change memory component and at least one threshold switching component. The electrical device of claim 37, wherein the control circuit comprises a phase change memory component. The electrical device of claim 38, further comprising an active device in series with the phase change memory component. The electrical device of claim 39, wherein the active device is a transistor or a diode. The electrical device of claim 37, further comprising an active device in series with the threshold switching element. The electrical device of claim 41, wherein the active device is a transistor or a diode. The electrical device of claim 37, wherein the control circuit comprises a phase change memory component in series with a threshold switching component. The electrical device of claim 43, wherein the control signal is provided by a node between the phase change memory component and the threshold switching component. The electrical device of claim 37, wherein the control circuit comprises a first phase change memory component in series with a second phase change memory component. The electrical device of claim 37, wherein the control circuit includes a first threshold switching element, the first threshold switching element being coupled in series with a second threshold switching element. The electrical device of claim 37, wherein the control circuit further comprises a first transistor, the first transistor is coupled to a second transistor, the first transistor is coupled to a first load, the second The crystal is coupled to a second load, the first load includes a first threshold switching component and/or a first phase change memory component, and the second load includes a second threshold switching component and/or a first Two-phase change memory component. The electrical device of claim 47, wherein the first load comprises the first threshold switching element and the second load comprises the second threshold switching element. The electrical device of claim 47, wherein the first load comprises the first phase change memory component and the second load comprises the second phase change memory component. The electrical device of claim 47, wherein the first load comprises the first threshold switching element, the first threshold switching element is in series with the first phase change memory element, and the second load comprises the second threshold a switching element, the second threshold switching element being in series with the second phase change memory element. The electrical device of claim 47, wherein the first load comprises a first additional transistor, the first additional transistor being in series with the first threshold switching element and/or the first phase change memory element, the The second load includes a second additional transistor in series with the second threshold switching element and/or the second phase change memory element. The electrical device of claim 37, wherein the control circuit comprises a first inverter, the first inverter is interleaved and coupled to a second inverter, the first inverter comprises a first memory component and And a first threshold switching element, the second inverter comprising a second memory element and/or a second threshold switching element. The electrical device of claim 37, further comprising a voltage regulator coupled to the control circuit. The electrical device of claim 37 further comprising a charge pump coupled to the control circuit. The electrical device of claim 37, wherein the threshold switching element comprises an S-type threshold switching material. The electrical device of claim 37, wherein the threshold switching element comprises a chalcogenide threshold switching material. The electrical device of claim 37, wherein the phase change memory element comprises a chalcogenide phase change material. The electrical device of claim 37, wherein the electrical device is a programmable logic device. The electrical device of claim 47, wherein the first electro-crystalline system is a MOS transistor and the second electro-crystalline system is a MOS transistor. The electrical device of claim 37, wherein the first conductor is one of a plurality of first conductors of a matrix array and the second conductor is one of a plurality of second conductors of the matrix array. The electrical device of claim 37, wherein the interconnect device comprises a transistor. The electrical device of claim 61, wherein the electro-optic system is coupled between the first wire and the second wire. The electrical device of claim 62, wherein the electro-crystalline system is a MOS transistor. The electrical device of claim 37, wherein the interconnect device is a transistor. The electrical device of claim 64, wherein the electro-crystalline system is a MOS transistor. The electrical device of claim 37, wherein the interconnect device is a controllable impedance device. The electrical device of claim 37, wherein the interconnect device is a controllable switch. The electrical device of claim 37, wherein the interconnect device is a controllable xenon rectifier. A programmable logic device comprising: a plurality of first wires; a plurality of second wires; a plurality of controllable interconnecting devices, each interconnecting device being coupled to a corresponding first wire and a corresponding first Between the two wires; and a plurality of control units, each control unit controls the state of a corresponding interconnecting device, each control unit comprising a chalcogenide material, wherein the chalcogenide material of each control unit comprises a threshold switching material. The logic device of claim 69, wherein the chalcogenide material of each control unit comprises a phase change material. The logic device of claim 69, wherein each control unit comprises a phase change material in series with a threshold switching material. The logic device of claim 69, wherein the first wires are oriented in a first direction and the second wires are oriented in a second direction. The logic device of claim 69, wherein each of the interconnecting devices comprises a transistor, each of the transistors being coupled between the corresponding first and second wires. The logic device of claim 73, wherein each of the electro-crystalline systems is a MOS transistor. The logic device of claim 73, wherein each of the interconnect devices is a transistor. The logic device of claim 75, wherein each of the electro-crystalline systems is a MOS transistor. The logic device of claim 69, wherein each of the interconnect devices is a controllable switch. The logic device of claim 69, wherein each of the interconnect devices is a controllable 矽 rectifier. The logic device of claim 69, wherein each of the interconnection devices includes a control terminal for controlling the state of the interconnection device, and each control unit is coupled to a corresponding control terminal of the corresponding interconnection device. The logic device of claim 69, wherein the threshold switching material is not a phase change material. A programmable logic device comprising: a plurality of first wires; a plurality of second wires; a plurality of controllable interconnecting devices, each interconnecting device being coupled to a corresponding first wire and a corresponding first Between two wires; and a plurality of control units, each control unit controls the state of a corresponding interconnect device, each control unit comprising a phase change memory component and a threshold switching component. The logic device of claim 81, wherein each control unit comprises a phase change memory component. The logic device of claim 81, wherein each control unit comprises a phase change memory element in series with a threshold switching element. The logic device of claim 81, wherein the first conductors are oriented in a first direction and the second conductors are oriented in a second direction. The logic device of claim 81 further includes a plurality of access devices, each memory device being in series with a corresponding access device. The logic device of claim 85, wherein the access device is a transistor, a diode, or a threshold switching element. The logic device of claim 81, wherein each phase change memory component comprises a chalcogenide phase change material. The logic device of claim 81, wherein each phase change memory component comprises a chalcogenide threshold switching material. The logic device of claim 81, wherein each of the interconnecting devices comprises a corresponding transistor, and each corresponding electro-optic system is coupled between the corresponding first and second wires. The logic device of claim 89, wherein each corresponding electro-crystalline system is a MOS transistor. The logic device of claim 81, wherein each of the interconnecting devices is coupled to a transistor between the corresponding first and second wires. The logic device of claim 91, wherein each of the electro-crystalline systems is a MOS transistor. The logic device of claim 81, wherein each of the interconnect devices is a controllable switch. The logic device of claim 81, wherein each of the interconnect devices is a controllable 矽 rectifier. A method of operating a programmable logic device, the device comprising an X-ray, a Y-line, a controllable interconnection device coupled between the X-ray and the Y-line, and controlling the controllable switching element a control circuit of the state, the control circuit comprising a chalcogenide device, the method comprising: providing the controllable interconnection device; providing the control circuit, the control circuit comprising the chalcogenide device, wherein the chalcogenide The device includes a threshold switching element, a first state of the chalcogenide device is an on state of the threshold switching element, and a second state of the chalcogenide device is an off state of the threshold switching element; And causing the interconnect device to be in a first state by causing the chalcogenide device to be in the first state; and causing the interconnect device to be in a second state by placing the chalcogenide device in the second state . The method of claim 95, wherein the chalcogenide device comprises a phase change memory device, the first state of the chalcogenide device being a first resistance state of the phase change memory device, and the chalcogenide device The second state is a second resistance state of one of the memory elements. The method of claim 96, wherein the first resistance state is a set state of the memory component, and the second resistance state is a reset state of the memory component. The method of claim 95, wherein the interconnecting device comprises a transistor coupled between the first and second wires. The method of claim 98, wherein the electro-crystalline system is a MOS transistor. The method of claim 95, wherein the interconnecting device is a transistor. The method of claim 100, wherein the electro-crystalline system is a MOS transistor. The method of claim 95, wherein the interconnect device is a controllable 矽 rectifier. The method of claim 95, wherein the interconnecting device is a controllable switch.