TWI470605B - Display devices and pixel driving methods - Google Patents

Description

Display and driver pixel method

The present disclosure relates to a display, and more particularly to a pixel drive circuit.

The organic light emitting diode (Organic Light Emitting Diode) is generally used to store charges by using a Thin Film Transistor (TFT) with a storage capacitor to control an Organic Light Emitting Diode (OLED). The brightness performance. Please refer to FIG. 1 , which is a schematic diagram of a conventional pixel circuit. The pixel circuit 100 is described by taking an (N-type) thin film transistor 102, a storage capacitor 104, and an organic light-emitting diode 106 as an example. The two ends of the storage capacitor 104 are connected between the gate G and the source S of the thin film transistor 102, and the capacitance across the voltage system is denoted as Vgs. The anode of the organic light-emitting diode 106 is coupled to the source S of the thin film transistor 102, and its potential is denoted as VOLED. The above structure controls the current flowing through the thin film transistor 102 by the capacitance across the voltage Vgs (also the gate voltage across the gate), that is, the current flowing through the organic light emitting diode 106 IOLED=K*(Vgs-Vth)^2 . The capacitance across the voltage Vgs is the voltage difference between the data signal Vdata and the potential VOLED of the anode end of the organic light emitting diode. Therefore, the brightness performance of the light-emitting diode 106 can be controlled by providing different data signals Vdata.

However, in actual operation, the thin film transistor 102 generates a shift (Shift) of the threshold voltage Vth. This offset is related to the process of the thin film transistor, the operation time, the magnitude of the current flowing, and the like. Therefore, for all the pixels on the entire display panel, the difference in on-time, on-current, and process of each of the thin-film transistors 102 causes the critical voltage shift between the thin film transistors 102 for driving. The quantities are different, so that the luminance of each pixel does not maintain the same correspondence with the received pixel voltage. This will result in uneven brightness of the picture. Therefore, there is a need for a pixel driving circuit and a pixel driving method to solve the problem of the threshold voltage shift of the thin film transistor.

In view of the above, the present disclosure provides a display comprising: a pixel driving circuit comprising: a first switching element having a first end coupled to a first node and a second end of a light emitting element, and A control terminal is coupled to a second node; a second switching component has a first end coupled to a first signal source, a second end coupled to the first end of the first switching component, and a control terminal The first switching signal is coupled to a first signal source, the second terminal is coupled to the second signal source, the second terminal is coupled to the second node, and the control terminal is coupled to the first a second scan signal having a first end coupled to a third node, a second end coupled to a ground end, and a control end coupled to the second scan signal line; a capacitor coupled between the second node and the third node; and a second capacitor coupled between the first node and the third node.

The disclosure also provides a driving pixel method for applying to a pixel array, comprising: cutting off the third and fourth switching elements of all pixels according to the second scanning signal during a reset period, and according to the first scanning The signal turns on the second switching elements of all the pixels, so that the voltages stored by the first and second capacitors are drained to a low voltage level by the first and second switching elements; and one of the compensation periods after the reset period Applying a first reference voltage level and a second reference voltage level to the control terminal and the first terminal of the first switching element of all the pixels, so that the first switching element increases according to the first reference voltage level. The voltage level of a node to a compensation level, wherein the second reference voltage level is greater than or equal to the first reference voltage level, and the compensation level is the reference voltage level minus the threshold voltage; one of the data carriers after the compensation period In the period of the input, the second switching element is turned off according to the first scan signal, so that the third switching element loads the reference voltage level of the second signal source and the corresponding data signal according to the second scan signal. A capacitor; and after one cycle on emission data load period, generates a driving current to the light emitting element according to the voltage level stored in the first capacitor is formed by a first switching element for driving the light emitting element.

The above and other objects, features, and advantages of the present invention will become more apparent and understood.

The following description is the best mode for carrying out the invention. It will be appreciated by those skilled in the art that a number of changes, substitutions and substitutions can be made without departing from the spirit and scope of the invention. The scope of the invention is determined by the scope of the appended claims.

FIG. 2 is an embodiment of the pixel driving circuit 200 of the present disclosure. As shown in FIG. 2, the pixel driving circuit 200 is configured to generate a driving current Id to a light emitting element ED such that the light emitting element ED emits light according to the driving current Id. In the disclosed embodiment, the light emitting element ED is an Organic Light Emitting Diode (OLED). The pixel driving circuit 200 includes switching elements T1 to T4 and capacitors C1 to C2. In the embodiment of the present disclosure, the switching elements T1 to T4 may be InGaZnO thin film transistors (IGZO TFTs), but are not limited thereto, and the switching elements T1 to T4 of the present disclosure may be any N type. Thin film transistors are used to achieve this.

In detail, the switching element T1 has a first end D1 (drain) coupled to the second end S2 of the switching element T2, a second end S1 (source) coupled to a node N2 and a light emitting element ED, and a control end G1 (gate) is coupled to a node N1. The switching element T2 has a first terminal D2 (drain) coupled to a signal source PVDD1, a second terminal S2 (source) coupled to the first terminal D1 of the switching element T1, and a control terminal G2 (gate) coupled Up to a scan signal line scan2. The switching element T3 has a first terminal D3 (drain) coupled to a signal source PVDD2, a second terminal S3 (source) coupled to the node N1, and a control terminal G3 (gate) coupled to a scan signal Line Scan1. The switching element (T4) has a first terminal D4 (drain) coupled to a node N3, a second terminal S4 (source) coupled to a ground terminal, and a control terminal G4 (gate) coupled to the scan Signal line scan1. The capacitor C1 is coupled between the node N1 and the node N3. The capacitor C2 is coupled between the node N2 and the node N3.

FIG. 3 is a timing diagram of the scanning signals SS1 and SS2 and the signal sources PVDD1 and PVDD2 of the present disclosure for explaining the pixel driving circuit 200. As shown in FIGS. 2 and 3, a frame period sequentially includes a reset period P1, a compensation period P2, a data loading period P3, and an illumination period P4. When the pixel driving circuit 200 operates in the reset period P1, the scan signal SS2 outputted by the scan signal line Scan2 is a high voltage level VDD, and the scan signal SS1 output by the scan signal line Scan1 is a low voltage level Vlow. The switching elements T3, T4 are operated in an off state (off state), and the switching element T2 is operated in an on state (on state). Since the previous period of the reset period P1 is the lighting period, the capacitor C1 still has the voltage level of the previous period (for example, the reference voltage level Vref + the data signal Vdata), so that the switching element T1 is now in the on state. Since the signal sources PVDD1 and PVDD2 are at a low voltage level Vlow, the switching elements T1 and T2 discharge the voltage level of the node N2 to the signal source PVDD1 (low voltage level) to the low voltage level Vlow, and The continuous voltage characteristic makes the voltage level of the node N1 be effectively coupled to the low voltage level Vlow, so the switching element T1 is changed from the on state to the off state, and the nodes N1 and N2 are reset to Low voltage level Vlow. In a preferred embodiment, the high voltage levels of SS1 and SS2 are higher than the high voltage levels of PVDD1 and PVDD1, and the low voltage levels of SS1 and SS2 are lower than the low voltage levels of PVDD1 and PVDD1.

When the compensation period P2 after the period P1 is reset, the scanning signal lines Scan1 and Scan2 output a high voltage level, so that the switching elements T2 to T4 are all operated in an on state. The signal source PVDD2 is a reference voltage level Vref, and the signal source PVDD1 is a voltage level higher than the reference voltage level Vref (for example, the high voltage level VDD), so that the switching element T3 increases the voltage level of the node N1 to the reference. The voltage level Vref is such that the switching element T1 transitions from the off state to the on state (because Vref>Vth), and the node N2, which is originally the low voltage level Vlow, is raised to a compensation level, wherein the compensation level is referenced. The voltage level Vref is reduced by the threshold voltage Vth (ie, Vref-Vth). Therefore, the voltage level difference between the nodes N1 and N2 is a threshold voltage Vth of the switching element T1 (that is, VN1 - VN2 = Vth).

It should be noted that the reference voltage level Vref is smaller than the sum of the threshold voltage Vth and a threshold voltage Voled0 of the light-emitting element ED (ie, Vref<Vth+Voled0), and the high voltage level VDD is greater than the reference voltage level Vref (ie, VDD>Vref) and greater than the reference voltage level Vref and the voltage level of the data signal Vdata (ie, VDD>Vref+Vdata).

During the data loading period P3 after the compensation period P2, the scan signal SS2 is changed from the high voltage level VDD to the low voltage level Vlow, so that the switching element T2 is in a turn-off state, and the switching element T3 is based on the scan signal. The scan signal SS1 of the line Scan1 loads the reference voltage level Vref of the signal source PVDD2 and the corresponding data signal Vdata into the capacitor C1. After the data signal Vdata is loaded into the capacitor C1, the scan signal SS1 is at the low voltage level Vlow, so that the switching elements T3 and T4 are operated in the off state. Therefore, after the data signal Vdata is loaded into the capacitor C1, the voltage level of the node N2 is maintained at Vref-Vth, and the voltage level of the node N1 is Vref+Vdata.

During the lighting period P4 after the data loading period P3, the scanning signals SS2 and SS1 are respectively the high voltage level VDD and the low voltage level Vlow, so that the switching elements T3 and T4 are operated in the off state, and the switching element T2 is operated in the on state. . The signal source PVDD1 is at a high voltage level VDD, and the voltage level of the signal source PVDD2 can be any voltage level. In the embodiment of the present disclosure, the signal source PVDD2 is at a low voltage level Vlow. Since the signal source PVDD1 is at the high voltage level VDD, the switching element T1 is operated in a saturation state for generating a driving current Id to the light emitting element ED according to the voltage level stored by the capacitor C1. Therefore, the light-emitting element ED can emit light in accordance with the drive current Id.

In detail, when the light-emitting element ED is in an on state, the voltage level of the node N2 is changed from Vref-Vth to Voled1, where Voled1 is a threshold voltage when the light-emitting element ED is in an on state. And because the voltage across the capacitor is continuous, the voltage level of the node N1 is changed from Vdata+Vth to (Vdata+Vref)+(Voled1-(Vref-Vth))=Vdata+Voled1+Vth. The gate voltage across the switching element T1 is Vgs=(Vdata+Voled1+Vth)-(Voled1)=(Vdata+Vth). Since the gate voltage of the switching element T1 is Vgs=Vdata+Vth>Vth, the voltage across the switching element T1 is Vds=VDD-Voled1>Vgs-Vth, so the switching element T1 operates in a saturated state, and the driving current Id is only The gate voltage of the switching element T1 is related. The drive current Id formula is as follows:

Id=K(Vgs-Vth) ² =K(Voled1+Vdata+Vth-Voled1-Vth) ² =K(Vdata) ²

Where K is the gain factor of the switching element T1. Obviously, when the light-emitting element ED is in an on state, the driving current Id and the threshold voltage Vth of the switching element T1 are independent of the open-circuit threshold voltage Voled1 of the light-emitting element ED, and are only related to the data signal Vdata, so the pixel driving circuit 200 does not The phenomenon of uneven brightness is caused by the critical voltage variation of the transistor and the light-emitting element.

Figure 4 is another embodiment of the pixel drive circuit of the present disclosure. As shown in FIG. 4, the pixel driving circuit 400 is similar to the pixel driving circuit 200. The difference is that the first terminal D3 of the switching element T3 is coupled to the first terminal D2 of the switching element T2, and the voltage levels of the signal sources PVDD1 and PVDD2 are The bits are the same and are coupled to the pixel driving circuit 400 by a single data signal line. In other words, the signal sources PVDD1 and PVDD2 of Fig. 1 are combined into a signal source PVDD3, and one pixel has only a single data signal line.

FIG. 5 is a timing chart of the scanning signals SS1, SS2 and the signal source PVDD3 of the present disclosure for illustrating the pixel driving circuit 400. The timings of the scanning signals SS1 and SS2 in FIG. 5 are the same as the timings of the scanning signals SS1 and SS2 in FIG. 3, with the difference that the voltage level of the signal source PVDD3 is low when the pixel driving circuit 400 operates in the reset period P1. Voltage level Vlow. During the compensation period P2, the voltage level of the signal source PVDD3 is the reference voltage level Vref. During the data loading period P3, the voltage level of the signal source PVDD3 is the reference voltage level Vref plus the data signal Vdata. During the lighting period P4, the voltage level of the signal source PVDD3 is the high voltage level VDD. The operation of the other components is as described above (for example, the description of FIG. 3), and will not be described again here. The benefit of combining the signal sources PVDD1 and PVDD2 into the signal source PVDD3 is to reduce the number of data signal lines in order to reduce the complexity and cost of the circuit design.

Figure 6 is a display panel of the present invention. As shown in FIG. 6, the display panel (also referred to as display) 600 includes a pixel array 610, a scan driver 620, a data driver 630, and a reference signal generator 640. For example, the pixel array 610 includes a plurality of pixels, each of which includes a pixel driving circuit 200 as shown in FIG. 2 or a pixel driving circuit 400 shown in FIG.

The scan driver 620 is configured to provide a scan signal to the pixel array 610 such that the scan signal line is driven or disabled, and the data driver 630 is configured to provide a data signal to the pixel drive circuit in the pixel array 610. The reference signal generator 640 is configured to provide a reference signal to the pixel driving circuit 200 (or the pixel driving circuit 400) of the pixel array 610, and may also be integrated into the scanning driver 620. It should be noted that the display panel 600 can be an organic light emitting diode (OLED) display panel, but can also be applied to other types of display panels, such as liquid crystal (LCD) display panels.

In addition, if the pixel array 610 includes the pixel driving circuit 200 shown in FIG. 2, each row of the pixel array 610 includes two different data signal lines for respectively coupling the signal sources PVDD1 and PVDD2 to the drawing. Driving circuit 200. If the pixel array 610 includes the pixel driving circuit 400 shown in FIG. 4, each row of the pixel array 610 only needs to include a single scanning signal line for coupling the signal source PVDD3 to the pixel driving circuit 400.

Figure 7 is an electronic device of the present invention. As shown, the electronic device 700 uses the display panel 600 shown in FIG. 6. The electronic device 700 can be, for example, a PDA, a notebook, a tablet, a mobile phone, a display, etc. .

In general, the electronic device 700 includes a housing 710, a display panel 600, and a power supply 720. Although the electronic device 700 also includes other components, it will not be described here. In operation, the power supply 720 is used to supply power to the display panel 600 such that the display panel 600 can display images.

FIG. 8 is a flow chart of the pixel driving method of the present disclosure, which is applicable to the pixel array 610. As shown in FIG. 8, when the pixel array 610 operates in the reset period P1, the process proceeds to step S81, the switching elements T3 and T4 of all the pixels are turned off, and the switching elements T2 of all the above pixels are turned on, so that the capacitors C1 and C2 are turned on. The stored voltage is drained to a low voltage level by switching elements T1 and T2. When the pixel array 610 operates in the compensation period P2 after the reset period P1, the process proceeds to step S82, where a reference voltage level Vref and a first terminal D1 are applied to the control terminal G1 and the first terminal D1 of all the pixel switching elements T1, respectively. The reference voltage level Vref1 is such that the switching element T1 increases the voltage level of the node N2 to a compensation level according to the reference voltage level Vref, wherein the reference voltage level Vref1 is greater than or equal to the reference voltage level Vref, and the compensation level is the reference voltage. The level Vref is reduced by the threshold voltage Vth (Vref - Vth). Therefore, the voltage level of the control terminal G1 of the switching element T1 and the second terminal S1 are different by a threshold voltage Vth value, so that the threshold voltage variation Vth caused by the switching elements T1 of all pixels can be simultaneously compensated. In other words, since the step S82 is to synchronously compensate the threshold voltage variations of all the switching elements T1 in the pixel array 610, the pixel driving circuits 200 and 400 are synchronous compensation pixel driving circuits.

When the pixel array 610 operates in the data loading period P3 after the compensation period P2, the process proceeds to step S83, and the switching element T2 is turned off according to the scanning signal line Scan2, so that the switching elements T3 of all the pixels are sequentially ordered according to the corresponding scanning signal SS1. The reference voltage level Vref outputted by the signal source PVDD2 and the corresponding data signal Vdata are loaded into the capacitor C1. When the pixel array 610 operates in the lighting period P4 after the data loading period P3, the process proceeds to step S84, in which the switching elements T1 of all the pixels synchronously generate the driving current Id to the light-emitting element ED according to the voltage level stored by the capacitor C1. Therefore, the light-emitting elements ED of all the pixels are simultaneously illuminated according to the driving current Id. In other words, the pixel driving circuits 200 and 400 are synchronous light-emitting pixel driving circuits.

Figure 9 is a timing diagram of a general progressive drive circuit, and Figure 10 is a timing diagram of the pixel drive circuit of the present disclosure, R is the illumination period of the right field of view, and L is the illumination period of the left field of view. As shown in Fig. 9, the illumination period of each column is less than about 4 ms, and the shutter switching period SSP (when the entire frame is the ink-blocking period) is about 2.5 ms. As shown in FIG. 10, since the pixel driving circuit of the present disclosure is a synchronous emission type and a synchronous compensation type pixel driving circuit, the light emission time is longer than 4 ms, and the gate switching period SSP is about 4 ms. Compared with the progressive driving circuit, the frame driving period of the pixel driving circuit of the present disclosure is long, which is advantageous for the switching of the glasses shutter of the shutter type stereoscopic display glasses.

In summary, since the display panel 600 and the pixel driving circuits 200 and 400 of the present disclosure are synchronous illumination driving circuits, the lighting period is longer than that of the progressive lighting driving circuit. In addition, since the display panel 600 of the present disclosure synchronously compensates for the threshold voltage variation of all pixels, the full-screen blanking period is longer than that of the progressive lighting driving circuit, so the shutter glasses have enough time to switch in the black screen. Since the present disclosure uses an N-type thin film transistor, an indium gallium zinc oxide thin film transistor having high resolution, low power consumption, fast reaction speed, and high color saturation can be used to drive the light-emitting element. In addition, since the pixel drive circuit 400 of the present disclosure requires only one voltage source, no additional data signal lines are required, thereby reducing circuit complexity and manufacturing cost.

The features of many embodiments are described above to enable those of ordinary skill in the art to clearly understand the form of the specification. Those having ordinary skill in the art will appreciate that the objectives of the above-described embodiments and/or advantages consistent with the above-described embodiments can be accomplished by designing or modifying other processes and structures based on the present disclosure. It is also to be understood by those skilled in the art that <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt;

100. . . Pixel circuit

102. . . Thin film transistor

104. . . Storage capacitor

106. . . Organic light-emitting diode

Vgs. . . Brake source cross pressure

S. . . Source

D. . . Bungee

G. . . Gate

IOLED. . . Current

VOLED. . . Potential

200, 400. . . Pixel drive circuit

T1~T4. . . Switching element

C1, C2. . . Capacitor

N1~N3. . . node

Scan1, Scan2. . . Scanning signal line

SS1, SS2. . . Scanning signal

PVDD1, PVDD2, PVDD3. . . signal source

D1~D4. . . First end

S1~S4. . . Second end

G1~G4. . . Control terminal

ED. . . Light-emitting element

Vdata. . . Data signal

Vth. . . Threshold voltage

Vref. . . Reference voltage level

Vlow, Vss. . . Low voltage level

VDD, Vdd. . . High voltage level

Id. . . Drive current

P1. . . Reset cycle

P2. . . Compensation period

P3. . . Data loading cycle

P4. . . Luminous cycle

600. . . Display panel

610. . . Pixel array

620. . . Scan drive

630. . . Data driver

640. . . Reference signal generator

700. . . Electronic device

710. . . shell

720. . . Power Supplier

SSP. . . Gate switching cycle

Figure 1 is a schematic diagram of a conventional pixel circuit;

Figure 2 is an embodiment of the pixel driving circuit of the present disclosure;

Figure 3 is a timing diagram of the scan signals SS1, SS2 and the signal sources PVDD1, PVDD2 of the present disclosure;

Figure 4 is another embodiment of the pixel driving circuit of the present disclosure;

Figure 5 is a timing diagram of the scanning signals SS1, SS2 and the signal source PVDD3 of the present disclosure;

Figure 6 is a display panel of the present disclosure;

Figure 7 is an electronic device of the present disclosure;

Figure 8 is a flow chart of the pixel driving method of the present disclosure;

Figure 9 is a timing diagram of a general progressive drive circuit;

Figure 10 is a timing diagram of the pixel driving circuit of the present disclosure.

200. . . Pixel drive circuit

T1~T4. . . Switching element

C1, C2. . . Capacitor

N1~N3. . . node

Scan1, Scan2. . . Scanning signal line

PVDD1, PVDD2. . . signal source

S1~S4. . . First end

D1~D4. . . Second end

G1~G4. . . Control terminal

Id. . . Drive current

ED. . . Light-emitting element

Claims (15)

A display comprising: a pixel driving circuit comprising: a first switching element having a first end coupled to a first node and a second end of a light emitting element; and a control end coupled to the first a second switching element having a first end coupled to a first signal source, a second end coupled to the first end of the first switching element, and a control end coupled to a first scan a signal line; a third switching element having a first end coupled to a second signal source, a second end coupled to the second node, and a control end coupled to a second scan signal line; The fourth switching element has a first end coupled to a third node, a second end coupled to a ground end, and a control end coupled to the second scan signal line; a first capacitor coupled to the a second node is coupled between the first node and the third node; and a second capacitor is coupled between the first node and the third node. The display device of claim 1, wherein the second switching element operates in a conducting state according to a first scanning signal of the first scanning signal line during a reset period, and the third and fourth The switching element operates in an off state according to a second scan signal of the second scan signal line, so that the first and second switching elements are according to the first The second signal source discharges the voltage level of the first node to a low voltage level, and the first and second capacitors discharge the second node to the low voltage level. The display device of claim 2, wherein the second, third, and fourth switching elements are respectively in an on state according to the first and second scan signals, respectively, at one of the compensation periods after the reset period The third switching element is configured to increase a voltage level of the second node to a reference voltage level according to the second signal source, and turn on the first switching element, so that the first switching element is configured according to the first signal source. The first node is increased to a compensation level, wherein the reference voltage level is less than a sum of a first threshold voltage and a second threshold voltage of the light-emitting element, a high voltage level is greater than the reference voltage level, and The compensation level is the reference voltage level minus the first threshold voltage. The display device of claim 3, wherein, in one of the data loading periods after the compensation period, the second switching element operates in an off state according to the first scan signal, so that the third switching element is according to the above The second scan signal loads the reference voltage level of the second signal source and the corresponding data signal into the first capacitor. The display device of claim 4, wherein the third and fourth switching elements are operated in an off state according to the second scan signal, and the second switch is in an illumination period after the data loading period The component is operated in an on state according to the first scan signal, so that the first switching component operates in a saturated state according to the first signal source, and generates a driving current to the light emitting component according to the voltage level stored by the first capacitor. In order to drive the above-mentioned light-emitting elements. The display device of claim 5, wherein the first end of the third switching element is coupled to the first end of the second switching element, so that the voltage levels of the first and second signal sources are the same and A single data signal line is coupled to the pixel driving circuit. The display device of claim 5, wherein the first and second signal sources are respectively coupled to the first end and the third end of the second switching element by different first and second data signal lines The first end of the switching element. The display of claim 1, wherein the first, second, third and fourth switching elements are N-type transistors. A driving pixel method for a display according to the first aspect of the invention, comprising: cutting off the third and fourth switching elements of all the pixels according to the second scanning signal during a reset period, and according to the above a scan signal turns on the second switching elements of all the pixels, so that the voltage stored by the first and second capacitors is discharged to the low voltage level by the first and second switching elements; a first reference voltage level and a second reference voltage level are respectively applied to the control end and the first end of the first switching element of each of the pixels, so that the first switch is The component increases the voltage level of the first node to a compensation level according to the first reference voltage level, wherein the second reference voltage level is greater than or equal to the first reference voltage level, and the compensation level is the above The first reference voltage level is reduced by a threshold voltage; according to one of the data loading periods after the compensation period, according to the above a scan signal is turned off the second switching element, so that the third switching element loads the first reference voltage level of the second signal source and the corresponding data signal into the first capacitor according to the second scan signal; During one of the light-emitting periods after the data loading period, the first switching element generates a driving current to the light-emitting element according to the voltage level stored by the first capacitor to drive the light-emitting element. The driving pixel method of claim 9, wherein the step of the resetting period further comprises: according to the voltage level of the first node, using the first and second capacitors to perform the second The voltage level of the node is equivalently coupled to the low voltage level described above. The driving pixel method of claim 10, wherein the step of the compensating cycle further comprises: conducting the second, third, and fourth switching elements respectively according to the first and second scanning signals, so that The third switching element increases the voltage level of the second node to the first reference voltage level according to the second scan signal. The driving pixel method of claim 11, wherein the step of the illuminating period further comprises: cutting off the third and fourth switching elements according to the second scanning signal; and conducting the above according to the first scanning signal. The second switching element is configured to operate the first switching element in a saturated state according to the first signal source, and generate a driving current to the light emitting element according to the voltage level stored by the first capacitor. The driving pixel method of claim 12, wherein the first end of the third switching element is coupled to the first end of the second switching element, so that the first and second signal sources are the same One of the first data signal lines is coupled to the above pixel. The driving pixel method of claim 12, wherein the first and second signal sources are coupled to the first end of the second switching element by different first and second data signal lines, respectively And the first end of the third switching element. The driving pixel method of claim 9, wherein the first, second, third, and fourth switching elements are N-type transistors.