TWI470328B - Display panel - Google Patents

Description

Display panel

The present invention relates to a display device, and more particularly to a display panel.

With the development of display technology, display panels have been widely used in various fields, such as mobile phones, tablets or digital cameras.

In the conventional method, the display panel has a scan driving chip and a data driving chip respectively disposed on both sides of the active area, and respectively wired into the active area to provide signals to the scan lines and data lines orthogonal to each other. However, such an approach requires sufficient space around the active area to be configured for scanning, data-driven wafers, and wiring. Under the trend that today's electronic products are gradually becoming lighter and shorter, the conventional practice is disadvantageous for realizing a narrow-frame display panel.

Therefore, in order to pursue a wider application of the display panel, it is necessary to propose a solution to the above problems.

One aspect of the present invention is to provide a display panel. According to an embodiment of the invention, the display panel includes a substrate, a plurality of first signal lines, a plurality of second signal lines, a plurality of pixel units, a plurality of transfer lines, and a driving wafer. The substrate has an active area including a plurality of pixel blocks. the first The signal lines are arranged in parallel on the substrate. The second signal lines are arranged in parallel on the substrate, and the first signal lines are interlaced with each other to define a pixel block, and the number of the second signal lines is greater than the number of the first signal lines. The pixel units are respectively disposed in the pixel block and are respectively connected to the first and second signal lines. The transmission lines are arranged in parallel on the substrate, and are respectively connected to the second signal lines, and traverse the opposite sides of the active area and parallel to the first signal lines. The driving chip includes a first pin second pin and a driving circuit. The first pin is connected to the first signal line. Link the transfer line. The driving circuit is configured to generate the first signal and the second signal to the first pin and the second pin, respectively. The first pin and the second pin interact and are evenly arranged such that the first signal line and the transfer line connected thereto do not overlap each other, and the transfer line is evenly disposed on the substrate.

According to an embodiment of the invention, the display panel further includes a plurality of pseudo transfer lines. The pseudo transfer lines are evenly disposed on the substrate, parallel to the transfer line and traversing opposite sides of the active area, wherein the transfer line is divided into a first transfer line and a second transfer line, and each of the pixel blocks passes thereon The number of the first transfer lines is the same, and each of the pixel blocks is passed by one of the second transfer lines or passed by one of the pseudo transfer lines.

According to an embodiment of the invention, the display panel further includes a common electrode and a control circuit. The common electrode is disposed on the substrate and located around the active region for connecting the dummy transfer line. The control circuit connects the common electrode and the driving wafer to provide a common electrode-off potential and drive the driving wafer.

According to an embodiment of the invention, the front projections of the dummy transmission line, the first transmission line, the second transmission line and the first signal line on the substrate do not overlap.

According to an embodiment of the present invention, a pixel block located between adjacent two of the pseudo transfer lines and not passed by the pseudo transfer line is defined as a plurality of central blocks Area, the number of pixel blocks in each central area is the same as each other.

According to an embodiment of the present invention, a pixel block located between the pseudo transfer line closest to the first boundary and the first boundary in the pseudo transfer line and not passed by the dummy transfer line is defined as a first boundary region. A pixel block located between the pseudo transfer line closest to the second boundary and the second boundary in the pseudo transfer line and not passed by the pseudo transfer line is defined as the second boundary area. The first and second boundaries are opposite boundaries of the active area, and the number of pixel blocks of the first boundary area and the second boundary area are the same.

According to an embodiment of the present invention, a pixel block located between the pseudo transfer line closest to the first boundary and the first boundary in the pseudo transfer line and not passed by the dummy transfer line is defined as the first boundary region. A pixel block located between the pseudo transfer line closest to the second boundary and the second boundary in the pseudo transfer line and not passed by the pseudo transfer line is defined as the second boundary area. The first and second boundaries are the opposite boundaries of the active area. The number of pixel blocks in the first boundary region and each of the central regions is the same, and the number of pixel blocks in the second boundary region is different.

According to an embodiment of the present invention, a pixel block located between adjacent two of the second transfer lines and not passed by the second transfer line is defined as a plurality of central regions, each of which is a pixel region The number of blocks is the same as each other.

According to an embodiment of the present invention, a pixel block located between the second transfer line closest to the first boundary and the first boundary in the second transfer line and not passed by the second transfer line is defined as the first boundary region . A pixel block located between the second transfer line and the second boundary closest to a second boundary in the second transfer line and not passed by the second transfer line is defined as a second boundary region. The first and second boundaries are the opposite boundaries of the active area. First boundary area and The number of pixel blocks in the two boundary regions is the same.

According to an embodiment of the present invention, a pixel block located between the second transfer line closest to the first boundary and the first boundary in the second transfer line and not passed by the second transfer line is defined as the first boundary region . A pixel block located between the second transfer line closest to the second boundary and the second boundary in the second transfer line and not passed by the second transfer line is defined as the second boundary region. The first and second boundaries are the opposite boundaries of the active area. The number of pixel blocks in the first boundary region and each of the central regions is the same, and the number of pixel blocks in the second boundary region is different.

Therefore, by applying the above embodiment, it is possible to realize a display panel having a narrow bezel. The use of a transfer line to transmit a second signal can replace the traditional approach to narrow the border. By alternately and evenly arranging the pins of the driving chip, the first signal line and the transmission line can be made to overlap each other, and stray capacitance between the lines can be avoided and the capacitive coupling effect can be avoided. In addition, through the configuration, the pseudo transfer line, the first transfer line, and the second transfer line and the front projection of the first signal line on the substrate are not overlapped, and the parasitic capacitance between the lines is avoided. In addition, the average configuration of the pseudo transfer line and the second transfer line can increase the picture load on the display panel to improve the picture quality.

The spirit and scope of the present disclosure will be apparent from the following description of the preferred embodiments of the present disclosure. Modifications do not depart from the spirit and scope of the disclosure.

FIG. 1 is a schematic view of a display panel 100 according to an embodiment of the invention. The display panel 100 includes a substrate 110, a plurality of first signal lines 120, a plurality of second signal lines 122, a plurality of pixel units 130, a plurality of transfer lines 140, 142, and a driving wafer 150. It should be noted that the first signal line 120 and the second signal line 122 are respectively a data line and a scan line. When the first signal line 120 is a data line, the second signal line 122 is a scan line, and vice versa. .

Structurally, substrate 110 has an active region 112 that includes a plurality of pixel blocks 114. The first signal lines 120 are arranged in parallel on the substrate 110. The second signal lines 122 are disposed on the substrate 110 in parallel, and the first signal lines 120 are interleaved with each other to define the pixel block 114, and the number of the second signal lines 122 is greater than the number of the first signal lines 120. The pixel units 130 are respectively disposed in the pixel block 114 and are respectively connected to the first and second signal lines 120 and 122. The pixel unit 130 may include a switch (which may be a thin film transistor), a storage capacitor and a pixel electrode. When the switch is turned on by the scan line, the storage capacitor may be charged by the data potential on the data line, and the data potential is continuously supplied after the switch is turned off. Give the pixel electrode. The transmission lines 140 and 142 are disposed on the substrate 110 in parallel, and traverse the opposite sides of the active region 112 and parallel to the first signal lines 120. The driver wafer 150 includes a first pin 152, a second pin 154, and a drive circuit 156. The first pin 152 is connected to the first signal line 120. The second leg 154 connects the transfer lines 140, 142. The driving circuit 156 is configured to generate the first signal and the second signal to the first pin 152 and the second pin 154, respectively. The first pin 152 and the second pin 154 are alternately arranged, and the first signal line 120 and the transmission lines 140 and 142 connected thereto are not overlapped with each other, and the transfer lines 140 and 142 are evenly disposed on the substrate 110. on. worth it It is noted that the transfer lines 140, 142 may be connected to the second signal line 122 by means of a perforation or a connection plug. In addition, the first and second signals herein may be data signals and scanning signals, respectively, which may be represented by different potentials. For example, the data signals can be -15V, 0V, +15V, which can represent three different levels of gray scale, respectively, and the scan signals can be -20V and +22V, which can respectively control a row of pixel units 130. The switch (not shown) is turned on or off.

In this embodiment, the driving chip 150 can be an adjustable driving chip, and the specific pin can be determined as the first pin 152 or the second pin by the driving circuit 156 giving a specific signal to a specific pin. Bit 154. For example, when the driving chip 150 is given a scan signal of a specific pin -20V or +22V through the driving circuit 156, the specific pin can be connected to the scan line for the scan pin. In other words, the driving chip 150 can be given a different potential to any of the pins by the driving circuit 156, so that the pin can be connected to the scan line or the data line according to the actual needs of the hardware. For example, five different potentials can be given, namely -15V, 0V, +15V, -20V, +22V. The following table is a further illustration of the configuration of the driver chip 150 pin.

In the above table, G can represent the scan pin, and S can represent the data pin. If the ratio of the display panel 100 is 10x8, the pin 1 can be the scan pin, the pin 2 can be the data pin, and so on.

Therefore, by using the driving chip 150 to determine the specific pin position as the data pin or the scan pin according to actual needs, the first pin 152 and the second pin 154 can be alternately and evenly configured, and the first signal line is configured. 120. The transfer lines 140, 142 do not overlap each other, and the transfer lines 140, 142 are evenly disposed on the substrate 110.

The layout of the transmission lines 140 and 142 can reduce the frame of the display panel 100. By driving the pin configuration of the wafer 150, the transfer lines 140 and 142 can be overlapped with each other to avoid stray capacitance. As well as the capacitive coupling effect, on the other hand, the transfer lines 140, 142 can be evenly disposed on the substrate 110 to avoid the imbalance of the active region 112, resulting in uneven brightness and darkness.

However, despite the average configuration of the transfer lines 140, 142, the number of transfer lines 140, 142 passing through the different pixel blocks 114 will be different, resulting in an unbalanced load on the active area 112. Therefore, in other embodiments, the problem can be solved by setting the pseudo transfer line 160.

In an embodiment of the invention, the display panel 100 further includes a plurality of pseudo transfer lines 160. The dummy transfer lines 160 are disposed in parallel and evenly on the substrate 110, parallel to the transfer lines 140, 142 and traversing opposite sides of the active region 112. In this embodiment, the transfer lines 140, 142 can be further divided into a first transfer line 140 and a second transfer line 142, and the number of the first transfer lines 140 passing through each of the pixel blocks 114 is the same, and each A pixel block 114 is passed by a second transfer line 142 or by a pseudo transfer line 160. In other words, the first transfer lines 140 are arranged in the same number on each row of pixel blocks 114, and the number of second transfer lines 142 is insufficient to be arranged in each row of pixel blocks 114, so that no second configuration is provided. The pixel of the transfer line 142 On the block 114, the dummy transfer line 160 can be configured to avoid uneven brightness of the picture caused by the load imbalance of the active area 112.

In an embodiment of the invention, the display panel 100 further includes a common electrode 170 and a control circuit 180. The common electrode 170 is disposed on the substrate 110 and located around the active region 112 for connecting all the dummy transmission lines 160. The control circuit 180 connects the common electrode 170 and the driving wafer 150 to provide a common potential of the common electrode 170 and drive the driving wafer 150. It should be noted that the control circuit 180 can be implemented by a hardware circuit or a software body, or a part of a hardware part. In addition, the turn-off potential may be the potential of the scan signal to open the switch of the pixel unit 130, for example, -20V.

By turning off the potentials of all the pseudo transfer lines 160 as described above, the pseudo transfer lines 160 can be given the first and second transfer lines 140, 142 that are turned off, and the display panel 100 can be balanced and the screen brightness is averaged. In addition, by configuring all of the dummy transfer lines 160 to be connected to the common electrode 170, the pins of the drive wafer 150 can be saved, and the cost and complexity of driving the wafers 150 can be reduced.

2 is a cross-sectional view of the display panel of FIG. 1 along line 2-2 in accordance with an embodiment of the present invention. The orthographic projection P1 of the pseudo transmission line 160 on the substrate 110, the orthographic projection P2 of the first transmission line 140 on the substrate 110, the orthographic projection P3 of the second transmission line 142 on the substrate 110, and the first signal line 120 are on the substrate 110. The orthographic projections P4 on the top do not overlap. This setting avoids parasitic capacitance and capacitive coupling effects. It should be noted that the second diagram is only an example. The first signal line 120, the first transmission line 140, the second transmission line 142, and the pseudo transmission line 160 may be disposed on different circuit layers according to actual requirements, and are not shown in FIG. It is drawn as a limit.

In the embodiment of the present invention, since the second transmission line 142 transmits the second signal, and the pseudo transmission line 160 does not, in order to avoid the image unevenness caused by the load imbalance of the active area 112, the second transmission line 142 is required. The dummy transfer lines 160 are evenly disposed on the active area 112. In order to further understand the spirit of the average configuration, the following description will be specifically made by the different embodiments shown in FIGS. 3 to 6.

FIG. 3 is a schematic diagram showing the second transfer line 142 and the dummy transfer line 160 being evenly arranged in accordance with an embodiment of the present invention. As shown in FIG. 3, the active area 112 is formed by a matrix combination of 15x9 pixel blocks 114. The active region 112 has a first boundary 320 and a second boundary 330, and the first and second boundaries 320, 330 are opposite each other and parallel to the dummy transfer line 160. In this embodiment, the number of rows corresponding to the pixel block 114 is nine lines of the first transmission line 140, and the second signal line 122 is connected, and the second transmission line 142 is connected to the second signal line. 122, a total of six. The pseudo transmission line 160 can be disposed on the second, fifth, and eighth rows of the pixel block 114, and the second transmission line 142 can be disposed on the first, third, fourth, sixth, seventh, and 9 rows of pixels on block 114. By arranging the second transfer line 142 and the dummy transfer line 160 on average, the load imbalance of the active region 112 can be avoided.

If the pixel block 114 located between the adjacent two pseudo transfer lines 160 and not passed by the pseudo transfer line 160 is defined as the central area 310. Then, arranging the second transfer line 142 and the dummy transfer line 160 on average so that the number of the pixel blocks 114 in each of the central regions 310 is identical to each other. In this embodiment, the pixel blocks 114 in each central region 310 are thirty. The number of pixel blocks 114 in the central area 310 is made equal to each other, and the function thereof is to prevent the load imbalance of each central area 310 of the active area 112, otherwise the brightness and darkness are uneven. The situation will be extremely obvious.

If the pixel block 114 that is located between the pseudo transfer line 160 and the first boundary 320 that is closest to the first boundary 320 and is not passed by the dummy transfer line 160 is defined as the first boundary region 322, and the definition is located closest to the first The pixel block 114 between the pseudo transfer line 160 and the second boundary 330 of the second boundary 330 and not passed by the pseudo transfer line 160 is the second boundary area 332. Then, the second transfer line 142 and the dummy transfer line 160 are evenly arranged in such a manner that the number of the pixel blocks 114 in the first boundary region 322 and the second boundary region 332 can be identical to each other. In this embodiment, the pixel blocks 114 in the first and second boundary regions 322 and 332 are all fifteen. It should be noted that although the number of the pixel blocks 114 of the first and second boundary regions 322, 332 and the central region 310 is different, since the unevenness of the boundary regions 322, 332 is not easily perceived by the human eye, it is not easy to cause Obvious influence. In addition, it is noted that in other implementations, the number of pixel blocks 114 of the first and second boundary regions 322, 332 and the central region 310 may also be the same.

4 is a schematic diagram showing the second transfer line 142 and the dummy transfer line 160 being evenly arranged in accordance with an embodiment of the present invention. The embodiment and the previous embodiment are the same as the active area 112 of the 15x9 pixel block 114, so the same points are not described herein. The active region 112 has a first boundary 420 and a second boundary 430. In this embodiment, the dummy transmission line 160 can be disposed on the third, sixth, and ninth rows of the pixel block 114, and the second transmission line 142 can be disposed on the first, second, fourth, and fifth sides. The 7th and 8th rows are on the pixel block 114.

If the pixel block 114 located between the adjacent two pseudo transfer lines 160 and not passed by the pseudo transfer line 160 is defined as the central area 410, the pixel blocks 114 in each central area 410 in this embodiment are all It is thirty.

If the pixel block 114 that is located between the pseudo transfer line 160 and the first boundary 420 that is closest to the first boundary 420 and is not passed by the dummy transfer line 160 is defined as the first boundary region 422, and the definition is located closest to the first The pixel block 114 between the pseudo transfer line 160 and the second boundary 430 of the two boundary 430 and not passed by the pseudo transfer line 160 is the second boundary area 432, and the pixel block 114 in the first boundary area 422 For thirty, the pixel block 114 of the second boundary region 432 is zero. It should be noted that although the number of pixel blocks of the first boundary area 422 and each of the central areas 410 is the same in the present embodiment, and the number of pixel blocks of the second boundary area 432 is different, the boundary area is different. The unevenness of light and darkness of 432 is not easy to be perceived by the human eye, so it is not easy to cause obvious influence.

The embodiments shown in the third and fourth figures described above divide the active area 112 according to the configuration of the dummy transfer line 160, and the embodiments shown in the fifth and sixth figures below will be based on the second transfer line 142. The configuration divides the active area 112.

FIG. 5 is a schematic diagram showing the second transfer line 142 and the dummy transfer line 160 being evenly arranged in accordance with an embodiment of the present invention. As shown in FIG. 5, the active area 112 is formed by a combination of 12x9 pixel blocks 114 in a matrix. The active region 112 has a first boundary 520 and a second boundary 530, and the first and second boundaries 520, 530 are opposite each other and parallel to the dummy transfer line 160. In this embodiment, the number of rows corresponding to the pixel block 114 is nine lines of the first transmission line 140, and the second signal line 122 is connected, and the second transmission line 142 is connected to the second signal line. 122, a total of three. The second transfer line 142 can be disposed on the second, fifth, and eighth rows of the pixel block 114, and the opposite pseudo transfer line 160 can be disposed on the first, third, fourth, sixth, seventh, and 9 rows of pixels on block 114. The second transfer line 142 and the pseudo transfer line 160 are evenly arranged in such a manner that Active zone 112 load imbalance can be avoided.

If the pixel block 114 located between the adjacent two second transfer lines 142 and not passed by the second transfer line 142 is defined as the central region 510. Then the number of pixel blocks 114 in each central region 510 is the same as each other. In the present embodiment, the pixel blocks 114 in each of the central regions 510 are twenty-four. The number of pixel blocks 114 in the central region 510 is made equal to each other, and its function is to prevent the load imbalance of each central region 510 of the active region 112, otherwise the situation of uneven brightness and darkness will be extremely obvious.

If the pixel block 114 defined between the second transfer line 142 and the first boundary 520 that is closest to the first boundary 520 and is not passed by the second transfer line 142 is defined as the first boundary region 522, and the definition is located closest to The pixel block 114 between the second transfer line 142 and the second boundary 530 of the second boundary 530 and not passed by the dummy transfer line 160 is the second boundary region 532. So configured, the number of pixel blocks 114 in the first boundary region 522 and the second boundary region 532 can be made identical to each other. In this embodiment, the pixel blocks 114 in the first and second boundary regions 522 and 532 are all fifteen. It should be noted that although the number of the pixel blocks 114 of the first and second boundary regions 522, 532 and the central region 510 is different, since the unevenness of the brightness of the boundary regions 522, 532 is not easily perceived by the human eye, it is not easy to cause Obvious influence. Additionally, it is worth noting that in other implementations the number of pixel blocks 114 of the first and second boundary regions 522, 532 and the central region 510 may also be the same.

FIG. 6 is a schematic diagram of the average arrangement of the second transfer line 142 and the dummy transfer line 160 in accordance with an embodiment of the present invention. The embodiment and the previous embodiment are the same as the active area 112 formed by the 12x9 pixel block 114, so the same points are not described herein. Active region 112 has a first boundary 620 and a second boundary 630. In this embodiment, the second transmission line 142 can be disposed on the third, sixth, and ninth rows of the pixel block 114, and the opposite pseudo transmission line 160 can be disposed on the first, second, fourth, and fifth, The 7th and 8th rows are on the pixel block 114.

If the pixel block 114 located between the adjacent two second transfer lines 142 and not passed by the pseudo transfer line 160 is defined as the central region 610, the pixel block 114 in each central region 610 in this embodiment is used. All are twenty-four.

If the pixel block 114 defined between the second transfer line 142 and the first boundary 620 that is closest to the first boundary 620 and is not passed by the second transfer line 142 is defined as the first boundary region 622, and the definition is located closest to The pixel block 114 between the second transfer line 142 and the second boundary 630 of the second boundary 630 and not passed by the second transfer line 142 is the second boundary area 632, and the picture in the first boundary area 622 The prime block 114 is twenty-four, and the second boundary region 632 has zero pixel blocks 114. It should be noted that although the number of the pixel blocks 114 of the first boundary region 622 and each of the central regions 610 is the same in the present embodiment, and the number of the pixel blocks 114 of the second boundary region 632 is different, The unevenness of the brightness and darkness of the boundary area 632 is not easily perceived by the human eye, and is not easily caused to have a significant influence.

It should be understood from the embodiments shown in the above third, fourth, fifth, and sixth figures that the spirit of arranging the pseudo transfer line 160 and the second transfer line 142 on average is to make the pseudo transfer line 160 or the second pass The number of pixel blocks 114 of the central regions 310, 410, 510, 610 defined by the line 142 are all the same, and when the pixel block 114 cannot be uniformly passed by the transfer line 160 and the second transfer line 142, it cannot be The pixel blocks 114 passing through the transfer line 160 and the second transfer line 142 are located in the boundary regions 322, 332, 422, 432, 522, 532, 622, 632 of the active region 112, such that the active region 112 is bright and dark. The phenomenon of unevenness is also not easy to detect by the human eye. It should be noted that the embodiments in the third, fourth, fifth, and sixth figures described above are merely illustrative of the spirit of the average configuration of the pseudo transfer line 160 and the second transfer line 142, rather than Limit the invention. In addition, it is also worth noting that the first boundary 320, 420, 520, 620 and the second boundary 330, 430, 530, 630 are only opposite sides of the active region 112 and the pseudo transmission line 160, and are not limited to the first 3. Drawings in Figures 4, 5, and 6.

In summary, the embodiment of the present invention can transmit the second signal through the first and second transmission lines instead of the traditional surrounding wiring to reduce the frame of the display panel. However, adding a transfer line, on the one hand, causes the lines to overlap, resulting in stray capacitance, and on the other hand, the active area load imbalance. Therefore, the first and second pins of the driving chip are alternately and evenly arranged, the capacitive coupling effect generated by the stray capacitance can be avoided, and the second transfer line can be evenly arranged on the active region. Then, a pseudo transfer line is additionally added, and the pseudo transfer line and the second transfer line are evenly distributed on the active area, which can avoid unevenness of the screen brightness caused by the imbalance of the active area load. Furthermore, by making the orthographic projections of the lines on the substrate not overlap, parasitic capacitance generation can be avoided.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and retouched without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.

100‧‧‧ display panel

110‧‧‧Substrate

112‧‧‧active area

114‧‧‧ pixel block

120‧‧‧First signal line

122‧‧‧Second signal line

130‧‧‧ pixel unit

140‧‧‧First transfer line

142‧‧‧second transfer line

150‧‧‧Drive chip

152‧‧‧First position

154‧‧‧second foot

156‧‧‧ drive circuit

160‧‧‧Pseudo-transmission line

170‧‧‧Common electrode

180‧‧‧Control circuit

310‧‧‧Central area

320‧‧‧ first border

322‧‧‧First border area

330‧‧‧ second border

332‧‧‧Second boundary area

410‧‧‧Central area

420‧‧‧ first border

422‧‧‧First border area

430‧‧‧ second border

432‧‧‧Second boundary area

510‧‧‧Central Area

520‧‧‧ first border

522‧‧‧First border area

530‧‧‧ second border

532‧‧‧Second boundary area

610‧‧‧Central Area

620‧‧‧ first border

622‧‧‧First border area

630‧‧‧ second border

632‧‧‧Second boundary area

P1-P4‧‧‧ orthographic projection

The above and other objects, features, advantages and embodiments of the present invention will become more apparent and understood. 1 is a schematic view of a display panel according to an embodiment of the invention.

2 is a cross-sectional view of the display panel of FIG. 1 along line 2-2 in accordance with an embodiment of the present invention.

FIG. 3 is a schematic diagram of arranging the second transfer line and the pseudo transfer line on average according to an embodiment of the invention.

4 is a schematic diagram of arranging an average of a second transfer line and a pseudo transfer line in accordance with an embodiment of the present invention.

FIG. 5 is a schematic diagram showing an average arrangement of a second transfer line and a pseudo transfer line in accordance with an embodiment of the present invention.

Figure 6 is a schematic diagram showing the arrangement of the second transfer line and the pseudo transfer line on average in accordance with an embodiment of the present invention.

100‧‧‧ display panel

110‧‧‧Substrate

112‧‧‧active area

114‧‧‧ pixel block

120‧‧‧First signal line

122‧‧‧Second signal line

130‧‧‧ pixel unit

140‧‧‧First transfer line

142‧‧‧second transfer line

150‧‧‧Drive chip

152‧‧‧First position

154‧‧‧second foot

156‧‧‧ drive circuit

160‧‧‧Pseudo-transmission line

170‧‧‧Common electrode

180‧‧‧Control circuit

Claims (10)

A display panel includes: a substrate having an active area, the active area including a plurality of pixel blocks; a plurality of first signal lines disposed in parallel on the substrate; and a plurality of second signal lines disposed in parallel On the substrate, the first signal lines are interlaced with each other to define the pixel blocks, and the number of the second signal lines is greater than the number of the first signal lines; the plurality of pixel units are respectively disposed on the The plurality of pixel blocks are respectively connected to the first and second signal lines; and the plurality of transmission lines are arranged in parallel on the substrate, respectively connected to the second signal lines, and traverse the active area Two sides, and parallel to the first signal lines; a driving chip, comprising: a plurality of first pins, connecting the first signal lines; a plurality of second pins connecting the transmission lines; and a driving a circuit for generating a first signal and a second signal for the first pin and the second pin; wherein the first pin interacts with the second pin and is evenly configured The first signal lines connected thereto These transmission lines do not overlap each other, and so that the plurality of transmission lines disposed on the substrate the average. The display panel of claim 1, further comprising: a plurality of pseudo-transmission lines, which are evenly disposed on the substrate, and the plurality of transmissions The transfer lines are parallel and traverse the opposite sides of the active area, wherein the transfer lines are divided into a plurality of first transfer lines and a plurality of second transfer lines, each of the pixel blocks passing therethrough The number of the first transfer lines is the same, and each of the pixel blocks is passed by one of the second transfer lines or passed by one of the pseudo transfer lines. The display panel of claim 2, further comprising: a common electrode disposed on the substrate and located around the active area for connecting the dummy transmission lines; and a control circuit connecting the common electrode and the driving chip And providing a common potential of the common electrode and driving the driving wafer. The display panel of claim 2, wherein the dummy transmission lines, the first transmission lines, the second transmission lines, and the orthographic projections of the first signal lines on the substrate do not overlap. The display panel of claim 2, wherein a pixel block located between adjacent ones of the pseudo transmission lines and not passed by the pseudo transmission lines is defined as a plurality of central areas, wherein the central areas are The number of pixel blocks is the same as each other. The display panel of claim 5, wherein the pixel area located between the pseudo transfer lines closest to a first boundary and the first boundary and not passed by the pseudo transfer lines Block setting Defining a first boundary region, a pixel block located between the pseudo transmission lines closest to a second boundary and the second boundary of the pseudo transmission lines and not passed by the pseudo transmission lines is defined as a a second boundary area, wherein the first and second boundaries are opposite boundaries of the active area, and the number of pixel blocks of the first boundary area and the second boundary area is the same. The display panel of claim 5, wherein the pixel area located between the pseudo transfer lines closest to a first boundary and the first boundary and not passed by the pseudo transfer lines The block is defined as a first boundary area, and a pixel block located between the pseudo transfer line closest to a second boundary and the second boundary among the pseudo transfer lines and not passed by the pseudo transfer lines is defined as a second boundary region, wherein the first and second boundaries are opposite boundaries of the active region, the number of pixel blocks of each of the first boundary region and each of the central regions are the same, and the second The number of pixel blocks in the boundary area is different. The display panel of claim 2, wherein the pixel blocks located between adjacent ones of the second transfer lines and not passed by the second transfer lines are defined as a plurality of central areas, the central areas The number of pixel blocks in the area is the same as each other. The display panel according to claim 8, wherein a pixel block located between the second transfer line closest to a first boundary and the first boundary of the second transfer lines and not passed by the second transfer lines is defined as a first boundary area, A pixel block located between the second transfer line closest to a second boundary and the second boundary of the second transfer lines and not passed by the second transfer lines is defined as a second boundary area. The first and second boundaries are opposite boundaries of the active area, and the number of pixel blocks of the first boundary area and the second boundary area is the same. The display panel of claim 8, wherein between the second transfer lines closest to a first boundary of the second transfer lines and the first boundary and not passed by the second transfer lines The pixel block is defined as a first boundary region located between the second transfer line closest to a second boundary and the second boundary among the second transfer lines and not passed by the second transfer lines The pixel block is defined as a second boundary region, wherein the first and second boundaries are opposite boundaries of the active region, and the number of pixel blocks of each of the first boundary region and each of the central regions is The same, the number of pixel blocks of the second boundary area is different.