TWI469216B - Semiconductor device manufacturing method and substrate processing apparatus - Google Patents

Description

Semiconductor device manufacturing method and substrate processing device

The present invention relates to a method of manufacturing a semiconductor device and a substrate processing apparatus.

For example, in a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), that is, a gold oxide half field effect transistor, an effective technique as a gate insulating film for forming a high dielectric constant is used.

With the high integration and high performance of the MOSFET, the applicability of the high dielectric constant insulating film of the gate insulating film is reviewed. From the viewpoint of mobility or reliability, a junction layer formed of a yttrium oxide (SiO ₂ ) layer is usually used as a junction between a high dielectric constant insulating film and a bismuth (Si) substrate.

However, when a SiO ₂ film is used as the junction layer, EOT (Equivalent Oxide Thickness) of 0.8 nm or less, that is, film thickness equivalent to an equivalent oxide film, becomes difficult due to a low dielectric constant.

Further, when a high dielectric constant insulating film is directly formed on the germanium substrate without using a junction layer, there are many dangling bonds, which may affect electrical characteristics. Further, when the LSI process is formed, an SiO _X layer is formed on the junction between the high dielectric constant insulating film and the germanium substrate. As a result, thin film formation of EOT becomes difficult.

It is an object of the present invention to provide an adverse effect on electrical characteristics Moreover, it is possible to thin the EOT semiconductor device manufacturing method and the substrate processing device.

A method of fabricating a semiconductor device according to an aspect of the present invention includes: forming a metal oxide film on a germanium substrate, and solid-reacting the metal oxide film with the germanium substrate by heat treatment to form a tantalate film; Engineering; and engineering of forming a high dielectric constant insulating film on the tantalate film.

According to another aspect of the present invention, a method for fabricating a semiconductor device includes: forming a high dielectric constant insulating film on a germanium substrate, and solid-reacting the high dielectric constant insulating film with the germanium substrate by heat treatment And repeating the process of forming a niobate film; and forming a high dielectric constant insulating film on the niobate film.

According to another aspect of the present invention, in a method of fabricating a semiconductor device, a ruthenium oxide film is formed on a ruthenium substrate, and the ruthenium oxide film is subjected to a solid phase reaction with the ruthenium substrate by heat treatment, and is formed by repeating the ruthenium oxide film. Engineering of a bismuth film; and engineering of forming a yttrium oxide film on the bismuth film.

A substrate processing apparatus according to another aspect of the present invention includes: a first processing chamber for forming a high dielectric constant insulating film on a germanium substrate; and a second processing chamber for performing heat treatment of the germanium substrate; The transfer chamber is disposed between the first processing chamber and the second processing chamber, and transports the crucible substrate between the first processing chamber and the second processing chamber; and the transfer robot is disposed in the transfer chamber and is used for Carrying the above-mentioned ruthenium substrate; and the controller performs the following control: moving the ruthenium substrate by the transfer robot arm Sending to the first processing chamber, forming the high dielectric constant insulating film on the germanium substrate in the first processing chamber, and forming the germanium substrate on which the high dielectric constant insulating film is formed by the transfer robot The first processing chamber is transported to the second processing chamber, and the tantalum substrate on which the high dielectric constant insulating film is formed is heat-treated in the second processing chamber to form the high dielectric constant insulating film and the tantalum substrate. Forming a niobate film by a reaction, repeating this operation to form a niobate film having a specific thickness on the surface of the tantalum substrate, and then forming the tantalum substrate after forming the niobate film having the specific thickness The second processing chamber is transported into the first processing chamber, and a high dielectric constant insulating film is formed on the niobate film having the specific film thickness in the first processing chamber.

Hereinafter, an embodiment of the present invention will be described based on the drawings.

1 is a flow chart showing a method of forming a high dielectric constant gate insulating film in a MOSFET according to an embodiment of the present invention.

2 to 4 show a substrate processing apparatus according to an embodiment of the present invention.

First, a substrate processing apparatus according to an embodiment of the present invention will be described.

In the present embodiment, the substrate processing apparatus of the present invention is configured as a group device as shown in FIG. 2, and is functionally configured by a method of forming a high-k gate insulating film for a MOSFET.

Further, in the group device of the present embodiment, the wafer transfer carrier (substrate storage container) for transporting the germanium substrate, that is, the germanium wafer 2 (hereinafter simply referred to as the wafer 2), is FOUP (front). Opening unified Pod, hereinafter referred to as wafer carrier)1.

As shown in FIG. 2, the group device 10 includes a housing 12 in which a first wafer transfer chamber (hereinafter referred to as a negative pressure transfer chamber) 11 is formed. The negative pressure transfer chamber 11 is configured as a transfer chamber configured to withstand a pressure less than atmospheric pressure (negative pressure). A frame body (hereinafter referred to as a negative pressure transfer chamber frame body) 12 in which the negative pressure transfer chamber 11 is formed has a rectangular parallelepiped shape and is formed in a box shape in which both upper and lower ends are closed.

A wafer transfer device (hereinafter referred to as a negative pressure transfer device) 13 as a transfer robot is provided in a central portion of the negative pressure transfer chamber 11, and the wafer 2 can be transferred under a negative pressure. The negative pressure transfer device 13 is composed of a selective compliance assembly robot arm (SCARA).

A long side wall among the seven side walls of the negative pressure transfer chamber frame 12 is adjacently connected to a carry-in preparation room (hereinafter referred to as a carry-in chamber) 14 and a carry-out preparation room (hereinafter referred to as a carry-out room) 15.

The frame that is moved into the chamber 14 and the frame of the unloading chamber 15 have a substantially circular shape, and are formed into a box shape in which the upper and lower ends are closed, and are configured as a vacuum lock chamber that can resist negative pressure. structure.

On the side opposite to the first wafer transfer chamber 11 of the carry-in chamber 14 and the carry-out chamber 15, the frame body 16A is connected adjacent to each other. The casing 16A constitutes a second wafer transfer chamber (hereinafter referred to as a positive pressure transfer chamber) 16. The positive pressure transfer chamber 16 is configured to maintain a pressure equal to or higher than atmospheric pressure (hereinafter referred to as positive pressure). The frame of the positive pressure transfer chamber 16 has a horizontally long rectangular shape and is formed into a box shape in which the upper and lower ends are closed.

A gate valve 17A is provided at the boundary between the positive pressure transfer chamber 16 and the carry-in chamber 14, and a gate valve 17B is provided at the boundary between the negative pressure transfer chamber 11 and the carry-in chamber 14.

A gate valve 18A is provided at the boundary between the positive pressure transfer chamber 16 and the carry-out chamber 15, and a gate valve 18B is provided at the boundary between the negative pressure transfer chamber 11 and the carry-out chamber 15.

A second wafer transfer device (hereinafter referred to as a positive pressure transfer device) 19 is provided in the positive pressure transfer chamber 16, and the wafer 2 can be transferred under a positive pressure. The positive pressure transfer device 19 is composed of a planar articulated robot arm.

The positive pressure transfer device 19 is reciprocated in the left-right direction by a linear brake while being lifted and lowered by the lifter provided in the positive pressure transfer chamber 16.

A groove alignment device 20 is provided at the left end of the positive pressure transfer chamber 16.

In the front wall of the positive pressure transfer chamber 16, three wafer carry-out ports 21 to 23 are arranged adjacent to each other, and the wafer carry-out ports 21 to 23 are used to carry the wafer 2 into the positive pressure transfer chamber 16, or The positive pressure transfer chamber 16 carries out the wafer 2.

The FOUP opener 24 is provided at each of the wafer carry-out ports 21 to 23, respectively.

The FOUP opener 24 includes a mounting table 25 for mounting the FOUP 1 and a cap attaching and detaching mechanism 26 for attaching and detaching the cap of the FOUP 1 placed on the mounting table 25. The cap attachment/detachment mechanism 26 opens/closes the wafer inlet and outlet of the FOUP 1 by attaching and detaching the cap of the FOUP 1 placed on the mounting table 25.

In the in-project conveyance device (RGV) (not shown), the FOUP 1 is supplied to the mounting table 25 of the FOUP opener 24, or the FOUP 1 is discharged from the mounting table 25 of the FOUP opener 24.

As shown in FIG. 2, among the seven side walls of the negative pressure transfer chamber frame 12, the first processing unit 31 and the second side are adjacently connected to the two side walls on the opposite side of the positive pressure transfer chamber 16 Processing unit 32.

A gate valve 44 (see FIG. 3) is provided between the first processing unit 31 and the negative pressure transfer chamber 11.

A gate valve 118 (see FIG. 4) is provided between the second processing unit 32 and the negative pressure transfer chamber 11.

The first clean unit 35 and the second clean unit 36 are connected to the other two of the seven side walls of the negative pressure transfer chamber frame 12. Both the first cleaning unit 35 and the second cleaning unit 36 are used to cool the processed wafer 2.

The group device 10 is provided with a controller 37. The controller 37 integrates and controls the sequence flow described later.

In the present embodiment, as shown in the structure of FIG. 3, the first processing unit 31 is configured as a blade type worm wall type substrate processing apparatus, and is functionally configured as an ALD (Atomic Layer Deposition) device (hereinafter referred to as an ALD device). ) 40.

As shown in FIG. 3, the ALD apparatus 40 is provided with the housing 42 which forms the process chamber 41. A heater (not shown) is housed in the casing 42 for heating the wall surface of the processing chamber 41.

In the casing 42, a wafer loading/unloading port (hereinafter referred to as a wafer loading port) 43 is provided at the boundary between the wafer loading and unloading port 11 and the negative pressure transfer chamber 11. The gate valve 44 is used to open/close the wafer transfer inlet 43.

An elevation driving device 45 is disposed on the bottom surface of the processing chamber 41, and the lifting drive is provided The moving device 45 raises and lowers the lifting shaft 46. At the upper end of the lifting shaft 46, the holder 47 holding the wafer 2 is horizontally supported.

The heater 47a is provided in the holder 47 for heating the wafer 2.

A purge gas supply port 48A and a purge gas supply port 48B are provided in the bottom wall of the wafer transfer inlet 43 and the processing chamber 41, respectively, through the purge gas supply port 48A and the purge gas supply port 48B, via the stop valve 64A and The stop valve 64B is connected to the purge gas supply pipe, that is, the Ar gas supply pipe 58, respectively. An Ar gas supply source 59 is connected to the Ar gas supply pipe 58.

In the casing 42, the exhaust port 49 is provided on the opposite side of the wafer loading port 43, and is connected to the exhaust port 49, and is connected to the exhaust pipe 51 of the exhaust device 50 such as a vacuum pump.

The processing gas supply port 52 is opened in the chamber wall of the casing 42 so as to communicate with the processing chamber 41, and the processing gas supply port 52 is connected to the first processing gas supply pipe 53A and the second processing gas supply pipe 53B.

The first diffuser 56A is connected to the first process gas supply pipe 53A via the upstream side stop valve 54A and the downstream side stop valve 55A. The diffusion pipe 57A of the first diffuser 56A is connected to the Ar gas supply pipe 58 of the Ar gas supply source 59.

The Ar gas supply pipe 58 is connected between the flow side stop valve 54A and the downstream side stop valve 55A in the first process gas supply pipe 53A via the stop valve 60A. The upper end of the vent pipe 61A is connected between the connection point of the Ar gas supply pipe 58 of the first process gas supply pipe 53A and the downstream side stop valve 55A. The flow side end of the vent pipe 61A is connected to the stop valve 62A is connected to the exhaust pipe 51 of the exhaust device 50.

Further, in the first process gas supply pipe 53A, the Ar gas supply pipe 58 is connected to the downstream side of the downstream side stop valve 55A via the stop valve 63.

In the second processing gas supply pipe 53B, the second diffuser 56B is connected via the upstream side stop valve 54B and the downstream side stop valve 55B. The diffusion pipe 57B of the second diffuser 56B is connected to the Ar gas supply pipe 58 of the Ar gas supply source 59.

The Ar gas supply pipe 58 is connected to the Ar gas supply pipe 58 via the stop valve 60A between the upstream side stop valve 54B and the downstream stop valve 55B. Between the connection point of the Ar gas supply pipe 58 of the second processing gas supply pipe 53B and the downstream side stop valve 55B, the upstream end of the vent pipe 61B is connected. The flow side end of the vent pipe 61B is connected to the exhaust pipe 51 of the exhaust device 50 via a stop valve 62B.

Further, the downstream side of the downstream side stop valve 55B of the second process gas supply pipe 53B is connected to the downstream side of the downstream flow stop valve 55A of the first process gas supply pipe 53A, and the first process gas supply pipe The 53A and the second process gas supply pipe 53B are integrally connected to the downstream side of the connection point, and are connected to the process gas supply port 52.

In the present embodiment, the second processing unit 32 uses an RTP (Rapid Thermal Processing) device 110 as shown in FIG.

The RTP (Rapid Thermal Processing) device 110 shown in FIG. 4 includes a housing 112 that constitutes a processing chamber 111 for processing the wafer 2. The frame 112 is formed by a cylindrical shape having an opening on the upper and lower surfaces. The side wall portion 113 and the disk-shaped top plate 114 that closes the upper opening portion of the side wall portion 113 and the disk-shaped bottom plate 115 that closes the lower opening portion of the side wall portion 113 are combined to form a cylindrical hollow body shape.

An exhaust port 116 is opened in one of the upper side walls of the side wall portion 113 to communicate the inside and outside of the processing chamber 111, and an exhaust device (not shown) is connected to the exhaust port 116 to exhaust the processing chamber 111 to be less than atmospheric pressure. (hereinafter referred to as negative pressure).

In the side wall portion 113, a wafer loading/unloading port (hereinafter referred to as a wafer loading port) 117 is provided at a position opposite to the exhaust port 116 of the upper side wall, and the wafer 2 can be carried out into the processing chamber 111. The gate valve 118 is used to open/close the wafer transfer inlet 117.

A lifting drive unit 119 is disposed on a lower center line of the bottom plate 115, and the elevation driving unit 119 raises and lowers the lifting shaft 120. The lifting shaft 120 is inserted into the bottom plate 115, and the bottom plate 115 is slidably supported in the vertical direction.

The lifting plate 121 is horizontally fixed to the upper end of the lifting shaft 120. A plurality of (usually 3 or 4) lifting pins 122 are vertically erected and fixed on the lifting plate 121, and the lifting pins 122 are lifted and lowered with the lifting of the lifting plate 121. The wafer 2 can be lifted and lowered in the horizontal direction by the lower support. The cooling plate 124 is horizontally mounted on the bottom plate 115. The support tube 123 is protruded from the outer side of the lifting shaft 120. On the upper end surface of the supporting cylinder 123, the cooling plate 124 is horizontally erected.

Above the cooling plate 124, the first heating lamp group 125 and the second heating lamp group 126, which are composed of a plurality of heating lamps, are arranged in order from the bottom, and are horizontally erected. The first heating lamp group 125 and the second heating lamp group 126 The first pillar 127 and the second pillar 128 are horizontally supported.

The electric power supply wires 129 of the first heating lamp group 125 and the second heating lamp group 126 are inserted through the bottom plate 115 and taken out.

In the processing chamber 111, the rotating table 131 and the processing chamber 111 are arranged concentrically. The rotary table 131 is attached to the upper spur gear 133 and the internal spur gear 133 is fixed in a concentric shape, and the internal spur gear 133 is horizontally supported by a bearing 132 provided on the bottom plate 115.

The inner spur gear 133 is meshed with the primary side spur gear 134, and the primary side spur gear 134 is horizontally supported by a bearing 135 provided on the bottom plate 115. The primary side spur gear 134 is rotationally driven by a susceptor rotation device 136 disposed under the bottom plate 115.

On the upper end surface of the rotary table 131, the outer platform 137 formed in the shape of a circular ring of a flat plate is horizontally erected. The inner platform 138 is horizontally spanned inside the outer platform 137.

At the inner lower end portion of the inner platform 138, the susceptor 140 is engaged with and held in the radial direction inwardly at the engaging portion 139 of the lower end portion of the inner peripheral surface of the inner platform 138.

The insertion holes 141 are respectively formed at positions facing the lift pins 122 of the susceptor 140.

In the top plate 114, the annealing gas supply pipe 142 and the inert gas supply pipe 143 are connected to each other so as to communicate with the processing chamber 111.

On the top plate 114, a plurality of radiation thermometer probes 144 are arranged to be offset from the center to the periphery of the wafer 2 in the radial direction, and are inserted in such a manner as to face the upper surface of the wafer 2. Radiation thermometers are based on a majority The emitted light detected by the probe 144 respectively transmits the measured temperature to the controller.

The emissivity measuring device 145 is provided in another place of the top plate 114, and the emissivity measuring device 145 can measure the emissivity of the wafer 2 in a non-contact manner. The emissivity measuring device 145 includes a reference probe 146, and the reference probe 146 is rotatable in the vertical plane by the reference probe motor 147.

On the upper side of the reference probe 146, the reference lamp 148 is disposed to face the front end of the reference probe 146, and the reference lamp 148 illuminates the reference light. The reference probe 146 is optically coupled to the radiation thermometer. The radiation thermometer corrects the measured temperature by comparing the photon density of the wafer 2 with the photon density of the reference light of the reference lamp 148.

Hereinafter, according to FIG. 1, a group device 10 which is a process of a semiconductor device, that is, a group device 10 having the above-described structure, is formed, and a tantalate film is formed on the surface of the germanium substrate as a junction layer, and a high dielectric is formed on the tantalate film. The method of coefficient insulation film.

In the present embodiment, as the tantalum film of the junction layer, a metal oxide film is formed on the tantalum substrate, and the metal oxide film is solid-phase reacted with the tantalum substrate by heat treatment to form a surface of the tantalum substrate. .

In the embodiment described in the present embodiment, a metal oxide film of a hafnium oxide film (HfO ₂ film) is formed on a tantalum substrate, and the tantalum oxide film is solid-phase reacted with the tantalum substrate by heat treatment to form a tantalum on the surface of the tantalum substrate. A ruthenium salt film (HfSiO _x film) is used as a ruthenium salt film, and a ruthenium oxide film (HfO ₂ film) as a high dielectric constant insulating film is formed on the ruthenium salt film. More specifically explained below.

In the following description, the actions of the various components constituting the group device 10 are The controller 37 controls.

The substrate 2, that is, the wafer 2, which is placed in the group device 10, is previously cleaned in a hydrogen fluoride (HF) cleaning process (see FIG. 1).

In the wafer loading step shown in FIG. 1, the lid portion of the FOUP 1 supplied to the mounting table 25 of the group device 10 is removed by the cap attaching and detaching mechanism 26, and the wafer inlet and outlet of the FOUP 1 is opened.

After the FOUP 1 is opened, the positive pressure transfer device 19 provided in the positive pressure transfer chamber 16 takes out one wafer 2 from the FOUP 1 via the wafer transfer inlet 21 or 22 or 23, and puts it into the transfer chamber 14 to transfer the wafer 2 Move to the temporary table for moving into the room.

In the displacing operation, the positive pressure transfer chamber 16 side of the carry-in chamber 14 is opened by the gate valve 17A, and the negative pressure transfer chamber 11 side of the carry-in chamber 14 is closed by the gate valve 17B, and the negative pressure transfer chamber 11 side The pressure is maintained at a pressure less than atmospheric pressure, such as 100 Pa.

In the wafer loading step shown in FIG. 1, the positive pressure transfer chamber 16 side of the carry-in chamber 14 is closed by the gate valve 17A, and the carry-in chamber 14 is exhausted by the exhaust device (not shown) to become a negative pressure. .

After the carry-in chamber 14 is depressurized to a pressure value set in advance, the negative pressure transfer chamber 11 of the carry-in chamber 14 is opened by the gate valve 17B.

Thereafter, the negative pressure transfer device 13 of the negative pressure transfer chamber 11 takes out the one wafer 2 from the loading chamber temporary stage and carries it into the vacuum transfer chamber 11 under vacuum.

Thereafter, the side of the negative pressure transfer chamber 11 of the carry-in chamber 14 is closed by the gate valve 17B.

Thereafter, the gate valve 44 of the first processing unit 31 is opened, and the negative pressure is transferred. The apparatus 13 transports the wafer 2 to the first processing unit 31 under vacuum, and carries it into the processing chamber of the first processing unit 31 (wafer loading).

Further, the processing chamber loaded into the first processing unit 31 is evacuated to a pressure value set in advance.

Further, when the wafer 2 is carried into the first processing unit 31, the loading chamber 14 and the negative pressure transfer chamber 11 are evacuated to a negative pressure, and the internal oxygen or moisture is removed first, so that external oxygen or moisture can be surely prevented. The wafer 2 is carried into the processing chamber of the first processing unit 31 as it is carried into the first processing unit 31.

Next, a process of forming a metal oxide film of a hafnium oxide film (HfO ₂ film) on the wafer 2 of the tantalum substrate by the ALD method using the ALD apparatus 40 of the first processing unit 31 will be described with reference to FIG.

In the present embodiment, TDMAH (Tetrakis-Dimethyl-Amino-Hafnium: Hf[N(CH ₃ ) ₂ ] ₄ ) is used as a ruthenium (Hf)-based precursor, and water vapor (H ₂ O) is used as an oxidant.

In the ALD apparatus 40 of the present embodiment, the TDMAH of the liquid material is accommodated in the first diffuser 56A, and the first diffuser 56A is used to vaporize the TDMAH. The flow rate of the Ar gas used for the diffusion of the first diffuser 56A is, for example, 0.5 to 1 SLM (standard. liter per minute).

In the ALD apparatus 40 of the present embodiment, the second diffuser 56B is used to generate water vapor of the oxidizing agent. The flow rate of the Ar gas used for the diffusion of the second diffuser 56B is, for example, 0.5 to 1 SLM.

In FIG. 3, the wafer transfer port 43 of the ALD device 40 of the first processing unit 31 is opened by the gate valve 44. At this time, the holder 47 is lowered to the crystal Round transport location. When the wafer loading port 43 is opened, the negative pressure transfer device 13 carries the wafer 2 into the processing chamber 41.

After the wafer 2 is carried into the processing chamber 41 and placed on the upper protruding pin, the negative pressure transfer device 13 is retracted to the outside of the processing chamber 41. Thereafter, the gate valve 44 closes the carry-in port 43.

The lift drive unit 45 raises the holder 47 from the wafer transfer position to the wafer processing position shown in FIG. 3 via the lift shaft 46. In the meantime, the holder 47 pushes up the wafer 2 on the upper protruding pin and places it on the holder 47.

After the gate valve 44 is closed, the exhaust device 50 performs the exhaust in the processing chamber 41. The inside of the processing chamber 41 is adjusted to, for example, a specific pressure in the range of 10 to 100 Pa, for example, 30 Pa.

The heater 47a built in the holder 47 is heated to uniformly heat the wafer 2 to a specific temperature in the range of, for example, 150 ° C to 350 ° C. In the meantime, that is, when the temperature and the pressure are adjusted, the stop valves 63, 64A, and 64B are in an open state, and the space in the processing chamber 41 and the processing chamber 41 is lower than the holder 47 to make the Ar gas as the purge gas. It is supplied through the processing gas supply port 52 and the purge gas supply ports 48A and 48B, and is exhausted via the exhaust port 49 and the exhaust pipe 51. In this case, the inside of the processing chamber 41 is set to an inert gas atmosphere.

When the wafer 2 is carried in, the stop valves 54A, 55A, 54B, and 55B are respectively in a closed state, and the stop valves 60A, 62A, 60B, 62B, 63, 64A, and 64B are in an open state.

For the preparation of the raw material supply, the stop valves 60A, 55A, 60B, 55B are set to the closed state, and the stop valves 54A, 62A, 54B, 62B are set. In the open state, the vaporized raw material and the steam are respectively inserted into the first process gas supply pipe 53A and the second process gas supply pipe 53B.

Further, Ar gas as a purge gas is supplied into the processing chamber 41 by the opening of the stop valve 63. Further, by the opening of the stop valves 64A and 64B, the space in the processing chamber 41 is lower than the holder 47, and the Ar gas as the purge gas flows in through the purge gas supply ports 48A and 48B. The flow rate of the Ar gas is set to, for example, 0.1 to 1.5 SLM.

After the temperature of the wafer 2 is stabilized and the pressure in the processing chamber 41 is stabilized, the following steps (1) to (4) are cycled, and the cycle is repeated until the yttrium oxide film becomes the target film thickness.

(1) Raw material supply step

While the stop valve 62A is closed, the stop valve 55A is opened, and the state is maintained, for example, for 0.5 to 5 seconds. In this manner, the vaporized raw material is supplied to the processing chamber 41 while being exhausted through the exhaust port 49.

The tantalum raw material supplied into the processing chamber 41 is adsorbed to the wafer 2.

(2) Raw material exhausting step

Thereafter, while the stop valve 54A is closed, the stop valve 60A is opened, and the state is maintained for, for example, 0.5 to 10 seconds. In this manner, the Ar gas is supplied into the inside of the first processing gas supply pipe 53A and the processing chamber 41, and is exhausted through the exhaust port 49. In other words, the inside of the first processing gas supply pipe 53A and the processing chamber 41 are cleaned by the Ar gas, and the raw materials supplied into the first processing gas supply pipe 53A and the processing chamber 41 are exhausted.

Thereafter, the stop valves 60A and 55A are closed, the stop valves 54A and 62A are opened, and the vaporized raw material is filled in the first process gas supply pipe 53A.

(3) oxidant supply step

While the vaporized raw material is filled in the first processing gas supply pipe 53A, the stop valve 62B is closed, and the stop valve 55B is opened, and the state is maintained for, for example, 0.5 to 15 seconds. In this manner, the water vapor as the oxidant is supplied into the processing chamber 41, and is exhausted through the exhaust port 49.

In this way, in step (1), the germanium raw material on the surface of the wafer 2 is reacted with water vapor to form about 1 on the wafer 2. Membrane thick yttrium oxide film.

(4) Exhaust step of oxidant

While the stop valve 54B is closed, the stop valve 60B is opened, and the state is maintained for, for example, 0.5 to 15 seconds. In this manner, the Ar gas is supplied to the inside of the second processing gas supply pipe 53B and the processing chamber 41, and is exhausted through the exhaust port 49. In other words, the inside of the second processing gas supply pipe 53B and the processing chamber 41 are cleaned by the Ar gas, and the oxidizing agent supplied into the second processing gas supply pipe 53B and the processing chamber 41 is exhausted.

Thereafter, the stop valves 60B and 55B are closed, the stop valves 54B and 62B are opened, and the water vapor is filled into the second process gas supply pipe 53B.

Usually, when the film is formed by the ALD method, about 1 film is formed in one cycle. , about 1 atomic layer is formed in the 2~3 cycle.

That is, as shown in FIG. 13, an island-shaped film is formed in the first cycle, and The second to third cycles form a continuous film of one atomic layer.

The above steps (1) to (4) are used for one cycle, and one to three such one cycles are carried out to form a cerium oxide film having a specific film thickness, that is, a level of one atomic layer or less.

After the formation of the ruthenium oxide film is completed, the inside of the processing chamber 41 is evacuated, and the residual gas in the processing chamber 41 is discharged. Thereafter, an inert gas is introduced into the processing chamber 41, and the inside of the processing chamber 41 is set to an inert gas atmosphere.

Further, the holder 47 is lowered from the wafer processing position to the wafer transfer position, and the formed wafer 2 is placed on the upper protruding pin.

Thereafter, the gate valve 44 of the ALD device 40 is opened, the wafer transfer port 43 is opened, and the wafer 2 after the film formation is carried out from the first processing unit 31 by the negative pressure transfer device 13 to a negative pressure maintained at a negative pressure. Transfer chamber 11 (wafer unloading).

The negative pressure transfer device 13 transports the wafer 2 to the second processing unit 32 under vacuum, and carries it into the processing chamber of the second processing unit 32 (wafer loading).

Next, a process of heat-treating the wafer 2 on which the hafnium oxide film is formed using the RTP apparatus 110 of the second processing unit 32 will be described with reference to FIG.

4, the gate valve 118 of the RTP device 110 of the second processing unit 32 is opened, and the wafer 2 is carried into the processing chamber 111 from the wafer loading port 117 by the negative pressure transfer device 13, and is transferred to most of the lift pins. At the top of 122.

When the negative pressure transfer device 13 that transfers the wafer 2 to the lift pin 122 is retracted outside the processing chamber 111, the wafer carry-in 117 is closed by the gate valve 118. shut down.

The lifting shaft 120 is lowered by the elevation driving device 119, and the wafer 2 above the lifting pin 122 is transferred onto the susceptor 140 to be in the state shown in FIG.

When the processing chamber 111 is closed in a sealed state, the inside of the processing chamber 111 is exhausted through the exhaust port 116 to a specific pressure in the range of 1 to 4000 Pa, for example, 1 to 1000 Pa.

After the wafer 2 is transferred to the susceptor 140, the wafer 2 is rotated by the susceptor rotation device 136 by the rotator 133 and the motive spur gear 134 held by the susceptor 140.

The wafer 2 held by the susceptor 140 is rotated by the susceptor rotation device 136, and the first heating luminaire group 125 and the second heating luminaire group 126 are rapidly heated to a specific temperature in the range of, for example, 650 to 850 ° C. . The temperature of the wafer 2 held by the susceptor 140 is maintained at this temperature after reaching a certain heat treatment temperature.

In the rotation and heating, an inert gas such as a nitrogen gas is supplied into the processing chamber 111 by the annealing gas supply pipe 142.

The susceptor 140 is rotated by the susceptor rotation device 136, and the wafer 2 held by the susceptor 140 is uniformly heated by the first heating luminaire group 125 and the second heating luminaire group 126, so that the wafer 2 can be fully integrated. It is uniformly applied to the heat treatment.

By this heat treatment, a solid phase reaction occurs between the tantalum oxide film formed on the wafer 2 and the tantalum wafer 2 of the tantalum substrate, and a niobate film (HfSiO _x film) is formed on the surface of the wafer 2.

After the predetermined processing time of the RTP device 110 is set in advance, the controller 37 ends the heating of the first heating lamp group 125 and the second heating lamp group 126, and starts the rapid cooling of the wafer 2.

After the processing chamber 111 is exhausted to a specific negative pressure by the exhaust port 116, the gate valve 118 is opened. Thereafter, the wafer 2 after the heat treatment is carried out by the negative pressure transfer device 13 from the processing chamber 111 to the negative pressure transfer chamber 11 (the wafer is carried out) in the reverse order of the loading.

The negative pressure transfer device 13 re-transfers the heat-treated wafer 2 to the first processing unit 31 under vacuum, and again carries it into the processing chamber 41 (wafer loading) of the ALD device 40 of the first processing unit 31.

Hereinafter, the yttrium oxide film forming process of the ALD device 40 and the heat treatment process of the RTP device 110 are repeated as shown in FIG. 2 a certain number of times.

By repeating the ruthenium oxide film formation process and the heat treatment process, a very thin tantalum film (hereinafter referred to as an extremely thin tantalate film) having a good contact layer can be formed on the surface of the wafer 2.

Further, the number of repetitions of the ruthenium oxide film forming process and the heat treatment process is preferably five times as described later.

After the repetition of the preset number of times, the wafer 2 on which the extremely thin tantalate film is formed is carried out from the processing chamber 111 of the RTP device 110 of the second processing unit 32 to the negative by the negative pressure transfer device 13. The pressure transfer chamber 11 (loaded on the wafer) is transferred to the first processing unit 31 under vacuum, and is carried into the processing chamber 41 (wafer loading) of the ALD device 40 of the first processing unit 31.

Oxidation as a high dielectric constant insulating film forming process as shown in FIG. In the ruthenium film formation process, a ruthenium oxide film which is a high dielectric constant insulating film is formed on the extremely thin tantalate film as a junction layer by the ALD device 40.

The formation sequence of the ALD device 40 for forming a hafnium oxide film as a high dielectric constant insulating film on the extremely thin tantalate film, and the ALD sequence of the formation of the hafnium oxide film as the metal oxide film by the above ALD device 40 the same.

That is, before the formation of the yttrium oxide film having the necessary film thickness of the high dielectric constant insulating film, the steps (1) to (4) of the above-described one cycle are repeated as the ALD cycle.

The high dielectric constant insulating film forming process is repeated for a specific number of ALD cycles to form a cerium oxide film having a specific film thickness. Thereafter, when the residual gas in the processing chamber 41 is removed, the gate valve 44 of the ALD device 40 is opened, and the wafer 2 after the film formation is carried out from the first processing unit 31 to the negative by the negative pressure transfer device 13. The negative pressure transfer chamber 11 (wafer carrying).

In the wafer loading step shown in FIG. 1 after the high dielectric constant insulating film forming process of the group device 10, that is, the yttrium oxide film forming process, the negative pressure transfer chamber 11 side of the carry-out chamber 15 is set by the gate valve 18B. Open state. The negative pressure transfer device 13 transports the wafer 2 from the negative pressure transfer chamber 11 to the carry-out chamber 15 under vacuum, and moves to the carry-out stage for the carry-out chamber of the carry-out chamber 15.

At this time, the positive pressure transfer chamber 16 side of the carry-out chamber 15 is previously closed by the gate valve 18A, and the unloading chamber 15 is evacuated by the exhaust device (not shown) to become a negative pressure. When the carry-out chamber 15 is decompressed to a previously set pressure value, the negative pressure transfer chamber 11 side of the carry-out chamber 15 is opened by the gate valve 18B. The wafer is loaded and executed.

After the wafer loading step, the gate valve 18B is set to the off state.

The first processing unit 31 to the second processing unit 32 are transported from the first processing unit 32 to the first processing unit 31 from the first processing unit 31 to the unloading chamber 15 from the first processing unit 31 to the second processing unit 31. In the case of the wafer 2, any of the transport paths of the transport operation is carried out while maintaining the vacuum state. Therefore, during the process, the wafer 2 is not exposed to the atmosphere, and the surface of the film formed on the wafer 2 does not have a natural oxide film, and impurities such as organic substances or foreign matter can be prevented from adhering.

By repeating the above operation, the 25 wafers 2 that are once loaded into the loading chamber 14 are sequentially executed, and the ruthenium oxide film forming process of the first processing unit 31 and the heat treatment process of the second processing unit 32, that is, the heat treatment, are repeated. The tantalum film formation process of the surface layer, and the yttrium oxide film formation process of the first processing unit 31 as a high dielectric constant insulating film.

In the wafer discharge step shown in FIG. 1, the nitrogen gas is supplied to the carry-out chamber 15 for maintaining the negative pressure, and after the inside of the carry-out chamber 15 is at atmospheric pressure, the positive pressure transfer chamber 16 side of the carry-out chamber 15 is opened by the gate valve 18A.

Thereafter, the lid portion of the empty FOUP 1 placed on the mounting table 25 is opened by the cap attaching and detaching mechanism 26 of the FOUP opener 24.

Thereafter, the positive pressure transfer device 19 of the positive pressure transfer chamber 16 takes out the wafer 2 from the carry-out chamber 15 and carries it out to the positive pressure transfer chamber 16, and is charged by the wafer transfer inlet 23 of the positive pressure transfer chamber 16 FOUP1.

After the processed 25 wafers 2 are stored in the FOUP 1, the cover of the FOUP 1 is replaced by the cap attachment and detachment mechanism 26 of the FOUP opener 24. Installed at the wafer entrance and exit, FOUP1 is turned off.

In the present embodiment, the wafer 2 after the completion of one of the group devices 10 is placed in the state of the FOUP 1 in a gas-tight manner, and the film forming apparatus in which the gate film formation step is performed is shown in FIG. The transfer process in the project of FOUP is carried.

The film forming apparatus that performs the gate film forming step may be, for example, a batch type vertical hot wall type CVD apparatus, a vane type ALD apparatus, a vane type CVD apparatus, or the like.

An electrode of a gate structure is formed on the wafer 2 via a patterning step as shown in FIG.

According to the present embodiment, the metal oxide film formed on the substrate of the tantalum is thermally treated to form a solid phase reaction with the tantalum substrate to form a tantalate film. Thus, a good tantalate film as a junction layer can be formed. A very thin, flat film can be formed.

In addition, the solid oxide reaction between the metal oxide film and the tantalum substrate can reduce the dangling bonds, and compared with the SiO ₂ film, the dielectric constant can be improved by the niobate film, and the EOT scaling and good can be achieved. Junction characteristics.

In particular, when a metal oxide film is formed by the ALD method, a heat treatment is performed for each of the film formations within 1 to 3 cycles, whereby a good tantalate film can be formed. That is, each of the film formation layers below the atomic layer level is heat-treated to form a good tantalate film.

The following describes the advantages of producing a solid phase reaction by heat treatment for each film formation of 1 atomic layer or less (1 to 3 cycles of ALD).

The property of the HfO ₂ film of the metal oxide film is such that O (oxygen atom) in the film is easily detached. The thicker the film thickness, the more O is detached from the film, and the thinner the film thickness, the smaller the amount of O that is detached from the film.

Therefore, it is set as a solid phase reaction in which a heat treatment is performed every time a thick film thickness, for example, a film of several tens of atomic layers is formed, and thus, the O which is detached from the HfO ₂ film before the bismuth hydride reaction occurs The tantalum substrate, that is, the tantalum wafer, is oxidized, resulting in a low dielectric constant film (SiO _x film and/or Si-rich HfSiO _x film) being formed.

On the other hand, in the case of a solid phase reaction in which heat treatment is performed for each of the film formation of about 1 atomic layer or less (1 to 3 cycles of ALD), the amount of O which is desorbed from the HfO ₂ film is small, and the low dielectric constant film is formed. It does not form, but produces a oximation reaction, so that a suitable HfO ₂ film can be formed.

Further, the thicker the film thickness of the metal oxide film, the more difficult it is to cause bismuthation even when the metal oxide film and the ruthenium substrate are subjected to heat treatment. Therefore, in order to sufficiently achieve the bismuthation, the metal oxide film must be formed to be thin to some extent, preferably at least 1 atomic layer or less, more preferably less than 1 atomic layer.

According to the ALD method, an atomic layer can be formed by 2 to 3 cycles.

Therefore, when the film is formed by the ALD method, heat treatment is performed every time the film formation is performed within 1 to 3 cycles, and thus, a good tantalate film having an atomic layer of 1 atomic layer can be formed. In particular, by performing heat treatment for each of the film formation of one cycle, the wafer transfer position can be more efficiently reacted with the germanium substrate, and a good tantalate film can be formed. Therefore, when forming a film by the ALD method, it is preferred to carry out heat treatment for each of the film formation of one cycle.

(Example)

Referring to Figs. 11 and 12, a method of the above embodiment is used to form a junction layer of a very thin tantalate film on the surface of a germanium substrate, i.e., a germanium wafer, on which a high dielectric gate insulating film is formed. The ruthenium oxide film forms an embodiment of a MOSFET.

First, HF-cleaning is cleaned by HF.

After the HF is cleaned, a very thin tantalate film is formed on the surface of the wafer as a junction layer (HfSiO _x -IL formation).

That is, only a metal oxide film of one cycle, that is, a film of ruthenium oxide film (ALD-HfO ₂ ) was formed on the wafer after the cleaning by the ALD apparatus.

The treatment conditions are: film formation temperature: 150~350 ° C, film formation pressure: 30 Pa, film thickness of 1 cycle unit: 1 .

Thereafter, an RTA (Rapid Thermal Anneal) heat treatment was performed in a nitrogen gas atmosphere by an RTP apparatus to cause a solid phase reaction between the ruthenium oxide film and the ruthenium wafer to form a ruthenium hydride film (RTA).

However, when the film formation temperature of the ALD film formation, for example, a low temperature of 150 to 350 ° C, a solid phase reaction does not occur between the ruthenium oxide film and the ruthenium wafer. On the other hand, although a solid phase reaction can be generated at a high temperature of 900 ° C, it is deuterated (HfSiO _x is desorbed to become HfSi) and cannot function as an insulating film. That is, in order to form a solid phase reaction between the ruthenium oxide film and the tantalum wafer, the heat treatment temperature needs to be higher than the film formation temperature of the ALD film formation, and lower than the temperature of the ruthenium formation. .

Therefore, the heat treatment temperature is 600 to 850 ° C, preferably 650 to 850 ° C, for example, 750 ° C in the present embodiment.

One cycle was repeated five times by the ALD method for the ruthenium oxide film formation and heat treatment, and an extremely thin bismuth film (HfSiO _x -IL formation) as a junction layer was formed on the surface of the ruthenium wafer.

Next, a mechanism for forming a solid phase reaction between a hafnium oxide (HfO ₂ ) film formed on a tantalum wafer and a tantalum wafer when an extremely thin tantalate film (HfSiO _x ) film is formed will be described with reference to FIG.

After the completion of the HF cleaning process in Fig. 14(a), the yttrium oxide film formation process (first time) in Fig. 14(b) is performed by forming a hafnium oxide (HfO ₂ ) film on a germanium wafer by one cycle of ALD. .

In the heat treatment process (first time) of Fig. 14 (c), the Hf atoms in the HfO ₂ film are diffused into the germanium wafer. At this time, Si atoms in the germanium wafer are released to form a Hf-O_Si bond. In addition, a portion of the O oxidizes the germanium wafer while releasing the Si in the germanium wafer.

In this way, an HfSiO _x film is formed on the surface of the germanium wafer. At this stage, an HfSiO _x film of less than (underfill) 1 atomic layer is formed.

In the ruthenium oxide film formation process of FIG. 14(d) (a solid phase reaction is formed between the HfO ₂ film and the ruthenium wafer to form an HfSiO _x film.

In the heat treatment process (second time) of Fig. 14(e), the Hf atoms in the HfO ₂ film are diffused into the germanium wafer. At this time, Si atoms in the germanium wafer are released to form a Hf-O_Si bond. In addition, a portion of the O oxidizes the germanium wafer while releasing the Si in the germanium wafer. At this stage, an atomic layer of HfSiO _x film is formed on the surface of the wafer.

After the third time, the reaction between the HfSiO _x film and the germanium wafer, and the reaction of the HfO ₂ film and the HfSiO _x film are suppressed, so that the diffusion of Si into the HfSiO _x film from the germanium wafer is suppressed, and further, from HfSiO _x The diffusion of Si into the HfO film in the film is also suppressed. Therefore, the solid phase reaction ends after several times, and does not occur more than a certain number of times.

In the present embodiment, the solid phase reaction was repeated five times.

As described above, a solid phase reaction occurs between the HfO ₂ film and the germanium wafer to form an HfSiO _x film.

Further, the ruthenium oxide film formation process and the heat treatment process of repeating ALD of 5 times can form an extremely thin tantalate film, but even if it is repeated 6 times, a ruthenium oxide film is formed only on the extremely thin tantalate film. .

The reason is as follows.

That is, the bismuthation caused by heat treatment between the HfO ₂ film and the ruthenium wafer is mainly caused by a pure solid phase reaction between the HfO ₂ film and the ruthenium wafer on the first and/or the first time. HfSiO _x film, a silicon wafer is formed after the third time by the previous, and the HfO ₂ film between the solid phase reaction. The original HfO ₂ film and the HfSiO _x film do not easily react, and the germanium wafer and the HfSiO _x film are not easily reacted. Therefore, it is more difficult to generate a solid phase reaction (Si is hardly adsorbed to the HfO ₂ film) after the third time. Thus with the number of repetitions increases, reducing the Si concentration of the surface most HfSiO _x film, the surface becomes enriched in the most of HfSiO _x Hf film. In this embodiment, after repeated 5 times, the concentration of each element of the slope between the HfSiO _x film and HfO ₂ film is almost a state (state of extremely small) non-existent, and become unable to produce a solid phase reaction, i.e. silicic acid Salinization.

Therefore, the ruthenium oxide film formation process and the heat treatment process of the ALD method of one cycle can be repeated five times or less. The film thickness may be 0.4 nm or less.

Also, the germanium wafer is a single crystal. The single crystal is a crystal in which the Si atoms are arranged in a uniform order, and the crystal orientation is regular and becomes a certain direction. Therefore, the defect of the germanium wafer is small, the amount of impurities is small, and the trap is small. When the tantalum wafer and the HfO ₂ film are directly subjected to a solid phase reaction by heat treatment, defects such as defects, impurities, or traps are formed, and the Hf and Si concentration distributions in the film are less changed due to the characteristics of the tantalum wafer. HfSiO _x film.

As described above, the solid phase reaction of the tantalum wafer with the heat treatment of the HfO ₂ film is repeated five times (when the film thickness is 0.4 nm), so that the film thickness of the HfSiO _x film can be controlled to be thin.

On the other hand, an SiON (yttrium oxynitride) film or a Si ₃ N ₄ (yttrium nitride) film or a Si ₃ O ₂ film is an amorphous film. The amorphous film is in a dispersed state in which the Si atoms are irregularly arranged, and there are many defects or impurities or traps. When the HfO ₂ film is reacted with such a SiON (yttrium oxynitride) film or a Si ₃ N ₄ (yttrium nitride) film, defects or impurities or traps are formed due to the above characteristics of the SiON film or the Si ₃ N ₄ film. Even a film of a film having a large variation in the concentration distribution of Hf and Si in the film.

Further, a Si ₃ N ₄ film is formed on the wafer, and a hydrogen-containing HfO ₂ film is formed thereon (in this case, the Si ₃ N ₄ film becomes SiON due to the oxidizing agent), and heat treatment is performed to thereby cause Si to be A method in which the wafer side is diffused into the HfO ₂ film to form a Si-containing HfO ₂ film exists.

However, in this method, since heat treatment causes hydrogen (H) to be detached from the SiON film and/or the HfO ₂ film, voids are formed. The Si contained in the germanium wafer or the SiON film diffuses into the HfO ₂ film through the hole, and the Hf contained in the HfO ₂ film diffuses into the SiON film. Therefore, where Si or Hf is released from the individual film, holes, i.e., traps, of the Si or Hf emitting portion (i.e., the hydrogen releasing portion) are formed. Further, hydrogen is present in a random manner in individual films, and thus the Hf concentration or the Si concentration distribution in the individual films may vary.

In contrast, this embodiment is not diffused with hydrogen from the Si and / or Hf to form holes, but the use of solid between the HfO ₂ film and the silicon wafer with the reaction, i.e. using a HfO ₂ film with silicon wafer of the present embodiment Since the atoms are mutually diffused and replaced by the reaction, there is an advantage that the traps are less, and the variation in the concentration distribution of Hf and Si in the film is small as compared with the above method.

After the formation of the extremely thin tantalate film, a hafnium oxide film (formation of a high dielectric constant film) as a high dielectric constant insulating film is formed on the extremely thin tantalate film.

That is, a tantalum oxide film as a high dielectric constant insulating film is formed by the ALD device 40 on the surface of the wafer on which the extremely thin tantalate film is formed.

The treatment conditions are: film formation temperature: 150 to 350 ° C, film formation pressure: 30 Pa, cycle number; 20 to 40 cycles, film thickness: 2 to 4 nm.

After forming a hafnium oxide film as a high dielectric constant insulating film, a nickel telluride (NiSi) as a gate is formed on a hafnium oxide (HfO ₂ ) film for patterning (deposition and patterning of Ni and Si), and then MOSFETs are formed in wiring engineering.

The characteristics of the MOSFET thus formed were tested.

Fig. 5 is a view showing the spectral distribution of the HfSiO _x layer (junction layer) formed by XPS analysis in the present embodiment.

Fig. 6 is a cross-sectional TEM photograph of a high-k gate stack structure when the extremely thin tantalate film of the present embodiment is used as a junction layer.

Figures 7-10 show the characteristics of the MOSFET.

And, on the characteristics of the MOSFET, also made comparative example does not have the configuration of the present embodiment HfSiO _x layer of the embodiment describes the result.

From the XPS spectral distribution of Fig. 5, it was confirmed that according to the present embodiment, a solid phase reaction was formed between the ruthenium oxide film and the tantalum wafer to form a niobate film.

From the cross-sectional TEM photograph of Fig. 6, it was confirmed that a very thin tantalate film of about 0.4 nm was formed.

7 shows a HfSiO _x film embodiment of the present embodiment used as a high dielectric constant (High-k) gate stack junction layer CV characteristics of MOS capacitors configured profile. As can be seen from Fig. 7, according to the high-k gate stack structure using the extremely thin tantalate film of the present embodiment, a large capacity can be obtained, and an EOT of about 0.6 nm can be obtained.

Figure 8 is a graph showing the relationship between EOT and physical film thickness of cerium oxide.

The following can be confirmed by the slice indicating the EOT of the junction layer.

Using a high dielectric constant gate stack structure of a tantalate film, the EOT of the junction layer portion was 0.24 nm, and the dielectric film thickness (about 0.4 nm) obtained by observation of the cross-sectional TEM photograph was used to calculate the dielectric constant. The extremely thin tantalate film of this embodiment has a dielectric constant of about 7, and can form a tantalate film having about 30% germanium.

Further, a high-k gate stack structure having no extremely thin tantalate film, which has a junction layer having an EOT of 0.38 nm, is conceivable as a SiO _x film having a low dielectric constant.

FIG. 9 shows HfSiO _x film embodiment of the present embodiment as the high dielectric constant layer surface profile of the gate stack of the MOS capacitor structure characteristic of the EOT-Jg.

Compared with the gate stack using the hafnium oxide film (SiO ₂ film) as the gate insulating film, the high-k gate stack structure using the extremely thin tantalate film of the present embodiment has a ratio of approximately ¹⁰⁶ times. The advantages of Jg.

In addition, compared with the high-k gate stack structure without the extremely thin tantalate film of the present embodiment, an advantage of approximately 10 ³ times Jg can be obtained.

10 is used in Example of the present embodiment HfSiO _x film as the high dielectric constant layer gate electrode stack surface profile of the effective electron mobility of the electric field lines associated with the MOSFET.

A higher effective electron mobility can be obtained as compared with a high-k gate stack structure without the extremely thin tantalate film of this embodiment.

As described above, with the high-k gate stack structure of the extremely thin tantalate film of the present embodiment as the junction layer, an extremely thin EOT can be obtained, which is excellent in terms of leakage current, and is obtained. Good MOSFET characteristics.

The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit thereof.

For example, in the above embodiment, a collective ALD device is used. The group apparatus of the RTP apparatus is an example of a ruthenium oxide film formation process and a heat treatment process. However, the present invention is not limited thereto, and an example in which the ruthenium oxide film formation process and the heat treatment process are performed in the same process chamber is also applicable.

Moreover, it is not limited to the use of a vane type film forming apparatus and a heat processing apparatus, and a batch type film forming apparatus and a heat processing apparatus are also applicable.

For example, in the above embodiment, the gate insulating film is described. However, the insulating film is not limited to this gate insulating film, and is also applicable to a capacitor insulating film.

For example, in the above embodiment, the metal oxide film for forming the contact layer is formed of the same film as the high dielectric constant insulating film formed on the contact layer, but may be a different film.

Further, the metal oxide film and/or the high dielectric constant insulating film for forming the contact layer are not limited to the use of a hafnium oxide film.

The metal oxide film and/or the high dielectric constant insulating film may be formed of an oxide having a singular or majority element selected from the group consisting of Hf, Ta, Al, Zr, La, and Y, or having such oxidation. An oxide of a stacked structure in which the object is placed up and down.

For example, it may be HfSiO _x , Ta ₂ O ₅ , AL ₂ O ₃ , ZrO ₂ , HfAlO _x , HfAlON, HfON, La ₂ O ₃ , Y ₂ O ₃ , HfO ₂ /AL ₂ O ₃ , HfO ₂ /ZrO ₂ , HfO ₂ /AL ₂ O ₃ /HfO ₂ and the like.

The material for forming the capacitor insulating film may be BST (Ba-Sr-TiO ³ ) or STO (Sr-TiO ³ ).

The substrate to be processed is not limited to the wafer, and may be a substrate such as a glass substrate or a liquid crystal panel in the process of the LCD device.

Preferred aspects of the invention.

A method for fabricating a semiconductor device according to an aspect of the present invention includes: forming a metal oxide film on a germanium substrate, and subjecting the metal oxide film to a solid phase reaction with the germanium substrate by heat treatment to form a tantalate film; Engineering; and engineering of forming a high dielectric constant insulating film on the tantalate film.

It is preferred that the above-mentioned niobate film is formed by repeating the formation of the metal oxide film and the solid phase reaction by the heat treatment.

It is preferred that the above-mentioned niobate film is formed by repeating the formation of the metal oxide film within one atomic layer and the solid phase reaction by the heat treatment.

It is preferred that the above-mentioned niobate film is formed by repeating the formation of the metal oxide film of the ALD method of 1 to 3 cycles and the solid phase reaction of the heat treatment.

Preferably, the heat treatment is performed at a temperature higher than a temperature at which the metal oxide film is formed and a temperature lower than a temperature at which the bismuth salt film is ruthenium.

Preferably, the metal oxide film is the same film as the high dielectric constant insulating film.

Preferably, the metal oxide film and the high dielectric constant insulating film are hafnium oxide (Hf) films, and the niobate film is a niobate film.

According to another aspect of the present invention, a method for fabricating a semiconductor device includes: forming a high dielectric constant insulating film on a germanium substrate, and solid-reacting the high dielectric constant insulating film with the germanium substrate by heat treatment And repeating the process of forming a niobate film; and forming a high dielectric constant insulating film on the niobate film.

According to still another aspect of the present invention, in a method of manufacturing a semiconductor device, a ruthenium oxide film is formed on a ruthenium substrate, and the ruthenium oxide film is subjected to a solid phase reaction with the ruthenium substrate by heat treatment, and is formed by repeating Engineering of a bismuth film; and engineering of forming a yttrium oxide film on the bismuth film.

According to still another aspect of the present invention, a substrate processing apparatus includes: a first processing chamber for forming a high dielectric constant insulating film on a germanium substrate; and a second processing chamber for performing heat treatment of the germanium substrate The transfer chamber is disposed between the first processing chamber and the second processing chamber, and transports the crucible substrate between the first processing chamber and the second processing chamber, and transports the robot arm in the transfer chamber. And transmitting, by the controller, the ruthenium substrate to the first processing chamber by the transfer robot arm, and forming the high dielectric constant insulation on the ruthenium substrate in the first processing chamber In the film, the germanium substrate on which the high dielectric constant insulating film is formed is transferred from the first processing chamber to the second processing chamber, and the high dielectric is formed in the second processing chamber. The tantalum substrate of the coefficient insulating film is subjected to heat treatment, and the high dielectric constant insulating film is solid-phase reacted with the tantalum substrate to form a niobate film, and the operation is repeated. a tantalate film having a specific film thickness is formed on the surface of the substrate, and then the tantalum substrate having the specific thickness of the tantalate film formed is transferred from the second processing chamber to the first processing chamber. A high dielectric constant insulating film is formed on the niobate film of the above specific film thickness in the processing chamber.

(effect of the invention)

According to the above means, the method for manufacturing a semiconductor device and the substrate processing device can prevent the influence on electrical characteristics and can thin the EOT.

1‧‧‧FOUP

2‧‧‧ Wafer (substrate to be processed)

10‧‧‧Group device (substrate processing device)

11‧‧‧Negative pressure transfer chamber (substrate transfer chamber)

12‧‧‧ Negative pressure transfer chamber frame

13‧‧‧Negative pressure transfer device (wafer transfer device)

14‧‧‧ moving into the room (preparation room for moving in)

15‧‧‧ Moving out of the room (preparation room for moving out)

16‧‧‧ Positive pressure transfer chamber (wafer transfer chamber)

19‧‧‧ Positive pressure transfer device (wafer transfer device)

24‧‧‧FOUP opener

25‧‧‧Station

31‧‧‧1st processing unit

32‧‧‧2nd processing unit

33‧‧‧3rd processing unit

34‧‧‧4th processing unit

37‧‧‧ Controller

40‧‧‧ALD device

110‧‧‧RTP device

1 is a flow chart showing a process of forming a gate insulating film of a MOSFET according to an embodiment of the present invention.

Figure 2 is a plan sectional view showing a cluster device according to an embodiment of the present invention.

Fig. 3 is a front sectional view showing the ALD apparatus in the group apparatus according to the embodiment of the present invention.

Fig. 4 is a front sectional view showing the RTP apparatus in the group apparatus according to the embodiment of the present invention.

Fig. 5 is a view showing the spectrum distribution of the HfSiO _x layer formed by XPS analysis in the examples.

Fig. 6 is a cross-sectional TEM photograph of a high dielectric gate stack structure when the tantalate film of the embodiment is used as a junction layer.

Fig. 7 is a CV characteristic distribution diagram of a capacitor of a MOSFET in the embodiment and the comparative example.

Fig. 8 is a graph showing the relationship between EOT and the physical film thickness of cerium oxide in Examples and Comparative Examples.

Fig. 9 is a distribution diagram of EOT-Jg characteristics in Examples and Comparative Examples.

Fig. 10 is a distribution diagram showing the relationship of the electric field of the effective electron mobility in the examples and the comparative examples.

Figure 11 is a flow chart showing the construction of the MOSFET of the embodiment.

Fig. 12 is a flow chart showing a process of forming a gate insulating film of a MOSFET of the embodiment and a cross-sectional view thereof.

Figure 13 is a cross-sectional view showing the film formation process of the ALD method.

Figure 14 is a flow chart and a cross-sectional view showing the process and mechanism for producing a solid phase reaction.

Claims (22)

A method of manufacturing a semiconductor device comprising: a process of forming a tantalate film by performing the following processes: performing a first process of forming a metal oxide film on a single crystal germanium substrate, and by using the metal oxide film a single crystal enthalpy on the surface of the ruthenium substrate, a heat treatment different from the treatment performed in the first project, and a second process in which a solid phase reaction occurs; After the formation of the niobate film, a high dielectric constant insulating film is formed on the above-described niobate film. The method of manufacturing a semiconductor device according to claim 1, wherein the first project and the second project are alternately repeated in the process of forming the niobate film. The method of manufacturing a semiconductor device according to claim 1, wherein in the first aspect, the metal oxide film is formed within one atomic layer. The method of manufacturing a semiconductor device according to claim 1, wherein in the first aspect, the metal oxide film is formed by an ALD method of one to three cycles. The method of manufacturing a semiconductor device according to claim 1, wherein the heat treatment in the second project is compared to the first project The temperature at which the metal oxide film is formed at a high temperature is high at a temperature lower than the temperature at which the above-described tantalate film is cleaved. The method of manufacturing a semiconductor device according to claim 1, wherein the metal oxide film and the high dielectric constant insulating film are made of the same material. The method of manufacturing a semiconductor device according to claim 1, wherein the metal oxide film and the high dielectric constant insulating film are hafnium oxide (Hf) films, and the niobate film is a niobate film. A method of manufacturing a semiconductor device, comprising: performing a process of repeatedly performing the following processes to form a tantalate film: a first process of performing a process of forming a high dielectric constant insulating film on a single crystal germanium substrate, and The high dielectric constant insulating film and the single crystal germanium on the surface of the germanium substrate are subjected to a heat treatment different from the treatment performed in the first engineering in a process different from the first engineering to cause a solid phase reaction. The second project; and the process of forming a high dielectric constant insulating film on the above-described tantalate film after the formation of the above-described tantalate film. A method of manufacturing a semiconductor device comprising: a process of forming a tantalate film by repeating the following processes: performing a first process of forming a tantalum oxide film on a single crystal germanium substrate, and heat treating the tantalum oxide The single crystal enthalpy of the film and the surface of the ruthenium substrate is different from the first project described above, and the first work is performed The second heat treatment is performed to treat the second phase of the solid phase reaction, and after the formation of the tantalate film, the tantalum oxide film is formed on the tantalate film. A substrate processing apparatus comprising: a first processing chamber for forming a high dielectric constant insulating film on a single crystal germanium substrate; a second processing chamber for performing heat treatment of the germanium substrate; and a transfer chamber provided in the first Between the processing chamber and the second processing chamber, the sputum substrate is transported between the first processing chamber and the second processing chamber; the robot arm is transported in the transfer chamber for transporting the cymbal substrate; and the control is performed The apparatus is configured to form a bismuth film having a specific film thickness on the surface of the ruthenium substrate by repeating the first and second processes described below, and then to apply the specific film thickness The tantalum substrate after the formation of the niobate film is transported into the first processing chamber by the second processing chamber, and a high dielectric constant insulating film is formed on the niobate film having the specific thickness in the first processing chamber; In the first process, the germanium substrate is transferred to the first processing chamber by the transfer robot, and the high dielectric constant insulating film is formed on the germanium substrate in the first processing chamber; Li, the transportation system by the robot arm above-described silicon substrate forming the high dielectric constant insulating film by the first transfer chamber to the processing chamber to the second process, in the second processing chamber to The tantalum substrate on which the high dielectric constant insulating film is formed is subjected to heat treatment different from the first treatment, and the high dielectric constant insulating film is solid-phase reacted with the single crystal germanium on the surface of the tantalum substrate. A method of manufacturing a semiconductor device comprising: a process of forming a tantalate film by repeating the following processes: performing a first process of forming a metal oxide film on a single crystal germanium substrate, and oxidizing the metal oxide a single crystal enthalpy on the surface of the ruthenium substrate and the first crystallization of the ruthenium substrate, and a heat treatment different from the treatment performed in the first project to perform a second phase of solid phase reaction; After the above-described tantalate film is formed, a high dielectric constant insulating film is formed on the above-described tantalate film. The method of manufacturing a semiconductor device according to claim 11, wherein the film thickness of the metal oxide film formed in the first process is within one atomic layer. The method of manufacturing a semiconductor device according to claim 11, wherein in the first aspect, the metal oxide film is formed by an ALD method of one to three cycles. The method of manufacturing a semiconductor device according to claim 11, wherein in the first project, the metal oxide film is subjected to one cycle of the following steps (a) and (b), and the cycle is performed for one to three cycles. To form: (a) a process of adsorbing a raw material on the surface of the crucible substrate; and (b) a process of reacting the raw material adsorbed on the surface of the crucible substrate with an oxidizing agent. The method of manufacturing a semiconductor device according to claim 11, wherein the first engineering is performed in a processing chamber, and the metal oxide film is subjected to the following (a), (b), (c), and (d) engineering. In one cycle, the cycle of 1 to 3 cycles is performed to form: (a) a process of supplying a raw material into the processing chamber; and (b) a process of purifying the processing chamber to perform exhausting of the raw material in the processing chamber; (c) a process of supplying an oxidizing agent to the processing chamber; and (d) a process of purifying the oxidizing agent by purifying the oxidizing agent by purifying the processing chamber. The method of manufacturing a semiconductor device according to claim 11, wherein in the first aspect, the metal oxide film is formed by an ALD method of one cycle. The method of manufacturing a semiconductor device according to claim 11, wherein in the first aspect, the metal oxide film is formed by one cycle of the following (a) and (b), and is formed by one cycle of the cycle. (a) a process of adsorbing a raw material on the surface of the above-mentioned tantalum substrate; and (b) oxidizing the above-mentioned raw material adsorbed on the surface of the tantalum substrate The agent reacts to the project. The method of manufacturing a semiconductor device according to claim 11, wherein the first engineering is performed in a processing chamber, and the metal oxide film is subjected to the following (a), (b), (c), and (d) engineering. In one cycle, the cycle of one cycle is performed to form: (a) a process of supplying a raw material into the processing chamber; (b) a process of purifying the processing chamber and performing the exhaust of the raw material in the processing chamber; a process of supplying an oxidizing agent to the processing chamber; and (d) performing a process of purifying the oxidizing agent by purifying the oxidizing agent in the processing chamber. The method of manufacturing a semiconductor device according to claim 11, wherein the number of repetitions of the first project and the second project in the process of forming the tantalate film is five or less. The method of producing a semiconductor device according to claim 11, wherein the film thickness of the bismuth salt film is 0.4 nm or less. A substrate processing method comprising: a process of forming a tantalate film by performing the following processes: performing a first process of forming a metal oxide film on a single crystal germanium substrate, and by using the metal oxide film and the above The single crystal enthalpy on the surface of the substrate is different from the first project described above, and is carried out in the first project. The second process of producing a solid phase reaction is performed by a different heat treatment, and a process of forming a high dielectric constant insulating film on the tantalate film after the formation of the above-described tantalate film. A substrate processing method comprising: a process of forming a tantalate film by repeating the following processes: performing a first process of forming a metal oxide film on a single crystal germanium substrate, and heat-treating the metal oxide film and The single crystal enthalpy on the surface of the ruthenium substrate is subjected to a heat treatment different from the treatment performed in the first project in a process different from the first project, so that the second phase of the solid phase reaction is generated; After the formation of the acid salt film, a high dielectric constant insulating film is formed on the above-described tantalate film.