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TWI452667B - 具有空腔結構之半導體封裝元件及其封裝方法 - Google Patents

具有空腔結構之半導體封裝元件及其封裝方法 Download PDF

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Publication number
TWI452667B
TWI452667B TW099142957A TW99142957A TWI452667B TW I452667 B TWI452667 B TW I452667B TW 099142957 A TW099142957 A TW 099142957A TW 99142957 A TW99142957 A TW 99142957A TW I452667 B TWI452667 B TW I452667B
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Taiwan
Prior art keywords
die
carrier
semiconductor package
cavity structure
active
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TW099142957A
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English (en)
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TW201225245A (en
Inventor
Longqiang Zu
Yu Yu Lin
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Global Unichip Corp
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Priority to TW099142957A priority Critical patent/TWI452667B/zh
Priority to US12/929,549 priority patent/US8247909B2/en
Publication of TW201225245A publication Critical patent/TW201225245A/zh
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Publication of TWI452667B publication Critical patent/TWI452667B/zh

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

具有空腔結構之半導體封裝元件及其封裝方法
本發明係有關於一種半導體封裝元件，特別是有關於一種具有空腔結構之半導體封裝元件。
首先，請參考第1圖，係表示習知技術之球柵式陣列封裝元件之截面示意圖。球柵式陣列封裝元件100具有一半導體晶粒120設置在載板或基板110上，且利用導線130與載板110形成電性連接。在相對於設置晶粒120的載板110的表面上設置複數個連接元件150。
然而，在習知的封裝技術中，由於環氧樹脂(epoxy resin)封裝材料140具有高介電常數(介電常數約大於2)，當環氧樹脂與具高敏感性元件，例如特殊應用積體電路(Application-specific integrated circuit)元件直接接觸時，會干擾由元件所產生的毫米波(millimeter wave)。由於具有高介電常數的環氧樹脂會改變訊號的波傳導速度，因此，在傳導的過程中會造成訊號衰減的問題。當波傳導經過不同的材質時，不同的介電常數會導致於不同的傳導速度且藉此會造成訊號的失真(distortion)。為了避免訊號的失真，在選擇封裝材料140時需避免使用具有高介電常數的材料。然而，在具有以打線製程所形成的導線的封裝結構中，仍須要環氧封裝化合物來保護這些導線，而這些環氧封裝化合物的介電常數通常大於4，仍然還是會造成元件訊號失真的問題。
根據上述習知技術之問題，本發明的主要目的係在封裝元件中設置一空腔結構使得封裝體可以遠離高敏感性的積體電路元件。
本發明的另一目的係利用空腔結構做為誘導裝置係將封裝體或是其他的有機材料與高敏感性之積體電路元件分離，以避免造成訊號傳送衰減。
根據上述目的，本發明揭露一種具有空腔結構之半導體封裝元件之封裝方法，包括：提供第一晶粒，具有主動面及背面，且於主動面上具有複數個焊墊；提供第一晶粒，具有主動面及背面，且於主動面上具有複數個焊墊；提供載板，具有上表面及下表面，於上表面配置有複數個第一連接端點及於下表面配置有相對於複數個第一連接端點之複數個第二連接端點；貼附第一晶粒在該載板上，係將第一晶粒之主動面朝上將第一晶粒之背面貼附在載板上；提供第二晶粒，具有上表面及背面，且於該上表面之上具有空腔結構；貼附第二晶粒在第一晶粒之主動面上，係將上表面朝下，貼附在第一晶粒之主動面上，使得空腔為倒U型結構設置在第一晶粒之主動面及第二晶粒之上表面之間；執行打線製程以形成複數條導線以電性連接第一晶粒之主動面上之複數個焊墊及載板之上表面之複數個第一連接端點；執行塑封步驟，形成一高分子材料以包覆第一晶粒、第二晶粒、複數條導線及載板之上表面以形成一封裝體；及形成複數個連接元件在載板之下表面且與配置於下表面之複數個第二連接端點電性連接。
根據上述之封裝方法，本發明還揭露一種具有空腔結構之半導體封裝元件，包含：載板，具有上表面及下表面，於上表面配置有複數個第一連接端點及於該下表面配置有相對於複數個第一連接端點之複數個第二連接端點；第一晶粒，具有主動面及背面，且於主動面上配置有複數個焊墊，且以主動面朝上將第一晶粒之背面設置在載板之上表面上；第二晶粒，具有上表面及背面，且於上表面之上具有空腔結構，且以上表面朝下將第二晶粒朝下設置在第一晶粒之主動面上，且空腔結構為倒U型結構設置在第一晶粒之主動面及第二晶粒之上表面之間；複數條導線，係用以電性連接第一晶粒之主動面上之複數個焊墊及載板上之複數個第一連接端點；一封裝體，用以包覆第一晶粒、第二晶粒、複數條導線、及載板之部份上表面；及複數個連接元件，設置在載板之下表面且與下表面之複數個第二連接端點電性連接。
為了讓本發明之上述和其他目的、特徵和優點能更明顯易懂，下文特舉一較佳實施例，並配合所附之圖示，做詳細說明如下。
製造及使用本發明之較佳實施例係詳細說明如下。必須瞭解的是本發明提供了許多可應用的創新概念，在特定的背景技術之下可以做廣泛的實施。此特定的實施例僅以特定的方式表示，以製造及使用本發明，但並非限制本發明的範圍。
首先請參考第2圖，係先提供一載板10，其具有一上表面12及一下表面14，且在上表面12具有複數個第一連接端點(未在圖中表示)及在下表面14具有相對應複數個第一連接端點之複數個第二個連接端點(未在圖中表示)，且複數個第一連接端點與複數個第二連接端點彼此電性連接，其中載板10可以是印刷電路板或是可撓性印刷電路板。在本發明的實施例中，於載板10內形成第一連接端點及第二連接端點之方法係為眾所皆知之技術，因此不在此多加贅述。
接著，係提供一晶圓(未在圖中表示)，其具有一上表面(未在圖中表示)其一下表面(未在圖中表示)，且配置有複數個晶粒20。接著，利用切割刀(未在圖中表示)根據晶圓上的切割線(未在圖中表示)切割該晶圓，以得到複數個晶粒20。在此實施例中，每一個晶粒20具有一主動面21及一背面23，且每一個晶粒20之主動面21上配置有複數個焊墊24。接著，將已經完成切割且檢測良好的至少一顆晶粒20以主動面22朝上的方式，置放在載板10的上表面12。在此實施例中，更包含一黏著層(未在圖中表示)設置在晶粒20之背面23及載板10之上表面12之間，用以固著晶粒20在載板10之上表面12之上。在此，晶粒20為高敏感性的特殊應用積體電路元件(Application-specific integrated circuit,ASIC)。
接著，請參考第3圖，積體電路元件20上設有高敏感性的電子材料，為了得到較佳的電子效能，且避免習知技術中環氧樹脂與具有高敏感性電子材料的積體電路元件20直接接觸，因此係將具有空腔結構(fillister)32之另一晶粒30做為一蓋體(cap)，將具有空腔結構32的一面(即為上表面)設置在晶粒20之主動面21上，晶粒30(蓋體結構)僅覆蓋晶粒20之主動面21上具有高敏感性電子材料處，而不會覆蓋到配置於晶粒20之主動面21上之複數個焊墊24，使得空腔結構32為一倒U型(inverse U-type)結構設置在晶粒20與晶粒30之間。因此藉由此空腔結構32可以將高敏感性的特殊應用積體電路元件20與後續的封裝材料(未在圖中表示)有效的分離，而降低元件傳送訊號衰減的問題。在本實施例中，於晶粒30上形成空腔結構32的方式係包含：提供一晶粒30，接著利用化學蝕刻(chemical etching)或是物理切割(physical cutting)方式在該晶粒30之上表面(未在圖中表示)上形成一空腔結構32；且第二晶粒30可以是玻璃。此外，在晶粒30之上表面(未在圖中表示)及晶粒20之主動面21之間更包含一黏著層(未在圖中表示)，係將晶粒30固定在晶粒20之主動面21上。
接著，請參考第4圖係表示利用導線電性連接晶粒及載板之截面示意圖。在第4圖中，係利用打線製程(wire bonding process)將複數條導線40形成在晶粒20的主動面21的複數個焊墊24上，且與配置在載板10之上表面12之複數個第一連接端點(未在圖中表示)彼此電性連接。
緊接著，請參考第5圖，係表示執行一塑封步驟以形成封裝體包覆晶粒及導線及部份載板之上表面之截面示意圖。在第5圖中，係將一高分子材料例如環氧樹脂(epoxy resin)形成在晶粒20上，用以包覆住晶粒20、晶粒30、複數條導線40及載板10之部份上表面12以形成一封裝體50。
接著，同樣參考第5圖，係將複數個連接元件60形成在載板10之下表面14，且與下表面14之複數個第二連接端點(未在圖中表示)電性連接，在此實施例中，連接元件60可以是錫球(solder ball)。
根據以上所述，在目前的封裝製程中，貼附一蓋體結構30在特殊應用積體電路元件之步驟係為廣泛且為一般常使用之技術步驟。此種堆疊晶粒的方式類似於系統級封裝(SIP,system in package)結構。在形成蓋體結構30之後，依序形成導線、封裝體以及植球，以完成一封裝步驟。此意味著，在本發明中所揭露之具有空腔結構之半導體封裝元件係為一高品質且可實施之封裝方法，經由此方法所形成之半導體封裝元件可以控制該元件之毫米波(millimeter wave)特性，同時也可以降低封裝成本。簡而言之，具有毫米波之電路可以藉由具有空腔結構之蓋體來保護而使得所產生的訊號不會被干擾，使得元件有較佳的可靠度。
以上所述僅為本發明之較佳實施例而已，並非用以限定本發明之申請專利範圍；凡其它未脫離本發明所揭示之精神下所完成之等效改變或修飾，均應包含在下述之申請專利範圍內。
10．．．載板
12．．．上表面
14．．．下表面
20．．．晶粒
21．．．主動面
23．．．背面
24．．．焊墊
30．．．晶粒
32．．．空腔結構
40．．．導線
50．．．封裝體
60．．．連接元件
100．．．球柵式陣列封裝元件
110．．．載板
120．．．半導體晶粒
130．．．導線
140．．．封裝體
150．．．連接元件
第1圖係根據習知技術，表示習知之球柵式陣列封裝元件之截面示意圖；
第2圖係根據本發明所揭露之技術，表示具有晶粒之載板之截面示意圖；
第3圖係根據本發明所揭露之技術，表示貼附一晶粒在晶粒之主動面上之截面示意圖；
第4圖係根據本發明所揭露之技術，表示形成複數條導線以電性連接晶粒及載板之截面示意圖；及
第5圖係根據本發明所揭露之技術，表示形成一封裝體以包覆第4圖所形成之結構及形成複數個連接元件之截面示意圖。
10．．．載板
12．．．上表面
14．．．下表面
20．．．晶粒
21．．．主動面
23．．．背面
24．．．焊墊
30．．．晶粒
32．．．空腔結構
40．．．導線
50．．．封裝體
60．．．導電元件

Claims (20)

  1. 一種具有空腔結構之半導體封裝元件之封裝方法，包括：提供一第一晶粒，具有一主動面及一背面，且於該主動面上具有複數個焊墊；提供一載板，具有一上表面及一下表面；貼附該第一晶粒在該載板上，係將該第一晶粒之該主動面朝上將該第一晶粒之該背面貼附在該載板上；提供一第二晶粒，具有一上表面及一背面，且於該上表面上具有一空腔結構；貼附該第二晶粒在該第一晶粒之該主動面上，係將該上表面朝下，貼附在該第一晶粒之該主動面上，使得該空腔結構為一倒U型結構設置在該第一晶粒之該主動面及該第二晶粒之該上表面之間；執行一打線製程以形成複數條導線以電性連接該第一晶粒之該主動面上之該些焊墊及該載板之該上表面；執行一塑封步驟，形成一高分子材料以包覆該第一晶粒、該第二晶粒、該些導線及該載板之該上表面以形成一封裝體；以及形成複數個連接元件在該載板之該下表面且與配置於該下表面電性連接。
  2. 如申請專利範圍第1項所述之封裝方法，其中該載板為印刷電路板。
  3. 如申請專利範圍第1項所述之封裝方法，其中該載板為可撓性印刷電路板。
  4. 如申請專利範圍第1項所述之封裝方法，更包含一黏著層在該載板之該上表面與該第一晶粒之該背面之間。
  5. 如申請專利範圍第1項所述之封裝方法，更包含一黏著層在該第二晶粒之該上表面及該第一晶粒之該主動面之間。
  6. 如申請專利範圍第1項所述之封裝方法，其中該第二晶粒之該空腔結構的形成方式包含化學蝕刻(chemical etching)。
  7. 如申請專利範圍第1項所述之封裝方法，其中該第二晶粒之該空腔結構的形成方式包含物理切割(physical cutting)。
  8. 如申請專利範圍第1項所述之封裝方法，其中該第一晶粒及該第二晶粒之功能及尺寸不同。
  9. 如申請專利範圍第1項所述之封裝方法，其中該第一晶粒為一特殊應用積體電路(Application-specific integrated circuit,ASIC)。
  10. 如申請專利範圍第1項所述之封裝方法，其中該高分子材料為環氧樹脂(epoxy resin)。
  11. 如申請專利範圍第1項所述之封裝方法，其中該連接元件為錫球(solder ball)。
  12. 一種具有空腔結構之半導體封裝元件，包含：一載板，具有一上表面及一下表面；一第一晶粒，具有一主動面及一背面，且於該主動面上配置有複數個焊墊，且以該主動面朝上將該第一晶片之該背面設置在該載板之該上表面上；一第二晶粒，具有一上表面及一背面，且於該上表面之上具有一空腔結構，且以該上表面朝下將該第二晶片朝下設置在該第一晶粒之該主動面上，且該空腔結構為一倒U型結構設置在該第一晶粒之該主動面及該第二晶粒之該上表面之間；複數條導線，係用以電性連接該第一晶粒之該主動面上之該些焊墊及該載板；一封裝體，用以包覆該第一晶粒、該第二晶粒、該些導線、及該載板之部份該上表面；以及複數個連接元件，設置在該載板之該下表面且與該下表面電性連接。
  13. 如申請專利範圍第12項所述之半導體封裝元件，其中該載板為印刷電路板。
  14. 如申請專利範圍第12項所述之半導體封裝元件，其中該載板為可撓性印刷電路板。
  15. 如申請專利範圍第12項所述之半導體封裝元件，更包含一黏著膠在該載板之該上表面與該第一晶粒之該背面之間。
  16. 如申請專利範圍第12項所述之半導體封裝元件，更包含一黏著層在該第二晶粒之該上表面及該第一晶粒之該主動面之間。
  17. 如申請專利範圍第12項所述之半導體封裝元件，其中該第一晶粒及該第二晶粒之功能及尺寸不同。
  18. 如申請專利範圍第12項所述之半導體封裝元件，其中該第一晶粒為一特殊應用積體電路(Application-specific integrated circuit,ASIC)。
  19. 如申請專利範圍第12項所述之半導體封裝元件，其中該封裝體為環氧樹脂(epoxy resin)。
  20. 如申請專利範圍第12項所述之半導體封裝元件，其中該連接元件為錫球(solder ball)。
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US9786609B2 (en) 2013-11-05 2017-10-10 Analog Devices Global Stress shield for integrated circuit package
US10418294B1 (en) 2018-05-15 2019-09-17 Texas Instruments Incorporated Semiconductor device package with a cap to selectively exclude contact with mold compound
US20210296196A1 (en) 2020-03-20 2021-09-23 Texas Instruments Incorporated Semiconductor device package with reduced stress

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