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TWI449155B - Semiconductor package and method for making the same - Google Patents

Semiconductor package and method for making the same Download PDF

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Publication number
TWI449155B
TWI449155B TW101109213A TW101109213A TWI449155B TW I449155 B TWI449155 B TW I449155B TW 101109213 A TW101109213 A TW 101109213A TW 101109213 A TW101109213 A TW 101109213A TW I449155 B TWI449155 B TW I449155B
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Taiwan
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substrate
pad
die
semiconductor package
package structure
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TW101109213A
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Chinese (zh)
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TW201340291A (en
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Seokbong Kim
Yuyong Lee
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Advanced Semiconductor Eng
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Publication of TWI449155B publication Critical patent/TWI449155B/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

半導體封裝結構及其製造方法Semiconductor package structure and method of manufacturing same

本發明係關於一種半導體封裝結構及其製造方法,詳言之,係關於一種堆疊式半導體封裝結構及其製造方法。The present invention relates to a semiconductor package structure and a method of fabricating the same, and more particularly to a stacked semiconductor package structure and a method of fabricating the same.

習知堆疊式半導體封裝結構具有一上封裝結構、一下封裝結構及複數個銲球。該等銲球係位於該下封裝結構之基板上。該上封裝結構之下表面係接觸該等銲球,以電性連接至該下封裝結構。在該習知堆疊式半導體封裝結構中,該等銲球係為球狀,因此二個銲球間之間距無法有效縮小,否則容易發生橋接(Bridge)的問題,進而造成短路的情況。The conventional stacked semiconductor package structure has an upper package structure, a lower package structure, and a plurality of solder balls. The solder balls are located on the substrate of the lower package structure. The underlying surface of the upper package structure contacts the solder balls to electrically connect to the lower package structure. In the conventional stacked semiconductor package structure, the solder balls are spherical, so that the distance between the two solder balls cannot be effectively reduced, otherwise the problem of bridging is likely to occur, thereby causing a short circuit.

因此,有必要提供一種半導體封裝結構及其製造方法,以解決上述問題。Therefore, it is necessary to provide a semiconductor package structure and a method of fabricating the same to solve the above problems.

本發明提供一種半導體封裝結構,其包括一第一基板、一第一晶粒、一第一封膠、一第二基板及至少一導通柱。該第一基板具有一上表面及一下表面。該第一晶粒鄰接於該第一基板之上表面,且電性連接至該第一基板之上表面。該第一封膠包覆該第一晶粒及該第一基板之上表面。該第二基板具有一上表面及一下表面,該第二基板之下表面係黏附於該第一封膠上。該導通柱貫穿該第一基板、該第一封膠及該第二基板。The present invention provides a semiconductor package structure including a first substrate, a first die, a first seal, a second substrate, and at least one via. The first substrate has an upper surface and a lower surface. The first die is adjacent to the upper surface of the first substrate and electrically connected to the upper surface of the first substrate. The first sealant covers the first die and the upper surface of the first substrate. The second substrate has an upper surface and a lower surface, and the lower surface of the second substrate is adhered to the first sealing material. The conductive pillar penetrates the first substrate, the first sealant, and the second substrate.

在本發明中,該導通柱係用以作為垂直方向電性連接之元件。由於該導通柱之外徑比習知銲球小,因此可縮小彼此間距且增加密度。In the present invention, the conductive post is used as an element that is electrically connected in the vertical direction. Since the outer diameter of the via post is smaller than a conventional solder ball, the pitch between the two can be reduced and the density can be increased.

本發明另提供一種半導體封裝結構之製造方法,其包括以下步驟:(a)提供一第一基板,該第一基板具有一上表面及一下表面;(b)附著一第一晶粒於該第一基板之上表面,且電性連接該第一晶粒至該第一基板之上表面;(c)形成一第一封膠以包覆該第一晶粒及該第一基板之上表面;(d)提供一第二基板,該第二基板具有一上表面及一下表面,且黏附該第二基板之下表面於該第一封膠上;(e)形成至少一貫穿孔以貫穿該第一基板、該第一封膠及該第二基板;及(f)形成一導電金屬於該至少一貫穿孔內以形成至少一導通柱。The present invention further provides a method of fabricating a semiconductor package structure, comprising the steps of: (a) providing a first substrate having an upper surface and a lower surface; and (b) attaching a first die to the first a first surface of the substrate, and electrically connecting the first die to the upper surface of the first substrate; (c) forming a first sealant to cover the first die and the upper surface of the first substrate; (d) providing a second substrate having an upper surface and a lower surface, and adhering the lower surface of the second substrate to the first seal; (e) forming at least a uniform perforation to penetrate the first a substrate, the first encapsulant and the second substrate; and (f) forming a conductive metal in the at least one of the perforations to form at least one via post.

參考圖1,顯示本發明半導體封裝結構之一實施例之示意圖。該半導體封裝結構1包括一第一基板10、一第一晶粒12、複數條第一導線13、一第一封膠14、一第二基板16、一第二晶粒18、複數條第二導線19、一第二封膠20、至少一導通柱22、一中間膠層24及複數個銲球26。Referring to Figure 1, a schematic diagram of one embodiment of a semiconductor package structure of the present invention is shown. The semiconductor package structure 1 includes a first substrate 10, a first die 12, a plurality of first wires 13, a first seal 14, a second substrate 16, a second die 18, and a plurality of second The wire 19, a second sealant 20, at least one conductive post 22, an intermediate adhesive layer 24, and a plurality of solder balls 26.

該第一基板10,例如一有機基板,具有一上表面101、一下表面102、至少一第一上銲墊103及至少一第一下銲墊104。該至少一第一上銲墊103係鄰接於該第一基板10之上表面101,該至少一第一下銲墊104係鄰接於該第一基板10之下表面102。The first substrate 10, such as an organic substrate, has an upper surface 101, a lower surface 102, at least a first upper bonding pad 103, and at least one first lower bonding pad 104. The at least one first upper pad 103 is adjacent to the upper surface 101 of the first substrate 10 , and the at least one first lower pad 104 is adjacent to the lower surface 102 of the first substrate 10 .

該第一晶粒12鄰接於該第一基板10之上表面101,且電性連接至該第一基板10之上表面101。在本實施例中,該第一晶粒12係利用一第一膠層121黏附於該第一基板10之上表面101,且利用該等第一導線13電性連接至該第一基板10之上表面101。然而,在其他實施例中,該第一晶粒12係利用覆晶接合方式電性連接至該第一基板10之上表面101。The first die 12 is adjacent to the upper surface 101 of the first substrate 10 and electrically connected to the upper surface 101 of the first substrate 10 . In this embodiment, the first die 12 is adhered to the upper surface 101 of the first substrate 10 by using a first adhesive layer 121, and is electrically connected to the first substrate 10 by using the first wires 13 . Upper surface 101. However, in other embodiments, the first die 12 is electrically connected to the upper surface 101 of the first substrate 10 by flip chip bonding.

該第一封膠14包覆該第一晶粒12、該等第一導線13及該第一基板10之上表面101。該中間膠層24係位於該第一封膠14之上表面,其中該中間膠層24之表面積實質上等於該第一封膠14之上表面的表面積。The first sealant 14 covers the first die 12 , the first wires 13 , and the upper surface 101 of the first substrate 10 . The intermediate adhesive layer 24 is located on the upper surface of the first sealant 14, wherein the surface area of the intermediate adhesive layer 24 is substantially equal to the surface area of the upper surface of the first sealant 14.

該第二基板16,例如一有機基板,具有一上表面161、一下表面162、至少一第二上銲墊163及至少一第二下銲墊164。該第二基板16之下表面162係利用該中間膠層24黏附於該第一封膠上14。該至少一第二上銲墊163係鄰接於該第二基板16之上表面161,該至少一第二下銲墊164係鄰接於該第二基板16之下表面162。The second substrate 16, such as an organic substrate, has an upper surface 161, a lower surface 162, at least a second upper bonding pad 163, and at least a second lower bonding pad 164. The lower surface 162 of the second substrate 16 is adhered to the first sealant 14 by the intermediate adhesive layer 24. The at least one second upper pad 163 is adjacent to the upper surface 161 of the second substrate 16 , and the at least one second lower pad 164 is adjacent to the lower surface 162 of the second substrate 16 .

該第二晶粒18鄰接於該第二基板16之上表面161,且電性連接至該第二基板16之上表面161。在本實施例中,該第二晶粒18係利用一第二膠層181黏附於該第二基板16之上表面161,且利用該等第二導線19電性連接至該第二基板16之上表面161。然而,在其他實施例中,該第二晶粒18係利用覆晶接合方式電性連接至該第二基板16之上表面161。The second die 18 is adjacent to the upper surface 161 of the second substrate 16 and electrically connected to the upper surface 161 of the second substrate 16 . In this embodiment, the second die 18 is adhered to the upper surface 161 of the second substrate 16 by a second adhesive layer 181, and is electrically connected to the second substrate 16 by using the second wires 19 . Upper surface 161. However, in other embodiments, the second die 18 is electrically connected to the upper surface 161 of the second substrate 16 by flip chip bonding.

該第二封膠20包覆該第二晶粒18、該等第二導線19及該第二基板16之上表面161。The second encapsulant 20 covers the second die 18 , the second wires 19 , and the upper surface 161 of the second substrate 16 .

該至少一導通柱22貫穿該第一基板10、該第一封膠14及該第二基板16。在本實施例中,該至少一導通柱22之材質係為銅,其貫穿該至少一第一上銲墊103、該至少一第一下銲墊104、該至少一第二上銲墊163及該至少一第二下銲墊164,且該至少一導通柱22之二端係分別顯露於該第一基板10之下表面102及該第二基板16之上表面161。The at least one via post 22 extends through the first substrate 10 , the first encapsulant 14 , and the second substrate 16 . In this embodiment, the at least one conductive pillar 22 is made of copper, and penetrates the at least one first upper bonding pad 103, the at least one first lower bonding pad 104, the at least one second upper bonding pad 163, and The at least one second lower pad 164 and the two ends of the at least one conductive post 22 are respectively exposed on the lower surface 102 of the first substrate 10 and the upper surface 161 of the second substrate 16.

該等銲球26係位該第一基板10之該至少一第一下銲墊104上,且電性連接至該至少一導通柱22。The solder balls 26 are fastened to the at least one first lower pad 104 of the first substrate 10 and electrically connected to the at least one conductive pillar 22 .

在本實施例中,該至少一導通柱22係用以作為垂直方向電性連接之元件。由於該至少一導通柱22之外徑比習知銲球小,因此可縮小彼此間距且增加密度。In this embodiment, the at least one via post 22 is used as an element that is electrically connected in a vertical direction. Since the outer diameter of the at least one via post 22 is smaller than a conventional solder ball, the pitch between the two can be reduced and the density can be increased.

參考圖2至圖10,顯示本發明半導體封裝結構之製造方法之一實施例之示意圖。參考圖2,提供一第一基板10。該第一基板10,例如一有機基板,具有一上表面101、一下表面102、至少一第一上銲墊103及至少一第一下銲墊104。該至少一第一上銲墊103係鄰接於該第一基板10之上表面101,該至少一第一下銲墊104係鄰接於該第一基板10之下表面102。Referring to Figures 2 through 10, there is shown a schematic diagram of one embodiment of a method of fabricating a semiconductor package structure of the present invention. Referring to FIG. 2, a first substrate 10 is provided. The first substrate 10, such as an organic substrate, has an upper surface 101, a lower surface 102, at least a first upper bonding pad 103, and at least one first lower bonding pad 104. The at least one first upper pad 103 is adjacent to the upper surface 101 of the first substrate 10 , and the at least one first lower pad 104 is adjacent to the lower surface 102 of the first substrate 10 .

參考圖3,附著一第一晶粒12於該第一基板10之上表面101,且電性連接該第一晶粒12至該第一基板10之上表面101。在本實施例中,該第一晶粒12係利用一第一膠層121黏附於該第一基板10之上表面101,且利用複數條第一導線13電性連接至該第一基板10之上表面101。然而,在其他實施例中,該第一晶粒12係利用覆晶接合方式電性連接至該第一基板10之上表面101。Referring to FIG. 3, a first die 12 is attached to the upper surface 101 of the first substrate 10, and the first die 12 is electrically connected to the upper surface 101 of the first substrate 10. In this embodiment, the first die 12 is adhered to the upper surface 101 of the first substrate 10 by using a first adhesive layer 121, and is electrically connected to the first substrate 10 by using a plurality of first wires 13. Upper surface 101. However, in other embodiments, the first die 12 is electrically connected to the upper surface 101 of the first substrate 10 by flip chip bonding.

參考圖4,形成一第一封膠14以包覆該第一晶粒12、該等第一導線13及該第一基板10之上表面101。Referring to FIG. 4, a first encapsulant 14 is formed to cover the first die 12, the first wires 13, and the upper surface 101 of the first substrate 10.

參考圖5,提供一第二基板16。該第二基板16,例如一有機基板,具有一上表面161、一下表面162、至少一第二上銲墊163及至少一第二下銲墊164。該第二基板16之下表面162係利用一中間膠層24黏附於該第一封膠上14,其中該中間膠層24之表面積實質上等於該第一封膠14之上表面的表面積。該至少一第二上銲墊163係鄰接於該第二基板16之上表面161,該至少一第二下銲墊164係鄰接於該第二基板16之下表面162。Referring to Figure 5, a second substrate 16 is provided. The second substrate 16, such as an organic substrate, has an upper surface 161, a lower surface 162, at least a second upper bonding pad 163, and at least a second lower bonding pad 164. The lower surface 162 of the second substrate 16 is adhered to the first sealant 14 by an intermediate adhesive layer 24, wherein the surface area of the intermediate adhesive layer 24 is substantially equal to the surface area of the upper surface of the first sealant 14. The at least one second upper pad 163 is adjacent to the upper surface 161 of the second substrate 16 , and the at least one second lower pad 164 is adjacent to the lower surface 162 of the second substrate 16 .

參考圖6,以機械鑽孔或雷射鑽孔方式形成至少一貫穿孔28以貫穿該第一基板10、該第一封膠14、該中間膠層24及該第二基板16。在本實施例中,該至少一貫穿孔28係貫穿該至少一第一上銲墊103、該至少一第一下銲墊104、該至少一第二上銲墊163及該至少一第二下銲墊164。Referring to FIG. 6, at least a uniform perforation 28 is formed through mechanical drilling or laser drilling to penetrate the first substrate 10, the first encapsulant 14, the intermediate subbing layer 24, and the second substrate 16. In this embodiment, the at least one of the first through pads 28 extends through the at least one first upper pad 103, the at least one first lower pad 104, the at least one second upper pad 163, and the at least one second lower bonding Pad 164.

參考圖7,以電鍍方式形成一導電金屬(例如銅)於該至少一貫穿孔28內以形成至少一導通柱22。該至少一導通柱22係貫穿該至少一第一上銲墊103、該第一基板10、該至少一第一下銲墊104、該第一封膠14、該中間膠層24、該至少一第二上銲墊163、該第二基板16及該至少一第二下銲墊164,且該至少一導通柱22之二端係分別顯露於該第一基板10之下表面102及該第二基板16之上表面161。Referring to FIG. 7, a conductive metal (e.g., copper) is formed in the at least consistent via 28 by electroplating to form at least one via post 22. The at least one conductive pillar 22 extends through the at least one first upper bonding pad 103, the first substrate 10, the at least one first lower bonding pad 104, the first sealing compound 14, the intermediate adhesive layer 24, and the at least one a second upper pad 163, the second substrate 16 and the at least one second lower pad 164, and the two ends of the at least one via post 22 are respectively exposed on the lower surface 102 of the first substrate 10 and the second The upper surface 161 of the substrate 16.

參考圖8,附著一第二晶粒18於該第二基板16之上表面161,且電性連接該第二晶粒18至該第二基板16之上表面161。在本實施例中,該第二晶粒18係利用一第二膠層181黏附於該第二基板16之上表面161,且利用複數條第二導線19電性連接至該第二基板16之上表面161。然而,在其他實施例中,該第二晶粒18係利用覆晶接合方式電性連接至該第二基板16之上表面161。Referring to FIG. 8 , a second die 18 is attached to the upper surface 161 of the second substrate 16 , and the second die 18 is electrically connected to the upper surface 161 of the second substrate 16 . In this embodiment, the second die 18 is adhered to the upper surface 161 of the second substrate 16 by a second adhesive layer 181, and is electrically connected to the second substrate 16 by using a plurality of second wires 19. Upper surface 161. However, in other embodiments, the second die 18 is electrically connected to the upper surface 161 of the second substrate 16 by flip chip bonding.

參考圖9,形成一第二封膠20以包覆該第二晶粒18、該等第二導線19及該第二基板16之上表面161。接著,形成複數個等銲球26於該第一基板10之該至少一第一下銲墊104上,以電性連接至該至少一導通柱22。Referring to FIG. 9, a second encapsulant 20 is formed to cover the second die 18, the second wires 19, and the upper surface 161 of the second substrate 16. Then, a plurality of solder balls 26 are formed on the at least one first lower pad 104 of the first substrate 10 to be electrically connected to the at least one via post 22 .

參考圖10,進行切割步驟,以切割該第一基板10、該第一封膠14、該中間膠層24、該第二基板16及該第二封膠20,而製得複數個如圖1所示之該半導體封裝結構1。Referring to FIG. 10, a cutting step is performed to cut the first substrate 10, the first sealant 14, the intermediate adhesive layer 24, the second substrate 16, and the second sealant 20, thereby producing a plurality of FIG. The semiconductor package structure 1 is shown.

惟上述實施例僅為說明本發明之原理及其功效,而非用以限制本發明。因此,習於此技術之人士對上述實施例進行修改及變化仍不脫本發明之精神。本發明之權利範圍應如後述之申請專利範圍所列。However, the above embodiments are merely illustrative of the principles and effects of the invention and are not intended to limit the invention. Therefore, those skilled in the art can make modifications and changes to the above embodiments without departing from the spirit of the invention. The scope of the invention should be as set forth in the appended claims.

1...本發明半導體封裝結構之一實施例1. . . One embodiment of the semiconductor package structure of the present invention

10...第一基板10. . . First substrate

12...第一晶粒12. . . First grain

13...第一導線13. . . First wire

14...第一封膠14. . . First glue

16...第二基板16. . . Second substrate

18...第二晶粒18. . . Second grain

19...第二導線19. . . Second wire

20...第二封膠20. . . Second sealant

22...導通柱twenty two. . . Conduction column

24...中間膠層twenty four. . . Intermediate glue layer

26...銲球26. . . Solder ball

28...貫穿孔28. . . Through hole

101...第一基板之上表面101. . . Upper surface of the first substrate

102...第一基板之下表面102. . . Lower surface of the first substrate

103...第一上銲墊103. . . First upper pad

104...第一下銲墊104. . . First lower pad

121...第一膠層121. . . First glue layer

161...第二基板之上表面161. . . Upper surface of the second substrate

162...第二基板之下表面162. . . Lower surface of the second substrate

163...第二上銲墊163. . . Second upper pad

164...第二下銲墊164. . . Second lower pad

181...第二膠層181. . . Second glue layer

圖1顯示本發明半導體封裝結構之一實施例之示意圖;及1 shows a schematic diagram of an embodiment of a semiconductor package structure of the present invention; and

圖2至圖10顯示本發明半導體封裝結構之製造方法之一實施例之示意圖。2 to 10 are schematic views showing an embodiment of a method of fabricating a semiconductor package structure of the present invention.

1...本發明半導體封裝結構之一實施例1. . . One embodiment of the semiconductor package structure of the present invention

10...第一基板10. . . First substrate

12...第一晶粒12. . . First grain

13...第一導線13. . . First wire

14...第一封膠14. . . First glue

16...第二基板16. . . Second substrate

18...第二晶粒18. . . Second grain

19...第二導線19. . . Second wire

20...第二封膠20. . . Second sealant

22...導通柱twenty two. . . Conduction column

24...中間膠層twenty four. . . Intermediate glue layer

26...銲球26. . . Solder ball

101...第一基板之上表面101. . . Upper surface of the first substrate

102...第一基板之下表面102. . . Lower surface of the first substrate

103...第一上銲墊103. . . First upper pad

104...第一下銲墊104. . . First lower pad

121...第一膠層121. . . First glue layer

161...第二基板之上表面161. . . Upper surface of the second substrate

162...第二基板之下表面162. . . Lower surface of the second substrate

163...第二上銲墊163. . . Second upper pad

164...第二下銲墊164. . . Second lower pad

181...第二膠層181. . . Second glue layer

Claims (15)

一種半導體封裝結構,包括:一第一基板,具有一上表面及一下表面;一第一晶粒,鄰接於該第一基板之上表面,且電性連接至該第一基板之上表面;一第一封膠,包覆該第一晶粒及該第一基板之上表面;一第二基板,具有一上表面及一下表面,該第二基板之下表面係黏附於該第一封膠上;及至少一導通柱,貫穿該第一基板、該第一封膠及該第二基板。A semiconductor package structure comprising: a first substrate having an upper surface and a lower surface; a first die adjacent to the upper surface of the first substrate and electrically connected to the upper surface of the first substrate; a first adhesive covering the first die and the upper surface of the first substrate; a second substrate having an upper surface and a lower surface, the lower surface of the second substrate being adhered to the first sealant And at least one via post extending through the first substrate, the first encapsulant, and the second substrate. 如請求項1之半導體封裝結構,其中該第一基板更具有至少一第一上銲墊及至少一第一下銲墊,該至少一第一上銲墊係鄰接於該第一基板之上表面,該至少一第一下銲墊係鄰接於該第一基板之下表面,且該至少一導通柱係貫穿該至少一第一上銲墊及該至少一第一下銲墊。The semiconductor package structure of claim 1, wherein the first substrate further comprises at least a first upper bonding pad and at least one first lower bonding pad, the at least one first upper bonding pad being adjacent to the upper surface of the first substrate The at least one first lower pad is adjacent to the lower surface of the first substrate, and the at least one conductive pillar extends through the at least one first upper pad and the at least one first lower pad. 如請求項1之半導體封裝結構,更包括一中間膠層,該第二基板之下表面係利用該中間膠層黏附於該第一封膠上,且該至少一導通柱貫穿該中間膠層。The semiconductor package structure of claim 1, further comprising an intermediate adhesive layer, wherein the lower surface of the second substrate is adhered to the first sealant by the intermediate adhesive layer, and the at least one conductive pillar penetrates the intermediate adhesive layer. 如請求項1之半導體封裝結構,其中該第二基板更具有至少一第二上銲墊及至少一第二下銲墊,該至少一第二上銲墊係鄰接於該第二基板之上表面,該至少一第二下銲墊係鄰接於該第二基板之下表面,且該至少一導通柱係貫穿該至少一第二上銲墊及該至少一第二下銲墊。The semiconductor package structure of claim 1, wherein the second substrate further comprises at least one second upper pad and at least one second lower pad, the at least one second upper pad being adjacent to the upper surface of the second substrate The at least one second lower pad is adjacent to the lower surface of the second substrate, and the at least one conductive pillar extends through the at least one second upper pad and the at least one second lower pad. 如請求項1之半導體封裝結構,其中該至少一導通柱之二端係分別顯露於該第一基板之下表面及該第二基板之上表面。The semiconductor package structure of claim 1, wherein the two ends of the at least one via post are respectively exposed on the lower surface of the first substrate and the upper surface of the second substrate. 如請求項1之半導體封裝結構,更包括一第二晶粒,鄰接於該第二基板之上表面,且電性連接至該第二基板之上表面。The semiconductor package structure of claim 1, further comprising a second die adjacent to the upper surface of the second substrate and electrically connected to the upper surface of the second substrate. 如請求項6之半導體封裝結構,更包括一第二封膠,其包覆該第二晶粒及該第二基板之上表面。The semiconductor package structure of claim 6, further comprising a second encapsulant covering the second die and the upper surface of the second substrate. 一種半導體封裝結構之製造方法,包括以下步驟:(a) 提供一第一基板,該第一基板具有一上表面及一下表面;(b) 附著一第一晶粒於該第一基板之上表面,且電性連接該第一晶粒至該第一基板之上表面;(c) 形成一第一封膠以包覆該第一晶粒及該第一基板之上表面;(d) 提供一第二基板,該第二基板具有一上表面及一下表面,且黏附該第二基板之下表面於該第一封膠上;(e) 形成至少一貫穿孔以貫穿該第一基板、該第一封膠及該第二基板;及(f) 形成一導電金屬於該至少一貫穿孔內以形成至少一導通柱。A method of fabricating a semiconductor package structure, comprising the steps of: (a) providing a first substrate having an upper surface and a lower surface; and (b) attaching a first die to the upper surface of the first substrate And electrically connecting the first die to the upper surface of the first substrate; (c) forming a first sealant to cover the first die and the upper surface of the first substrate; (d) providing a a second substrate having an upper surface and a lower surface, and adhering the lower surface of the second substrate to the first seal; (e) forming at least a uniform through hole to penetrate the first substrate, the first a sealant and the second substrate; and (f) forming a conductive metal in the at least one of the perforations to form at least one via post. 如請求項8之製造方法,其中該步驟(a)中,該第一基板更具有至少一第一上銲墊及至少一第一下銲墊,該至少一第一上銲墊係鄰接於該第一基板之上表面,該至少一第一下銲墊係鄰接於該第一基板之下表面,且該步驟(e)中,該至少一貫穿孔係貫穿該至少一第一上銲墊及該至少一第一下銲墊。The manufacturing method of claim 8, wherein the first substrate further has at least one first upper bonding pad and at least one first lower bonding pad, wherein the at least one first upper bonding pad is adjacent to the An upper surface of the first substrate, the at least one first lower pad is adjacent to the lower surface of the first substrate, and in the step (e), the at least one continuous through hole penetrates the at least one first upper pad and the At least one first lower pad. 如請求項8之製造方法,其中該步驟(d)中,該第二基板之下表面係利用一中間膠層黏附於該第一封膠上;該步驟(e)中,該至少一貫穿孔貫穿該中間膠層;且該步驟(f)中,該至少一導通柱貫穿該中間膠層。The manufacturing method of claim 8, wherein in the step (d), the lower surface of the second substrate is adhered to the first sealant by an intermediate glue layer; in the step (e), the at least one of the perforations is continuously penetrated. The intermediate adhesive layer; and in the step (f), the at least one conductive pillar penetrates the intermediate adhesive layer. 如請求項8之製造方法,其中該步驟(d)中,該第二基板更具有至少一第二上銲墊及至少一第二下銲墊,該至少一第二上銲墊係鄰接於該第二基板之上表面,該至少一第二下銲墊係鄰接於該第二基板之下表面,且該步驟(e)中,該至少一貫穿孔係貫穿該至少一第二上銲墊及該至少一第二下銲墊。The manufacturing method of claim 8, wherein in the step (d), the second substrate further has at least one second upper pad and at least one second lower pad, the at least one second upper pad being adjacent to the An upper surface of the second substrate, the at least one second lower pad is adjacent to the lower surface of the second substrate, and in the step (e), the at least one continuous through hole penetrates the at least one second upper pad and the At least one second lower pad. 如請求項8之製造方法,其中該步驟(f)中,該至少一導通柱之二端係分別顯露於該第一基板之下表面及該第二基板之上表面。The manufacturing method of claim 8, wherein in the step (f), the two ends of the at least one conducting post are respectively exposed on the lower surface of the first substrate and the upper surface of the second substrate. 如請求項8之製造方法,更包括一附著一第二晶粒於該第二基板之上表面,且電性連接該第二晶粒至該第二基板之上表面之步驟。The manufacturing method of claim 8, further comprising the step of attaching a second die to the upper surface of the second substrate and electrically connecting the second die to the upper surface of the second substrate. 如請求項13之製造方法,更包括一形成一第二封膠以包覆該第二晶粒及該第二基板之上表面之步驟。The manufacturing method of claim 13, further comprising the step of forming a second encapsulant to cover the second die and the upper surface of the second substrate. 如請求項14之製造方法,更包括一切割該第一基板、該第一封膠、該第二基板及該第二封膠之步驟。The manufacturing method of claim 14, further comprising the step of cutting the first substrate, the first encapsulant, the second substrate, and the second encapsulant.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200416787A (en) * 2002-10-08 2004-09-01 Chippac Inc Semiconductor stacked multi-package module having inverted second package
TW200933869A (en) * 2008-01-30 2009-08-01 Advanced Semiconductor Eng Package process for embedded semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200416787A (en) * 2002-10-08 2004-09-01 Chippac Inc Semiconductor stacked multi-package module having inverted second package
TW200933869A (en) * 2008-01-30 2009-08-01 Advanced Semiconductor Eng Package process for embedded semiconductor device

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