TWI440181B - High voltage metal oxide semiconductor device and method for making same - Google Patents

Description

High-voltage metal oxide semiconductor device and manufacturing method

The present invention relates to a high voltage metal oxide semiconductor device, and more particularly to an N-type high voltage metal oxide semiconductor device which defines a P-type doping region range to enhance a breakdown voltage of a device, or reduces the conduction resistance of the device. (ON resistance) P-type high voltage metal oxide semiconductor device. The invention also relates to a method of fabricating a high voltage metal oxide semiconductor device.

The breakdown protection voltage between the source and the drain of the MOS device depends on the PN junction between the source and the drain. For example, the occurrence of avalanche breakdown is due to the increase in the electric field in the depletion region of the PN junction, thus limiting the voltage that can be applied by the source and the drain. If the crash occurs at the PN junction between the source and the drain, the current between the source and the drain will rise rapidly, causing damage to the PN junction and malfunction of the MOS device.

1 shows the structure of a prior art N-type high voltage metal oxide semiconductor device, including: a semiconductor substrate 11, a P-type well region 12a, an N-type drift region 14a, an N-type source 15a, and an N-type drain 18a. The N-type lightly doped region 16a, the threshold voltage-adjusted P-type doped region 19a, and the gate structure 17. Among them, the N-type lightly doped region 16a and the N-type drift region 14a both have the effect of strengthening the collapse protection voltage of the N-type high voltage metal oxide semiconductor device. Both of them are PN junctions between the source 15a or the drain 15b of the heavily doped region and the P-type well region 12a, and are doped with a lighter N-type impurity to increase the width of the PN junction depletion region to enhance the N-type high voltage metal oxide semiconductor device breakdown protection voltage.

As the size of the component shrinks and the voltage that the high voltage component is required to withstand increases, the prior art described above also encounters a bottleneck that cannot be broken. Because the prior art described above enhances the crash protection voltage, it sacrifices another important component operating parameter, the on-resistance.

Conversely, P-type high-voltage MOS devices have a bottleneck that reduces on-resistance.

In view of the above, the present invention is directed to the deficiencies of the prior art described above, and provides an enhancement of the N-type high voltage metal oxide semiconductor device breakdown protection voltage without sacrificing on-resistance, and can reduce the on-resistance of the P-type high-voltage metal oxide semiconductor device without A high voltage metal oxide semiconductor device that sacrifices a breakdown protection voltage and a method of fabricating the same.

SUMMARY OF THE INVENTION One object of the present invention is to provide an N-type high voltage metal oxide semiconductor device capable of enhancing a device breakdown protection voltage without sacrificing on-resistance.

SUMMARY OF THE INVENTION One object of the present invention is to provide a P-type high voltage metal oxide semiconductor device capable of reducing on-resistance without sacrificing component breakdown protection voltage.

Another object of the present invention is to provide a method of fabricating a high voltage metal oxide semiconductor device.

In order to achieve the above object, in one aspect, the present invention provides a high voltage metal oxide semiconductor device comprising: a substrate; a gate structure on the surface of the substrate; and a P-type well region inside the substrate From the top view, the P-type well region constitutes an element region on a horizontal plane; a first N-type drift region located inside the P-type well region; and an N-type source electrode located inside the P-type well region; An N-type drain inside the first N-type drift region, separated from the gate structure by the first N-type drift region; and at a boundary between the P-type well region and the first N-type drift region Only one of the first P-type doped regions is covered, and the first P-type doped region is implanted with P-type impurities by an ion implantation technique to enhance the breakdown voltage of the high-voltage MOS device.

In one embodiment, from the cross-sectional view, one end of the first P-type doped region extends at most to the midpoint of the N-type drain, and the other end extends at least to a portion below the gate structure.

The high-voltage metal oxide semiconductor device may be a symmetric element or an asymmetric element. When it is an asymmetric element, an N-type lightly doped region partially overlapping the N-type source portion and partially under the gate is preferably disposed. When it is a symmetrical element, a second N-type drift region located inside the P-type well region is preferably disposed to separate the N-type source from the gate structure; and the P-type well region and the first The junction of the two N-type drift regions covers only one of the second P-type doped regions of the partial device region.

In another aspect, the present invention also provides a high voltage metal oxide semiconductor device comprising: a substrate; a gate structure on the surface of the substrate; and an N-type well region inside the substrate, viewed from the top surface The N-type well region constitutes an element region on a horizontal surface; a first P-type drift region located inside the N-type well region; and a P-type source region inside the N-type well region; and the first P-type a P-type drain inside the drift region, separated from the gate structure by the first P-type drift region; and at a boundary between the P-type drain and the first P-type drift region and covering only some components A first P-type doped region of the first P-type doped region is implanted with a P-type impurity by an ion implantation technique to reduce the on-resistance of the high-voltage MOS device.

In one embodiment, from the cross-sectional view, one end of the first P-type doped region extends at most to the junction of the N-type well region and the first P-type drift region.

The high-voltage MOS device may be a symmetrical element or an asymmetrical element. When it is an asymmetrical element, a P-type lightly doped region partially overlapping the P-type source and partially under the gate is preferably provided. When it is a symmetrical element, a second P-type drift region located inside the N-type well region is preferably disposed to separate the P-type source from the gate structure; and the N-type well region and the first a second P-type doped region at a junction of the second P-type drift region and covering only one of the component regions, wherein one end of the second P-type doped region extends at most to the N-type well region The junction of the second P-type drift region.

In still another aspect, the present invention provides a method of fabricating a high voltage metal oxide semiconductor device, comprising the steps of: providing a substrate; forming a first conductive well region inside the substrate, viewed from the top surface a conductive well region forms an element region on a horizontal surface; a second conductivity type drift region is formed inside the first conductivity type well region; a gate structure is formed on the surface of the substrate; and the first conductivity type is formed Forming a second conductive type source inside the well region; forming a second conductive type drain inside the first drift region, which is separated from the gate structure by the drift region; and implanting by ion implantation technology The P-type impurity forms a P-type doped region not covering the entire element region under the surface of the substrate to enhance the breakdown voltage of the semiconductor element or reduce the on-resistance of the semiconductor element while adjusting the threshold voltage.

In the above method of fabricating a high voltage metal oxide semiconductor device, the first conductivity type may be a P type, the second conductivity type may be an N type; or the first conductivity type may be an N type, and the second conductivity type may be a P type. The parameter of the ion implantation technique for forming the P-type doping region is preferably: an acceleration voltage range of 10,000 electron volts to 200,000 electron volts; the implanted ions are ions containing boron or indium; the implantation dose is per Square centimeters 1E12 to 1E14 ions.

The purpose, technical content, features and effects achieved by the present invention will be more readily understood by the detailed description of the embodiments.

The drawings in the present invention are schematic and are mainly intended to represent the process steps and the relationship between the layers, and the shapes, thicknesses, and widths are not drawn to scale.

Referring to the cross-sectional flowchart of FIGS. 2A-2F, a first embodiment of the present invention is shown. This embodiment shows the structure and fabrication method of an N-type high voltage metal oxide semiconductor device. As shown in FIG. 2A, a substrate 11 is first provided, and then a P-type well region 12a is defined in the substrate 11 by lithography and ion implantation technology. From the top surface, the P-type well region is formed on a horizontal surface. An element area 100. Next, as shown in FIG. 2B, an isolation region 13 is formed in the substrate 11, and the isolation region 13 may be formed by a region oxidation (LOCOS) or shallow trench isolation (STI) process technology. Next, as shown in FIG. 2C, the N-type first drift region 14a is defined in the P-type well region 12a by lithography and ion implantation techniques.

Next, as shown in FIG. 2D, a first P-type doped region 19b is formed by a lithography technique and an ion implantation technique at a boundary between the P-type well region 12a and the N-type first drift region 14a. A P-type doping region 19b is formed by implanting a P-type impurity by an ion implantation technique; the first P-type doping region 19b can improve the breakdown protection voltage of the N-type high-voltage MOS device without sacrificing On resistance. Moreover, the step of forming the first P-type doping region 19b can be integrated with the VT implant step of adjusting the threshold voltage, that is, using the threshold voltage adjustment step required by the original component, without adding a mask and In the case of the process step, the effect of the present invention can be achieved only by the layout of the moving mask. In detail, the threshold voltage adjustment step in the prior art exposes the entire component and comprehensively implants the component region, and the present invention opens only the junction of the P-type well region 12a and the N-type first drift region 14a. For the range, please refer to the 2F figure. One end extends at most to the midpoint of the drain region 18a, and the other end extends at least to a portion below the gate structure 17, as defined by the broken line portion in FIG. 2F. The process parameters of the ion implantation step can also adopt the parameters of the threshold voltage adjustment, and the preferred parameters are set as: the acceleration voltage range is 10,000 electron volts to 200,000 electron volts; the implanted ions are boron or indium. Ion; implant dose is 1E12 to 1E14 ions per square centimeter. This step utilizes variations in lateral concentration in the channel to increase the collapse protection voltage of the N-type high voltage MOS device without sacrificing on-resistance, eliminating the need to add masks, process steps, or other process parameters (eg, Not changing the thermal budget of the integrated process, etc., is one of the features of the present invention over the prior art.

Next, as shown in FIG. 2E, a portion of the gate structure 17 is formed on the substrate 11, and includes a gate dielectric layer 17a and a gate conductive layer 17b. 2F shows a N-type lightly doped region 16a formed by self-alignment technology, lithography, etching, and ion implantation techniques, and a gate spacer layer 17c formed on the gate sidewall (this is part of the gate structure 17). And forming an N-type source 15a and an N-type drain 18a. The N-type lightly doped region 16a partially overlaps the N-type source 15a and is partially located below the gate structure 17.

Fig. 3 shows a second embodiment of the present invention, which is a P-type high voltage metal oxide semiconductor device. The manufacturing process of the P-type high-voltage metal oxide semiconductor device is mainly different from the first embodiment of the present invention, except that the present embodiment includes the N-type well region 12b, the first P-type drift region 14b, and the P-type source 15b, P. The type drain electrode 18b and the P type lightly doped region 16b are different from the N-type high voltage metal oxide semiconductor device described above, mainly in that the first P type doping region 19b is defined by the P type drain electrode 18b and the P type. At the junction of a drift region 14b, one end of the range extends at most to the junction of the N-type well region 12b and the first P-type drift region 14b, and the other end is not limited (as indicated by a broken line and an arrow), and its ion implantation The process parameters of the step can also adopt the parameters of the threshold voltage adjustment, and the preferred parameters are set as: the acceleration voltage range is 10,000 electron volts to 200,000 electron volts; the implanted ions are ions containing boron or indium; the implantation dose It is 1E12 to 1E14 ions per square centimeter. This step takes advantage of changes in the lateral concentration in the channel to reduce the on-resistance without sacrificing the breakdown voltage. Similarly, the step of forming the first P-type doping region 19b can be integrated with the ion implantation step of adjusting the threshold voltage, and only the layout of the photomask is changed to achieve the effect of the present invention.

The foregoing two embodiments are asymmetrical elements, and FIG. 4 shows another embodiment of the present invention. This embodiment is an N-type high-voltage metal oxide semiconductor symmetrical element. The main difference from the first embodiment lies in the P-type well region. The N-type lightly doped region 16a is omitted in 12a, but a second N-type drift region 14c is added to separate the gate structure 17 from the N-type source 15a, so that the source 15a can also apply a high voltage. In addition, the second P-type doping region 19c at the intersection of the P-type well region 12a and the second N-type drift region 14c is also added in the embodiment. The second P-type doping region 19c is implanted by ion implantation technology. P-type impurity to strengthen the breakdown voltage of the high-voltage N-type metal oxide semiconductor symmetrical element. Similarly, one end of the second P-type doping region 19c extends at most to the midpoint of the source region 15a, and the other end extends at least to a portion below the gate structure 17.

Fig. 5 is a view showing still another embodiment of the present invention. This embodiment is a P-type high-voltage metal oxide semiconductor symmetrical element. The main difference from the second embodiment is that the P-type light doping is omitted in the N-type well region 12b. a region 16b, but a P-type second drift region 14d is added to separate the gate structure 17 from the P-type source 15b. In addition, the present embodiment also increases the boundary between the P-type source 15b and the second P-type drift region 14d. The second P-type doping region 19c is implanted with a P-type impurity by an ion implantation technique to further reduce the on-resistance value of the high-voltage P-type metal oxide semiconductor symmetrical element.

The present invention has been described with reference to the preferred embodiments thereof, and the present invention is not intended to limit the scope of the present invention. In the same spirit of the invention, various equivalent changes can be conceived by those skilled in the art. For example, other process steps or structures, such as deep well areas, may be added without affecting the main characteristics of the components; for example, lithography is not limited to reticle technology, and may include electron beam lithography. Further, in Figs. 1-5, the drain electrodes 18a/18b are aligned with the gate spacer layer 17c, which implies that the drain electrodes 18a/18b in the respective embodiments are self-aligned, with the gate structure as a mask. It is formed by ion implantation, but the present invention is not limited thereto, and it is also possible to form the drains 18a/18b without self-alignment, for example, Figures 6 and 7. Therefore, the scope of the invention should be construed as covering the above and all other equivalents.

11. . . Substrate

12a. . . P type well area

12b. . . N type well area

13. . . quarantine area

14a. . . First N-type drift region

14b. . . First P-type drift region

14c. . . Second N-type drift region

14d. . . Second P-type drift region

15a. . . N-type source

15b. . . P-type source

16a‧‧‧N type lightly doped area

16b‧‧‧P type lightly doped area

17‧‧‧ gate structure

17a‧‧‧ Gate dielectric layer

17b‧‧‧ gate conductive layer

17c‧‧‧gate spacer

18a‧‧‧N type bungee

18b‧‧‧P type bungee

19a‧‧‧Critical voltage adjustment P-doped region

19b‧‧‧First P-doped region

19c‧‧‧Second P-doped region

Fig. 1 is a cross-sectional view showing a prior art N-type high voltage metal oxide semiconductor device.

2A-2F are cross-sectional views showing the first embodiment of the present invention.

Figures 3-5 show cross-sectional views of three other embodiments of the invention.

Figures 6-7 illustrate cross-sectional views of other embodiments of the present invention in which the drains 18a/18b are formed without self-alignment.

11. . . Substrate

12a. . . P type well area

13. . . quarantine area

14a. . . First N-type drift region

15a. . . N-type source

16a. . . N type lightly doped area

17a. . . Gate dielectric layer

17b. . . Gate conductive layer

17c. . . Gate spacer

18a. . . N-type bungee

19b. . . First P-doped region

100. . . Component area

Claims (14)

A high voltage metal oxide semiconductor device comprising: a substrate; a gate structure on a surface of the substrate; a P-type well region located inside the substrate, wherein the P-type well region is formed on a horizontal surface from a top surface An element region; a first N-type drift region located inside the P-type well region; an N-type source electrode located inside the P-type well region; and an N-type drain electrode located inside the first N-type drift region, Separating from the gate structure by the first N-type drift region; and at a boundary between the P-type well region and the first N-type drift region and covering only one of the first P-type doped regions of the partial device region, The first P-type doped region is implanted with a P-type impurity by an ion implantation technique, wherein the first P-type doped region is not a complete channel between the N-type source and the N-type drain. Thereby, a change in the lateral concentration of the channel between the N-type source and the N-type drain is caused to enhance the collapse protection voltage of the high-voltage MOS device. The high voltage metal oxide semiconductor device according to claim 1, wherein, from a cross-sectional view, one end of the first P-type doping region extends at most to a midpoint of the N-type drain, and the other end extends at least to A part of the gate structure below. The high voltage metal oxide semiconductor device of claim 2, wherein the high voltage metal oxide semiconductor device is an asymmetrical component, further comprising: a portion overlapping the N-type source portion and partially located at the gate An N-type lightly doped region below the structure. The high voltage metal oxide semiconductor device of claim 2, wherein the high voltage metal oxide semiconductor device is a symmetrical component, Included: a second N-type drift region located inside the P-type well region to separate the N-type source from the gate structure; and at a boundary between the P-type well region and the second N-type drift region Covering only one of the second P-type doped regions of a portion of the device region, wherein from the cross-sectional view, one end of the second P-type doped region extends at most to the midpoint of the N-type source, and the other end extends at least to A part below the gate structure. A high voltage metal oxide semiconductor device comprising: a substrate; a gate structure on a surface of the substrate; and an N-type well region inside the substrate, wherein the N-type well region is formed on a horizontal surface from a top surface An element region; a first P-type drift region located inside the N-type well region; a P-type source region located inside the N-type well region; and a P-type drain electrode located inside the first P-type drift region, Separating from the gate structure by the first P-type drift region; and at a boundary between the P-type drain and the first P-type drift region and covering only one of the first P-type doped regions of the component region, The first P-type doped region is implanted with a P-type impurity by an ion implantation technique, wherein the first P-type doped region is not a complete channel between the N-type source and the N-type drain. Thereby, a lateral concentration change occurs in the channel between the P-type source and the P-type drain to reduce the on-resistance of the high-voltage MOS device. The high voltage metal oxide semiconductor device according to claim 5, wherein, from a cross-sectional view, one end of the first P-type doping region extends at most to the N-type well region and the first P-type drift region Junction. High-voltage metal oxide semiconductor element as described in claim 6 The high voltage metal oxide semiconductor device is an asymmetric component, and further comprising: a P-type lightly doped region partially overlapping the P-type source portion and partially under the gate. The high voltage metal oxide semiconductor device of claim 6, wherein the high voltage metal oxide semiconductor device is a symmetrical component, further comprising: a second P-type drift region located inside the N-well region, Separating the P-type source from the gate structure; and at a junction of the N-well region and the second P-type drift region and covering only one of the component regions and a second P-doped region, wherein As shown in the cross-sectional view, one end of the second P-type doping region extends at most to the junction of the N-type well region and the second P-type drift region. A method for fabricating a high voltage metal oxide semiconductor device, comprising the steps of: providing a substrate; forming a first conductive type well region inside the substrate, wherein the first conductive type well region forms a component on a horizontal surface from a top surface a second conductivity type drift region is formed inside the first conductivity type well region; a gate structure is formed on the surface of the substrate; and a second conductivity type source is formed inside the first conductivity type well region Forming a second conductive type drain inside the first drift region, which is separated from the gate structure by the drift region; and implanting P-type impurities by ion implantation technology to form under the surface of the substrate A P-doped region of the entire device region is not covered, wherein the P-doped region is not located between the second conductive type source and the second conductive type drain Channel, thereby causing a lateral concentration change of the channel between the second conductive type source and the second conductive type drain to enhance the breakdown voltage of the semiconductor element or lower the semiconductor while adjusting the threshold voltage The conduction resistance of the component. The method for fabricating a high voltage metal oxide semiconductor device according to claim 9, wherein the first conductivity type is a P type, the second conductivity type is an N type, and the P type doping region is located at the first conductive layer. The well region and the drift region meet and only cover a part of the component region for increasing the breakdown voltage of the high voltage metal oxide semiconductor device. The method for fabricating a high voltage metal oxide semiconductor device according to claim 10, wherein, from the cross-sectional view, one end of the P-type doping region extends at most to a midpoint of the second conductivity type source, and the other end Extending at least a portion below the gate structure. The method of fabricating a high voltage metal oxide semiconductor device according to claim 9, wherein the first conductivity type is N type, the second conductivity type is P type, and the P type doping region is located at the second conductive layer. The type drain has a junction with the drift region and covers only a part of the device region for reducing the on-resistance of the high voltage metal oxide semiconductor device. The method for fabricating a high voltage metal oxide semiconductor device according to claim 12, wherein, from the cross-sectional view, one end of the P-type doped region extends at most to the first conductive type well region and the second conductive type The junction of the drift zone. The method for fabricating a high voltage metal oxide semiconductor device according to claim 9, wherein the parameter of the ion implantation technique for forming the P-type doping region ranges from an acceleration voltage range of 10,000 electron volts to 200,000 electrons. Volt; implanted ions are ions containing boron or indium; The implant dose is 1E12 to 1E14 ions per square centimeter.