TWI332239B - Semiconductor wafer and method for forming the same - Google Patents

Description

1332239 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor wafer, and more particularly to a semiconductor wafer 0 capable of effectively preventing wafer delamination caused by wafer dicing [Prior Art] · With the continuous improvement of semiconductor process technology and the miniaturization of integrated circuit chips, many unnecessary parasitic capacitances (parasite capacit0r) are often formed between metal interconnects. Since the electrons must be filled with parasitic capacitance before they can be transmitted, the delay of signal transmission is delayed, causing so-called RC time delay effects, and the resistance_capacitor time delay effect is further improved. The bottleneck of the speed and performance of components. In order to improve the speed and performance of integrated circuit components, most of the current methods are to reduce the resistance of the resistor-capacitor time delay by reducing the line resistance of the metal interconnect or reducing the dielectric constant of the dielectric layer. Under this demand, copper metal with lower resistivity gradually replaces aluminum metal with higher resistivity as the material of metal inner connecting line, and dielectric material with low dielectric constant gradually replaces fluorinated silicate glass. , FSG), phosphosiiate giaiss (PSG) or undoped silicate glass (tJSG) and other oxidized oxide dielectric materials. ♦ . However, the interface between the low dielectric constant material and the copper metal is particularly prone to the phenomenon of peeling or peeling. Because after the semiconductor wafer_integrated circuit is completed, the package will be cut by the grinding or cutting tool to cut the semiconductor wafer for subsequent packaging process, but the mechanical knife cutting will inevitably be in the semiconductor crystal. Mechanical internal stress in the circle (intermal = ress) 'cause cracks, especially when cutting, scribe line contains low dielectric constant material and steel metal, it is particularly easy to cause low-media The layer of electrically constant material is spalled or interbedded. Because the cutting step is performed = the grinding wheel or the cutting blade will apply cutting stress downward from the wafer surface, and the field knife. When the 丨 stress is pressed to a large area of the metal structure, the entire metal structure will squash the surrounding low dielectric constant material layer, and the extrusion result may cause the low 'I electrical constant material layer peeling phenomenon, which is due to the copper metal material. The hard nature is harder to cut than other layers of the wafer, while the low-k material layer is soft or porous and has poor adhesion to other material layers. These potential problems often jeopardize the reliability of the final product when the flaking phenomenon extends from the scribe line to the drive circuitry in each die area. Although the above disadvantages may exist, it is difficult to avoid a large area of metal material such as a metal pad in the dicing street. Because in the semiconductor manufacturing process, in order to maintain the stability of product quality, it is necessary to continue online testing for the semiconductor wafers produced. Most of the current industry adopts wafer acceptance testing (WAT), which is based on two The PeriPhery area provides a plurality of test key structures, and 1332239 is used to monitor the defects of the parent semiconductor process. That is, while performing various processes, the same steps are used to simultaneously synthesize a test component in the channel of the wafer to simulate the same process, and then the test device is measured by a test device such as a metal probe. Each parameter is used as an indicator to check whether the process is normal, and thus effectively control product quality. The above test key structure comprises a metal pad and is located in the scribe line. The other metal pad structure located in the scribe line has an electrical test key, a feature dimension, a measuring component, and a component alignment mark. (alignment mark) and other process test structures or identification marks (logo). * * · - Please refer to Figure 1 and Figure 2. Fig. 1 is a top plan view of a conventional semiconductor wafer, and Fig. 2 is a side view showing a semiconductor wafer shown in Fig. 1 after cutting. As shown in FIG. 1, the semiconductor wafer 10 includes a plurality of die-arranged die regions 12, a plurality of first scribe line regions 14 that are substantially parallel to each other, and a plurality of substantially parallel to each other. The second scribe line region 16 wherein the first scribe lane region 14 and the second scribe lane region 16 are substantially directly distributed to each other to separate the respective grain regions 12. Further, on the surface of the current semiconductor wafer 10, a passivation layer or an indium metal dielectric layer (IMD layer) composed of a low dielectric constant material layer 18 is often contained. At least one metal test structure 20 is disposed in the first scribe line region 14 or the second scribe channel region 16. The metal test structure 20 can be any electrical measurement test structure, feature size, etc., and component alignment. Mark, 8 1332239 wafer reliability test pad and other process test structures. As described above, when the package process is completed after the integrated circuit on the semiconductor wafer 10 is completed, the grinding wheel or the cutter will follow the first * * ' cutting channel region 14 and the second cutting channel. The region 16 is diced to divide the semi-conductor wafer 10 into a plurality of individual die regions 12. In general, the widths of the first scribe line region 14 and the second scribe channel region 16 may be determined by factors such as the size of the spring conductor wafer, the cutting method, the type of the integrated circuit, and the like, and are about several tens of micrometers ( Micrometer) to between hundreds of microns. As shown in FIG. 2, after the semiconductor wafer 10 is diced, peeling or interlayer peeling is particularly likely to occur at the interface of the topmost layer of the low dielectric constant material 18 and the other material layers below, especially When the cutting stress is pressed to the metal structure of a large area in the scribe line region 14, the entire metal structure will squash the surrounding low dielectric constant material layer, thereby causing peeling of the low dielectric constant material layer and peeling of the dielectric layer. And this phenomenon is very easy to transfer along the direction perpendicular to the cutting path, so that the peeling range of the low dielectric constant material layer 18 may touch the metal interconnect layer in the grain region 12 and destroy the product in the grain. The body circuit operates. SUMMARY OF THE INVENTION Accordingly, it is a primary object of the present invention to provide a semiconductor wafer that solves the problem that conventional techniques cannot overcome, thereby preventing grain damage caused by semiconductor wafer cutting. According to the patent application scope of the present invention, the present invention provides a semiconductor wafer including a plurality of die regions, at least one first scribe region, and at least one second scribe region surrounding each die region. At least one first metal structure and at least one second metal structure are respectively disposed in the first and second scribe line regions, and the first metal structure has at least one first slit parallel to the yoke-cutting region or The opening, the second metal structure has at least one second slit or opening parallel to the second scribe line region. The invention further provides a method of making a metal structure according to the scope of the patent application. First, a semiconductor wafer is provided, the semiconductor wafer defining a scribe region and the scribe region having at least a first dielectric layer. Next, a first metal layer is formed in the first dielectric layer in the scribe line region, and the first metal layer has at least one slit parallel to the scribe line region. Thereafter, a second dielectric layer is formed in the scribe line region, and the second dielectric layer has a plurality of vias parallel to the scribe region to expose a portion of the first metal Floor. Finally, a second metal layer is formed on the surface of the second dielectric layer, and a plurality of via stripes are filled in the elongated via holes, and the second metal layer is electrically connected to the first metal layer by the via stripes. Since the slit structure or the plurality of arrayed open σ structures are formed in the metal structure of the semiconductor wafer of the present invention, the delamination of the mechanical 1332239 can be prevented from causing the material layer to peel off or the dielectric layer is peeled off, thereby protecting the crystal grains. Not damaged by peeling. Effective

V For a more detailed understanding of the features and technical aspects of the present invention, please refer to the following detailed description of the present invention and the accompanying drawings. The drawings are for illustrative purposes only and are not intended to be limiting of the invention. Μ Embodiments Please refer to FIGS. 3 to 7 , and FIGS. 3 to 6 are schematic views showing a method of forming a semiconductor wafer according to a preferred embodiment of the present invention, and FIG. 7 is a diagram of FIG. A schematic cross-sectional view of the semiconductor wafer 3 Q along the 7-7, tangent line. As shown in FIG. 3, the semiconductor wafer 30 of the present invention includes at least one low-power tenth dielectric layer 38a, a plurality of die regions 32, and a plurality of first substantially parallel to each other. The scribe line region 34 and a plurality of second scribe lane regions 36 that are substantially parallel to each other. Wherein, an integrated circuit is formed in each of the die regions 32, which may include a transistor (10) nSiSt〇r), a capacitor (four) acitr), a diode (di〇de), a push-diffusion region, and a memory. Various electronic components and wire circuits such as arrays or metal interconnects. The first dicing area 3' and the first dicing area % are substantially perpendicular to each other and constitute a mesh-shaped scribe line area for separating the respective grain area %. Then, as shown in FIG. 4, a metal process is performed for each grain region.

Claims (1)

1332239 Application 4 Scope 1. A semiconductor wafer comprising: a plurality of die regions, and a scribe line region around each of the die regions and at least a second scribe region; and wherein the first metal structure is disposed In the first-cutting region, the first structure has at least one first slit parallel to the first cutting lane region and the -metal-metal material completely surrounds the first slit; and at least one second metal structure, Provided in the second scribe line region, and the second metal structure has at least - a first slit parallel to the second butterfly region and a second metal material completely surrounding the second slit. 2. The semiconductor wafer of claim i, wherein the first metal structure and the second metal structure comprise a measuring component of an electrical test structure, a feature size, and the like, and a component alignment mark, a wafer Reliability test 塾 process test structure. 3. The semiconductor wafer according to claim ii, wherein an integral circuit is formed in each of the crystal domains. 4. The semiconductor wafer of claim 1, wherein the first scribe lane region and the second scribe lane region each comprise at least one low dielectric constant dielectric layer. < [S} 23 5 The semiconductor wafer of claim 4, wherein the first layer surface. I. The dielectric wafer of the low dielectric constant, such as the semiconductor wafer of claim 4, wherein the semiconductor NMOS protective layer covers the low dielectric constant dielectric layer and the first a metal structure and a surface of the second metal structure. 8. The semiconductor wafer of claim i, wherein the first, genus structure and the second metal structure comprise titanium, group, crane, sho, copper, nitride, nitride or the above A combination of alloys. 9. The semiconductor wafer of claim 1, wherein the first metal structure and the second metal structure have a plurality of third slits extending inwardly from a boundary of the metal structures. 10. The semiconductor wafer of claim 9, wherein the first metal structure and the second metal structure further have a plurality of fourth slits staggered with the third slits. 1332239 η—a metal structure disposed in a scribe line region, the metal structure having at least one slit parallel to the scribe line region and a metal material completely surrounding the slit. 12. The metal structure according to claim 5, wherein the metal structure comprises a measuring component having an electrical test structure, a feature size, and the like; and a component alignment mark, a wafer reliability test pad, and the like; . 13. The metal structure of claim 5, wherein the scribe region is disposed in a semiconductor wafer. J. The metal structure of claim 13, wherein the third layer further comprises at least two grain areas, and the scribe line area is disposed between the Uz temple grain areas. The structure, the structure of the metal, is as described in claim 15, and the structure is embedded in the dielectric layer of the low dielectric constant. The metal structure of claim 11, wherein the metal structure comprises titanium, tantalum, tungsten, aluminum, copper, titanium nitride, a zirconium button or a combination of the foregoing. 19. The metal structure of claim 11, wherein the metal structure has a plurality of boundary slits extending inwardly from a boundary of the metal structure. The metal structure of claim 19, wherein the metal structure further has a plurality of staggered slits which are staggered with the boundary slits. 21. A metal structure 'the metal structure is disposed in a scribe line region of a semiconductor wafer, and the metal structure comprises: a first-gold ride' and the first metal layer has at least a parallel-cut region a slit and a metal material completely surround the slit; a second metal layer disposed above the first metal layer; and a plurality of via strips parallel to the scribe line region disposed on the first metal layer The first metal layer and the second metal layer are electrically connected between the second metal layers. 22. The metal structure according to claim 21, wherein the first metal layer comprises an electrical test structure, a measuring element of the characteristic ruler, a component alignment mark, a wafer reliability test, and the like. Test structure. [S 26 = · For example, (4) 21 rhyme gold i 纟 (4), wherein the semiconductor: 曰 further comprises at least two grain regions, and the scribe region is disposed between the grain regions. 24. A dielectric layer having at least one low dielectric constant as described in claim 21 of the scope of the patent application. The n-cut is a metal structure as described in claim 24, wherein the metal, ', ° configuration is disposed on the surface of the low dielectric constant dielectric layer. 26. The metal structure of claim 24, and (4) the structure is embedded in the dielectric layer of the low dielectric constant. The metal structure according to the item, wherein the metal aluminum, copper 'titanium nitride, nitride button or the above 27. The structure of the twenty-first aspect of the invention includes a combination of titanium, a button, a tungsten, and an alloy. For example, the metal structure described in claim 21, wherein the first layer of the cough has a viewing boundary depending on the boundary of the first metal layer, and the inner structure of the tf paste is the gold structure of the 28th item (4). The first two-layer layer further has a plurality of staggered slits staggered with the boundary slits 27 1332239 31. The plurality of metal structures are picked up in the butterfly track region, and the metal structure has an array of openings and - The metal material completely surrounds the opening. The metal structure as described in claim 31, wherein the metal has a measuring component such as an electrical test structure, a feature size, and a process test structure such as a memory-receiving, wafer reliability test, and the like. 33. The metal bypass region as described in claim 31 of the patent application is disposed on a semiconductor wafer. For example, if the metal structure is as described in claim 33, the bulk wafer further includes at least - 曰, $, Λ, Λ, and the grain area between the die areas is set in the H application. The metal structure of the item 31 has a dielectric layer having at least one low dielectric constant. 36. The metal structure of claim 35, wherein the gold structure is disposed on a surface of the low dielectric constant dielectric layer. Λ 28 U32239 where the metal is as described in the metal structure described in claim 35 of the patent scope, , , , . The structure is embedded in the low dielectric constant dielectric layer. Further, the metal portion is the metal structure described in the metal structure of the crane, the shovel, the copper, or the "or the second range of the third item" as described in claim 31, wherein the metal has a plurality of boundary slits. The boundary of the metal structure extends inward. = The metal structure described in claim 39, wherein the metal has a plurality of staggered slits which are staggered with the boundary slits. 41. A method of fabricating a metal structure, comprising: providing a semiconductor wafer defining a dicing region and having at least a first dielectric layer; in the dicing region Forming a second dielectric layer, and the second dielectric layer has a plurality of county vias in the butterfly region for exposing a portion of the first metal layer; and the second dielectric layer Surface formation - second metal layer and a plurality of layers 29 丄: filled in the elongated via holes, and the second metal or the like is electrically connected to the first metal layer. The method of claim 41, wherein the first metal is a measurement element such as a butterfly, a feature size, and the like, and a process test structure such as a component, aa circular reliability test, and the like. 43. The circle of claim ", wherein the circle further comprises at least two days, ... wherein the semiconductor crystal grain region is between the heart and the region" and the edge cutting region is disposed in the layer The method of claim 41, wherein the first dielectric I electrical layer comprises a low dielectric constant material. The method of applying the method described in the 41st item, the (iv) equal interlayer layer - A method of electrically connecting the metal layer to the first metal layer, wherein the metal structure is combined, wherein the metal structure is combined with a turn, a copper, a titanium nitride, a nitrided surface. Or the method of the above-mentioned alloy interlayer strip, and the method of claim 41, wherein after forming the one metal layer, the first portion is formed on the exposed portion of the layer of the scribe line region 30 1332239 A protective layer and a protective layer - a metal layer. 48. The method of claim 41, wherein the first metal layer forms (four), the first metal layer has a plurality of boundaries The slit extends inward from the boundary of the first metal layer. H applies for full-time (4) 48 items The method, wherein in the step of forming the metal layer, the first metal layer further has a plurality of staggered slits arranged in a staggered manner with boundary slits such as 戎. : The metal structure according to claim 49," In forming a tantalum-like metal layer and a material-like layer (four) towel, each of the via strips has a zigzag shape, a wave shape or a square wave shape. 51. 1 disposed in a dicing zone - a metal structure comprising a plurality of boundary slits extending inwardly from a boundary of the metal structure; a plurality of interlaced slits staggered with the boundary slits; A metallic material completely surrounds the staggered slits. ϋ The metal structure described in claim 51, wherein the shoulder == contains the electrical test structure, the feature size, etc. (10) and the day (four) quasi-marker, wafer reliability test pad and other process test structures. 31 1332239 53. As claimed in claim 51, the region κ metal structure, wherein the dicing system 5 is again placed in a semiconductor wafer. 54. The 曰圄s a a I genus structure as set forth in claim 53 wherein the semi-conductive day further comprises at least two grain regions and between the grain regions. The W-drag domain is set forth in 鄕, a metal structure as described in the section, wherein the dicing k region has at least one dielectric layer of low dielectric constant. A metal structure as described in claim 55, wherein the structure is disposed on a surface of the low dielectric constant dielectric layer. Person 57. The metal and structure described in claim 55, wherein the gold structure is embedded in the low dielectric constant dielectric layer. The metal structure of claim 51, wherein the metal structure comprises a combination of titanium, group, crane, stellite, copper, gasified ruthenium, gasification group or upper alloy. Ten schema · 32