TWI312869B - Power level detector - Google Patents
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1312869 九、發明說明: 【發明所屬之技術領域】 本案係有關於一種電壓源準位偵測裝置(power detector)。 【先前技#Ϊ】 第1圖為一種傳統電壓源準位偵測裝置1〇〇,用以偵 • 测一晶片所使用的電壓源VDD之準位,其中包括一能隙參 考電壓產生器(Bandgap Voltage Generator) 102、一债測電壓 產生電路104、以及一比較器CMP。該能隙參考電壓產生 器102常見於一般積體電路晶片中,乃用來產生一能隙參 考電塵VBG供晶片參考。該能隙參考電壓vBG為固定值(通 常為1.25伏特)不受溫度影響、亦不隨電壓源vDD飄移。 該镇測電壓產生電路1〇4包括三個電晶體(Ml、M2、與M3) 以及兩個電阻(心與,乃用來在該能隙參考電壓¥阳產 _ 生後’分壓該電壓源VDD,產生一偵測電壓Vdet。如第1 圖所示’該能隙參考電壓VBG產生後,電晶體Mi導通、 電曰日體Μ?操作在飽和區(saturati〇11 region)、並且電晶體 Μ?導通且產生一電流流經上述電阻心與r2。由於電晶體 Mg的面積遠大於電晶體m2,因此電晶體m3操作在線性區 (linear region),以電阻型態操作,其電阻值為。電阻 Ron、Rl、與R2將該電壓源VDD分壓後輸出該偵測電壓 Vdet。該比較器CMP比較該偵測電壓Vdet以及該能隙參考 電壓VBG後’輪出一旗標Flag標示比較結果,以供判斷該1312869 IX. Description of the invention: [Technical field to which the invention pertains] This case relates to a voltage source level detector. [Previous Technique #Ϊ] Figure 1 is a conventional voltage source level detecting device for detecting the level of the voltage source VDD used by a chip, including a bandgap reference voltage generator ( A Bandgap Voltage Generator 102, a debt measurement voltage generating circuit 104, and a comparator CMP. The bandgap reference voltage generator 102 is commonly found in general integrated circuit chips and is used to generate a bandgap reference dust VBG for wafer reference. The bandgap reference voltage vBG is a fixed value (typically 1.25 volts) that is unaffected by temperature and does not drift with the voltage source vDD. The town voltage measuring circuit 1〇4 includes three transistors (M1, M2, and M3) and two resistors (the core is used to divide the voltage source after the bandgap reference voltage is generated). VDD, a detection voltage Vdet is generated. As shown in Fig. 1, after the bandgap reference voltage VBG is generated, the transistor Mi is turned on, the cell is turned on, the cell is operated in the saturation region (saturati〇11 region), and the transistor is导? is turned on and generates a current flowing through the resistor core and r2. Since the area of the transistor Mg is much larger than the transistor m2, the transistor m3 operates in a linear region and operates in a resistive mode, and the resistance value thereof is The resistors Ron, R1, and R2 divide the voltage source VDD and output the detection voltage Vdet. The comparator CMP compares the detection voltage Vdet with the bandgap reference voltage VBG and then 'rounds a flag Flag to compare Result, for judgment
Client’s Docket No.:VTT〇6-〇147 TT's Docket No:0608-A41〇〇5.TW/Final /Glorious_Tien £ 1312869 電壓源vDD目前的準位。 然而,該電壓源VDD遭重置(reset)時,上述傳統電壓 源準位偵測裝置100常發生錯誤。因為該能隙參考電壓產 生器102在電壓源VDD被重置後,並不是立即產生該能隙 參考電壓VBG ;必須在該電壓源VDD回復至一準位以後, 才會產生該能隙參考電壓VBG。舉例說明之,假設VDD為 5V,該電壓源VDD被重置後,該能隙參考電壓產生器102 一開始並不會輸出該能隙參考電壓VBG,必須等到該電壓 • 源VDD回升至一準位(例如2.5V)後才會產生該能隙參考電 麈VBG。如此一來,該電壓源VDD遭重置後尚未回升至該 準位的這一段時間,該比較器CMP的兩個輸入信號(該能 隙參考電壓VBG以及該偵測電壓Vdet)都還沒有準備好,因 此該比較器CMP的運作會發生錯誤。 【發明内容】 本發明提供一種新穎的電壓源準位偵測裝置,可避免 • 上述傳統電壓源準位偵測裝置100在電壓源重置時所發生 的問題。 本發明所提出的電壓源準位偵測裝置包括一電壓源分 壓器、一能隙參考電壓產生器、一比較電路、一控制電路、 以及一強制電路。該電壓源分壓器乃用來分壓一電壓源, 以產生一偵測電壓。在重置(reset)該電壓源後,該能隙參 考電壓產生器會在該電壓源回復至一準位後,產生一能隙 參考電壓。該比較電路乃用來比較該偵測電壓以及該能隙 參考電壓,以判斷該電壓源的準位。在該能隙參考電壓尚Client’s Docket No.: VTT〇6-〇147 TT's Docket No:0608-A41〇〇5.TW/Final /Glorious_Tien £1312869 Voltage source vDD current level. However, when the voltage source VDD is reset, the conventional voltage source level detecting device 100 often causes an error. Because the bandgap reference voltage generator 102 does not immediately generate the bandgap reference voltage VBG after the voltage source VDD is reset; the bandgap reference voltage must be generated after the voltage source VDD returns to a level. VBG. For example, assuming that VDD is 5V, after the voltage source VDD is reset, the bandgap reference voltage generator 102 does not initially output the bandgap reference voltage VBG, and must wait until the voltage source VDD rises to a level. The bandgap reference cell VBG is generated after the bit (for example, 2.5V). As a result, after the voltage source VDD is reset and has not recovered to the level, the two input signals of the comparator CMP (the gap reference voltage VBG and the detection voltage Vdet) are not yet prepared. Ok, so the operation of the comparator CMP will be wrong. SUMMARY OF THE INVENTION The present invention provides a novel voltage source level detecting device that avoids the problems that occur when the conventional voltage source level detecting device 100 is reset at a voltage source. The voltage source level detecting device proposed by the present invention comprises a voltage source voltage divider, a bandgap reference voltage generator, a comparison circuit, a control circuit, and a forcing circuit. The voltage source voltage divider is used to divide a voltage source to generate a detection voltage. After resetting the voltage source, the bandgap reference voltage generator generates a bandgap reference voltage after the voltage source returns to a level. The comparison circuit is configured to compare the detection voltage and the gap reference voltage to determine the level of the voltage source. The energy gap reference voltage is still
Client’s Docket No.:VIT06-0147 TT's Docket No:0608-A41005-TW/Final /Glorious Tien ( 1312869 未產生時’該控制電路會去能(disable)該 ^隙參考電壓產生後,該控制電路由去能該比較電路切換 ^(enable)該比較電路。該強制電路_接於該比較電路 控制電路控制。在該比較電路為去能狀態 、二強制電路會強制該比較電路之輪出端電壓為一定 值,以避免該比較電路輪出錯誤信息。 :讓本發明:上述和其他目的、特徵、和優點能更明 '、、、員易t重,下文特舉出較佳實施例,並配合所附圖式作詳細 說明。 【實施方式】 第2圖為本發明之電壓源準位偵測裳置的示意圖,其 中’-電壓源準位偵測裝置2 〇 〇包括一電壓源分壓器搬、 -此隙參考電壓產生器204、-比較電路2Q6、一控制電路 208、以及-強制電路21〇。該電壓源分壓器搬將一電壓 源VDD分壓後,輸出一偵測電壓Vdet。該偵測電壓^為 • 該電壓源Vdd之分壓。該能隙參考電壓產生器2〇4乃用來 產生具有固疋值的一能隙參考電壓VBG。當該電壓源vDD 發生重置(reset)時’該能隙參考電壓產生器204必須等待 該電壓源VDD回升至一準位後,才會產生該能隙參考電壓 Vbg。該比較電路206乃用來比較該偵測電壓vdet以及該 能隙參考電壓vBG ’以判斷該電壓源vDD的準位。該比較 電路206的致能/去能(enable/disable)由該控制電路208控 制。在該能隙參考電壓Vbg尚未產生時,該控制電路208 的動作為去能(disable)該比較電路206。在該能隙參考電壓Client's Docket No.:VIT06-0147 TT's Docket No:0608-A41005-TW/Final /Glorious Tien ( 1312869 When not generated 'The control circuit will disable the gap reference voltage generated, the control circuit is gone The comparison circuit can enable the comparison circuit to be controlled by the comparison circuit control circuit, wherein the comparison circuit is in a de-energized state, and the second forcing circuit forces the voltage of the output terminal of the comparison circuit to be constant. The value is to prevent the comparison circuit from rotating the error message. The present invention and the other objects, features, and advantages will be more apparent, and the members will be more important, and the preferred embodiment will be described below. 2 is a schematic diagram of a voltage source level detection skirt of the present invention, wherein the '-voltage source level detecting device 2 〇〇 includes a voltage source voltage divider The gap reference voltage generator 204, the comparison circuit 2Q6, a control circuit 208, and the - forcing circuit 21. The voltage source divider divides a voltage source VDD and outputs a detection voltage Vdet. The detection voltage ^ is • The voltage source Vdd is divided. The bandgap reference voltage generator 2〇4 is used to generate a bandgap reference voltage VBG having a solid value. When the voltage source vDD is reset, the bandgap The reference voltage generator 204 must wait for the voltage source VDD to rise back to a level before generating the bandgap reference voltage Vbg. The comparison circuit 206 is configured to compare the detected voltage vdet with the bandgap reference voltage vBG ' The level of the voltage source vDD is determined. The enable/disable of the comparison circuit 206 is controlled by the control circuit 208. When the bandgap reference voltage Vbg has not been generated, the action of the control circuit 208 is The comparison circuit 206 can be disabled. The gap reference voltage
Client’s Docket N〇.:VIT06-0147 TT's Docket No:0608-A41005-TW/Final /Glorious_Tien 1312869 ί二:該t制電路208的動作由去能該比較電路206 切換成致4滿)該比較電路2G6。該強制電路2 於該比較電路206之輸出蛾 ^ 亦由該控制電路208控制。 該比較電路206為去能肤能 狀態時,該強制電路210會強制琴 比較電路206之輸出端電壓A f J ^ u 馬—疋值’以避免該比較電路 206輸出錯誤的比較結果。 第3圖為本發明之電壓、、β^ A 楚/原準位偵測裝置的一實施例。 電壓源準位偵測裝置300所接jClient's Docket N〇.:VIT06-0147 TT's Docket No:0608-A41005-TW/Final /Glorious_Tien 1312869 ί 2: The operation of the t-circuit 208 is switched from the comparison circuit 206 to 4 full) The comparison circuit 2G6 . The output moth of the forcing circuit 2 at the comparison circuit 206 is also controlled by the control circuit 208. When the comparison circuit 206 is in the deenergized state, the forcing circuit 210 forces the output voltage A f J ^ u 疋 疋 value of the comparator circuit 206 to prevent the comparison circuit 206 from outputting an erroneous comparison result. Fig. 3 is a view showing an embodiment of the voltage, β^A/original level detecting device of the present invention. The voltage source level detecting device 300 is connected to j
吓私用的比較電路302包括一屮 較器CMP以及一第一開關q% 闻關。該第一開關SWi| 該比較器CMP之電源端與兮φ厭、β λ, 牧么 ⑽電壓源VDD之間,由控制 路304所產生的一第一控制作 ^ 列唬cs!控制。该第一開關sw 在邊控制電路304去能該比較電路观時為不導通,並且 在該控制電路304致能該比較電路3〇2時為導通。 如第3圖所示’電壓源準位摘測裝置3〇〇以一第二開 關SW2實現第2圖之強制電路21〇。該第二開關SW2由二 制電路304所產生的一第二控制信號CSz控制。由於此實 施例將該能隙參考電壓vBG輸入該比較器CMP之反相: 入端’並且將該偵測電壓Vdet輸入該比較器CMP之非反相 輸入知,故该弟一開關SW2必須在該比較電路3 〇2為去倉h 狀態時將其輸出端耦接至一接地端(一定電壓端),以確保 該比較電路302不會在該比較電路302為去能狀態時誤判 該偵測電壓Vdet高於該能隙參考電壓VBC〇 弟4圖為控制電路3 04的一實施例,其中包括—電容 C、一放電電路402、一第一反相器Inv〗、以及一第二反相The comparison circuit 302 for intimidation includes a comparator CMP and a first switch q%. The first switch SWi| is connected between the power supply terminal of the comparator CMP and the voltage source VDD of the comparator CMP, and a first control generated by the control circuit 304 is controlled by the control circuit 304. The first switch sw is non-conducting when the side control circuit 304 is de-energized, and is turned on when the control circuit 304 enables the comparison circuit 3〇2. As shown in Fig. 3, the voltage source level pick-up device 3A implements the forcing circuit 21A of Fig. 2 with a second switch SW2. The second switch SW2 is controlled by a second control signal CSz generated by the binary circuit 304. Since the energy gap reference voltage vBG is input to the inversion of the comparator CMP: the input terminal 'and the detection voltage Vdet is input to the non-inverting input of the comparator CMP, the younger switch SW2 must be The comparison circuit 3 〇2 couples its output terminal to a ground terminal (a certain voltage terminal) when the state is in the h state, to ensure that the comparison circuit 302 does not misjudge the detection when the comparison circuit 302 is in the de-energized state. The voltage Vdet is higher than the bandgap reference voltage VBC. FIG. 4 is an embodiment of the control circuit 304, including a capacitor C, a discharge circuit 402, a first inverter Inv, and a second inversion.
Client's Docket N〇.:VIT06-0147 TT's Docket No:〇608-A41005-TW/Final /Glorious Tien 1312869 器Inv2。如圖所示,該電容C的第一端點以及第二端點分 別耦接該電壓源VDD以及該放電電路402。該放電電路402 在該能隙參考電壓VBG產生後啟動,用以產生一放電電流 I放電該電容C。該第一反相器Invi之輸入端耦接該電容C 之第二端點,以輸出上述第一控制信號CS!控制上述第一 開關SWi。該第一控制信號CSi為高準位時,該第一開關 SWi導通,該比較電路302被致能;反之,該第一開關SW! 不導通,該比較電路302被去能。該第二反相器Inv2之輸 • 入端耦接該第一反相器Ιην!之輸出端,用以反相該第一控 制信號CS!以產生上述第二控制信號CS2控制該第二開關 SW2。該第二控制信號CS2為高準位時,該第二開關SW2 導通,反之則不導通。 在本發明中,上述放電電流I可隨著該電容C之第二 端點的電壓準位下降而減少。第5圖為控制電路304的另 一實施例,所採用的放電電路502為一電流鏡,其中包括 一第一電晶體Μι以及一第二電晶體M2。該第一電晶體 籲 Μ!之閘極與汲極耦接在一起。該第一與第二電晶體(M!以 及M2)之閘極電壓皆由該能隙參考電壓VBG控制,並且具 有同樣的閘源極壓差。該第二電晶體M2之汲極端耦接該 電容C之第二端點。 參閱第5圖,該電壓源VDD發生重置但尚未回升至一 準位時’該能隙參考電壓Vbg尚未產生’故該放電電路5 02 尚未開啟,該放電電流I為零。此時,該電容C的第二端 點之電位會隨著其第一端點變化,即隨著該電壓源乂耶上Client's Docket N〇.:VIT06-0147 TT's Docket No:〇608-A41005-TW/Final /Glorious Tien 1312869 Inv2. As shown, the first end and the second end of the capacitor C are coupled to the voltage source VDD and the discharge circuit 402, respectively. The discharge circuit 402 is activated after the bandgap reference voltage VBG is generated to generate a discharge current I to discharge the capacitor C. The input end of the first inverter Invi is coupled to the second end of the capacitor C to output the first control signal CS! to control the first switch SWi. When the first control signal CSi is at a high level, the first switch SWi is turned on, and the comparison circuit 302 is enabled; otherwise, the first switch SW! is not turned on, and the comparison circuit 302 is disabled. The input end of the second inverter Inv2 is coupled to the output end of the first inverter Ιην! for inverting the first control signal CS! to generate the second control signal CS2 to control the second switch SW2. When the second control signal CS2 is at a high level, the second switch SW2 is turned on, and vice versa. In the present invention, the above-described discharge current I may decrease as the voltage level of the second terminal of the capacitor C decreases. Fig. 5 is a diagram showing another embodiment of the control circuit 304. The discharge circuit 502 is a current mirror including a first transistor 以及1 and a second transistor M2. The gate of the first transistor is coupled to the drain. The gate voltages of the first and second transistors (M! and M2) are controlled by the bandgap reference voltage VBG and have the same gate-source voltage difference. The second terminal of the second transistor M2 is coupled to the second terminal of the capacitor C. Referring to Fig. 5, when the voltage source VDD is reset but has not yet risen to a level, the bandgap reference voltage Vbg has not yet been generated. Therefore, the discharge circuit 502 has not been turned on, and the discharge current I is zero. At this time, the potential of the second terminal of the capacitor C changes with its first end point, that is, with the voltage source 乂
Client's Docket N〇.:VIT06-0147 TT's Docket No:0608-A41005-TW/Final /Glorious_Tien 1312869 升。因此,該電容c之第二端點的電位經該第一與第二反 相器Ιην:與Inv2處理後,會輸出低準位的第一控制信號 CSi以及高準位的第二控制信號CS2。參閱第3圖,藉由上 述第一與第二控制信號(CSi以及CS2),該控制電路304去 能該比較電路302並且強制該比較電路302所產生的旗標 Flag為接地,以避免該比較電路302輸出錯誤的判斷結果。 參閱第5圖,該電壓源VDD回升至該準位後,該能隙 參考電壓VBG產生,該放電裝置502開啟並且產生一放電 • 電流I放電該電容C。第6圖為該放電電流I與該第二電晶 體M2之没源極麼差VDS_M2之關係圖。如第6圖所示,該 放電電流I剛產生時,該電容C之第二端點的電位(即該第 二電晶體M2之汲·源極壓差VdS_M2)為V〇 ’該放電電流1=1〇。 該電容C之第二端點的電位(VDS_M2)在放電過程中逐漸下 降,如第6圖所示,該放電電流I亦隨之逐漸降低,最後 兩者皆降至零。上述放電程序會令該電容C之第二端點電 位經該第一與第二反相器11^1與Inv2處理後,輸出高準位 • 的第一控制信號CSi、及低準位的第二控制信號cs2。因 此,該比較電路302被致能,並且該比較電路302之輸出 端不再被強制接地。該比較電路302得以開始正常運作。 第7圖為控制電路304的另一實施例,所採用的放電 電路702為一 N型金氧半電晶體Mn,其閘極耦接該能隙 參考電壓VBG、其汲極耦接該電容C之第二端點、並且其 源極接地。由上述實施例可知,本發明之放電電路在該電 容C之第二端點的電位降至零後即停止提供該放電電流Client's Docket N〇.:VIT06-0147 TT's Docket No:0608-A41005-TW/Final /Glorious_Tien 1312869 L. Therefore, the potential of the second end of the capacitor c is processed by the first and second inverters Ιη: and Inv2, and the first control signal CSi of low level and the second control signal CS2 of high level are output. . Referring to FIG. 3, by the first and second control signals (CSi and CS2), the control circuit 304 can disable the comparison circuit 302 and force the flag Flag generated by the comparison circuit 302 to be grounded to avoid the comparison. The circuit 302 outputs an erroneous judgment result. Referring to Figure 5, after the voltage source VDD rises back to the level, the bandgap reference voltage VBG is generated, the discharge device 502 is turned on and a discharge is generated. • The current I discharges the capacitor C. Fig. 6 is a graph showing the relationship between the discharge current I and the source-to-source difference VDS_M2 of the second transistor M2. As shown in FIG. 6, when the discharge current I is generated, the potential of the second end of the capacitor C (ie, the 压·source voltage difference VdS_M2 of the second transistor M2) is V〇' the discharge current 1 =1. The potential of the second terminal of the capacitor C (VDS_M2) gradually decreases during the discharge process. As shown in Fig. 6, the discharge current I also gradually decreases, and finally both fall to zero. The discharge process causes the second terminal potential of the capacitor C to be processed by the first and second inverters 11^1 and Inv2, and outputs a first control signal CSi of the high level and a low level. The second control signal cs2. Therefore, the comparison circuit 302 is enabled and the output of the comparison circuit 302 is no longer forced to ground. The comparison circuit 302 is ready for normal operation. FIG. 7 is another embodiment of the control circuit 304. The discharge circuit 702 is an N-type MOS transistor Mn, the gate is coupled to the bandgap reference voltage VBG, and the drain is coupled to the capacitor C. The second end point and its source is grounded. It can be seen from the above embodiment that the discharge circuit of the present invention stops supplying the discharge current after the potential of the second terminal of the capacitor C falls to zero.
Client’s Docket N〇.:VIT06-0147 TT's Docket No:0608-A41005-TW/Final /Glorious_Tien 、I312869 i,故本發明不需要耗費大量能量。 第8圖為本發明的另一實施例,其中所採用的電壓源 分壓器802乃由串聯於該電壓源vDD與一接地端之間的複 數個電阻(本實施例為心與R2)所組成。本發明採用單純電 阻分壓,使用者可輕易掌握該偵測電壓Vdet與該電壓源vdd 的關係。反觀第丨圖之傳統電壓源準位偵測裝置1〇〇,該 偵測電壓產生電路〗04之電晶體Ms之電阻值Rcm會隨著製 φ %變化’不易掌握,容易造成使用者困擾。 第9圖為本發明的另一實施例,其中更包括一切換裝 置902 ’耦接於該電壓源分壓器904與該比較電路906之 間’用以在該比較電路906為去能狀態時’將該偵測電壓 Vdet切換成一接地端以輸入該比較電路906。如圖所示,該 切換裝置902包括一第三開關SW3、以及一第四開關SW4。 該第三開關SW3在該比較電路906被致能(該第一控制信號 〇81為高準位)時導通,用以耦接該偵測電壓乂加至該比較 電路9〇6。該第四開關SW*在該比較電路906被去能(該第 二控制信號CS2為高準位)時導通,用以耦接該接地端至該 比較電路906。 第10圖為本發明的另一種實施例,其中包括多組比較 電路(1002與1004)。本實施例之電壓源分壓器1〇〇6會輸 出兩組偵測電壓(Vdetl與Vdet2),分別輸入比較電路1 〇〇2與 1004。該等比較電路1〇〇2與1〇〇4之致能與否、以及其輸 出端所耦接之強制電路之動作與否皆和本發明其他實施例 相同。藉由本實施例,使用者可由旗標Flagl與Flag2判斷Client's Docket N〇.: VIT06-0147 TT's Docket No: 0608-A41005-TW/Final /Glorious_Tien, I312869 i, so the present invention does not require a lot of energy. FIG. 8 is another embodiment of the present invention, wherein the voltage source voltage divider 802 is used by a plurality of resistors (heart and R2 in this embodiment) connected in series between the voltage source vDD and a ground terminal. composition. The invention adopts a simple resistor partial voltage, and the user can easily grasp the relationship between the detection voltage Vdet and the voltage source vdd. In contrast, in the conventional voltage source level detecting device of the first drawing, the resistance value Rcm of the transistor Ms of the detecting voltage generating circuit -04 is difficult to grasp with the change of φ%, which is likely to cause user trouble. FIG. 9 is another embodiment of the present invention, further including a switching device 902 ′ coupled between the voltage source voltage divider 904 and the comparison circuit 906 for when the comparison circuit 906 is in an unenergized state. 'Switching the detection voltage Vdet to a ground terminal for inputting the comparison circuit 906. As shown, the switching device 902 includes a third switch SW3 and a fourth switch SW4. The third switch SW3 is turned on when the comparison circuit 906 is enabled (the first control signal 〇81 is at a high level) for coupling the detection voltage to the comparison circuit 9〇6. The fourth switch SW* is turned on when the comparison circuit 906 is deenergized (the second control signal CS2 is at a high level) for coupling the ground terminal to the comparison circuit 906. Figure 10 is another embodiment of the present invention including multiple sets of comparison circuits (1002 and 1004). The voltage source voltage divider 1〇〇6 of this embodiment outputs two sets of detection voltages (Vdetl and Vdet2), which are input to the comparison circuits 1 〇〇 2 and 1004, respectively. The operation of the comparison circuits 1〇〇2 and 1〇〇4 and the compulsory circuit to which the output terminals are coupled are the same as other embodiments of the present invention. With this embodiment, the user can judge by the flags Flagl and Flag2
Client’s Docket N〇.:VIT06-0147 TT^ Docket No:0608-A41005-TW/Final /Glorious Tien 11 1312869 該電壓源vDD目前位於某一電壓範圍内。 本發明雖以較佳實施例揭露如上,然其並非用以限定 本發明的範圍,任何熟習此項技藝者,在不脫離本發明之 精神和範圍内,當可做些許的更動與潤飾,因此本發明之 保護範圍當視後附之申請專利範圍所界定者為準。Client’s Docket N〇.:VIT06-0147 TT^ Docket No:0608-A41005-TW/Final /Glorious Tien 11 1312869 This voltage source vDD is currently within a certain voltage range. The present invention has been described above with reference to the preferred embodiments thereof, and is not intended to limit the scope of the present invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.
Client’s Docket N〇.:VIT06-0147 TT's Docket No:0608-A41005-TW/Final /Glorious_Tien 1312869 【圖式簡單說明】 第1圖為一種傳統電壓源準位偵測裝置; 第2圖為本發明之電壓源準位偵測裝置的示意圖; 第3圖為本發明之電壓源準位偵測裝置的一實施例; 第4圖為控制電路304的一實施例; 第5圖為控制電路304的另一實施例; 第6圖為該放電電流I與第5圖之第二電晶體M2的汲 源極壓差Vds_M2之關係圖, 第7圖為控制電路304的另一實施例; 第8圖為本發明之電壓源準位偵測裝置的一實施例; 第9圖為本發明之電壓源準位偵測裝置的一實施例; 以及 第10圖為本發明之電壓源準位偵測裝置的一實施例。 【主要元件符號說明】 100〜傳統電壓源準位偵測裝置; 102〜能隙參考電壓產生器;104〜偵測電壓產生電路; 200〜電壓源準位偵測裝置;202〜電壓源分壓器; 204〜能隙參考電壓產生器;206〜比較電路; 208〜控制電路; 210〜強制電路; 300〜電壓源準位偵測裝置;302〜比較電路; 304〜控制電路; 402〜放電電路; 502〜放電電路; 702〜放電電路; 802〜電壓源分壓器; 902〜切換電路;Client's Docket N〇.:VIT06-0147 TT's Docket No:0608-A41005-TW/Final /Glorious_Tien 1312869 [Simple diagram of the diagram] Figure 1 is a conventional voltage source level detection device; Figure 2 is the invention FIG. 3 is a schematic diagram of a voltage source level detecting device according to the present invention; FIG. 4 is an embodiment of the control circuit 304; FIG. 5 is another embodiment of the control circuit 304. An embodiment; FIG. 6 is a diagram showing the relationship between the discharge current I and the threshold voltage difference Vds_M2 of the second transistor M2 of FIG. 5, and FIG. 7 is another embodiment of the control circuit 304; An embodiment of the voltage source level detecting device of the present invention; FIG. 9 is an embodiment of the voltage source level detecting device of the present invention; and FIG. 10 is a voltage source level detecting device of the present invention. An embodiment. [Main component symbol description] 100~ conventional voltage source level detecting device; 102~gap reference voltage generator; 104~ detecting voltage generating circuit; 200~voltage source level detecting device; 202~voltage source voltage dividing 204~bandgap reference voltage generator; 206~comparing circuit; 208~control circuit; 210~force circuit; 300~voltage source level detecting device; 302~comparing circuit; 304~control circuit; 402~discharging circuit 502~ discharge circuit; 702~ discharge circuit; 802~voltage source voltage divider; 902~ switching circuit;
Client's Docket N〇.:VIT06-0147 TT5s Docket No:0608-A41005-TW/Final/Glorious Tien 13 1312869 904〜電壓源分壓器; 1002、1004〜比較電路; C〜電容; CSi〜第一控制信號; 906〜比較電路; 1006〜電壓源分壓器; CMP〜比較器; CS2〜第二控制信號;Client's Docket N〇.:VIT06-0147 TT5s Docket No:0608-A41005-TW/Final/Glorious Tien 13 1312869 904~voltage source divider; 1002,1004~comparison circuit; C~capacitor; CSi~first control signal 906~ comparison circuit; 1006~voltage source voltage divider; CMP~comparator; CS2~second control signal;
Flag、Flagl、Flag2〜比較電路之輸出旗標; I〜放電電流;Flag, Flagl, Flag2~ comparison circuit output flag; I~ discharge current;
Inv2〜第二反相器;Inv2 to second inverter;
Mi、M2、與M3〜電晶體 Ri與R2〜電阻; SWi〜第一開關; SW3〜第三開關;Mi, M2, and M3 ~ transistor Ri and R2 ~ resistance; SWi ~ first switch; SW3 ~ third switch;
Vbg〜能隙參考電壓; Ιηνγ第一反相器;Vbg~gap reference voltage; Ιηνγ first inverter;
Mn〜N型金氧半電晶體 SW2〜第二開關; SW4〜第四開關;Mn~N type MOS semi-transistor SW2~second switch; SW4~fourth switch;
Vdd〜電壓源; vdet、vdetl、vdet2〜偵測電壓。Vdd~ voltage source; vdet, vdetl, vdet2~ detection voltage.
Client’s Docket N〇,:VIT06-0147 TT's Docket No:0608-A41005-TW/Final /Glorious Tien 14Client’s Docket N〇,:VIT06-0147 TT's Docket No:0608-A41005-TW/Final /Glorious Tien 14
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CN101726649B (en) * | 2009-10-30 | 2013-04-24 | 海洋王照明科技股份有限公司 | Signal detection circuit, emergency power switching device and emergency light |
CN103516349A (en) * | 2012-06-26 | 2014-01-15 | 深圳市威尔科思技术有限公司 | High-voltage compatible input system |
US9081396B2 (en) * | 2013-03-14 | 2015-07-14 | Qualcomm Incorporated | Low power and dynamic voltage divider and monitoring circuit |
US10552756B2 (en) * | 2015-11-12 | 2020-02-04 | University Of Rochester | Superconducting system architecture for high-performance energy-efficient cryogenic computing |
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CN111092613B (en) * | 2018-10-23 | 2023-12-05 | 雅特力科技(重庆)有限公司 | Power-on reset circuit and related reset method |
CN111987754A (en) * | 2019-05-24 | 2020-11-24 | 凹凸电子(武汉)有限公司 | Mobile device and control method for supplying power to load |
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US11888474B2 (en) | 2020-06-03 | 2024-01-30 | Changxin Memory Technologies, Inc. | On die termination circuit and memory device |
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