1309837 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種半導體記憶體裝置；且更特定言之， 本發明係關於一種能夠藉由防止不必要之時脈之輸出來減 少電流消耗量的延遲鎖定迴路（DLL)驅動控制電路。 【先前技術】 諸如雙資料速率同步動態隨機存取記憶體（ddr SDRAM)之以高速操作之半導體記憶體裝置與外部時脈同 φ 步地傳輸貝料。對於該高速操作而言，必需建立時脈同步。 DLL電路建置於半導體中以取決於外部時脈來控制將自 DRAM向外部發送之資料的時序，以便使資料與時脈同 步。換言之，DLL電路用於接收外部時脈並基於該外部時 脈輸出資料。 圖1為習知DLL電路之方塊圖，且圖2為圖！中所示之通用 DLL驅動控制器1〇〇之電路圖。 參看圖1，習知DLL電路包括一 DLL時脈產生器3〇〇，該 Φ DLL時脈產生器300包含一時脈緩衝器、一延遲線、一相位 比較器、一延遲控制器及一延遲複製模型。dll時脈產生 器300藉由執行相位更新而產生與外部時脈之相位同步之 DLL時脈irclk及ifclk。DLL電路亦包括一用於驅動内部時脈 訊號irclk及ifclk之DLL驅動器200，及一用於控制DLL驅動 器200之開啟/關閉操作之Dll驅動控制器100。如圖2中所說 明，DLL驅動控制器1〇〇包含一n〇r閘NR，該NOR閘NR接 受一指示是否進入省電模式之訊號PDM，以及含有關於自 112688.doc 1309837 更新之資訊之訊號SREF。且N0RMR提供訊號刪以確定 是否操作DLL驅動器200。 如上文所建構之習知DLL電路允許肌驅動器在記憶 體之省電模式期間被關閉，以得到低功率消耗。 除省電模式或自更新模式以外，一旦輸入外部時脈，則 在現有dll驅動控制器i⑽控制之下的DIX驅動器便無 條件地提供輸出。在作料模式時間間隔期間始終致能 DLL驅動H2GG，且因此即使在不需要時脈之作用中模式之 部分時間間隔期間亦觸發DLL時脈。 在如上文所建構之習知DLL電路中，輸出端係與具有大 電容值之輸出資料路徑之許多緩衝器及電晶體閘耦接。愈 經常地觸發輸出時脈，DRAM中電流消耗量愈高。此電流 消耗可總计達到若干mA。 因此，習知DLL電路即使在其未被使用時亦產生時脈， 從而不必要地消耗能量。 【發明内容】 因此，本發明之一目的為提供一種DLL電路，其能夠在 正常模式以及省電模式或自更新模式中，藉由防止dll時 脈在任何時間間隔期間被無意義地觸發，從而將觸發限制 於實際使用DLL時脈之時間間隔，來減少⑽趙之操作電 流。 根據本發明之一態樣，提供一種DLL驅動控制電路，其 包括：一DLL驅動器，其用於驅動〇1^時脈；及一dll驅動 控制，其用於回應於具有與作用中模式相關聯之資訊之 112688.doc 1309837 -· 訊號而產生控制訊號，以控制該DLL驅動器之操作β • 該DLL驅動控制器包括：一計數器，其用於對該DLL時脈 進行計數以產生具有複數個位元之計數值；—比較器，其 用於比較該計數值與具有複數個位元之設定值，並在該兩 個值相同時產生經啟動之相等訊號；及一 SR鎖存器，其用 於接受該相等訊號及具有與該作用中模式相關聯之該資訊 之該訊號，以提供該控制訊號。 如上所述，本發明允許僅在當該DLL驅動器已關閉之狀 • 態下輸入與作用中模式（讀取或寫入）相關聯之訊號時之該 作用中模式之部分時間間隔期間觸發DLL時脈。 本發明之其它目的及優點將根據以下描述來理解，且亦 將根據本發明之實施例而更清楚地瞭解。 【實施方式】 下文中，將參考隨附圖式詳細闡明本發明之較佳實施 例，以使本發明可易於由熟習本發明所屬技術者執行。 圓3為根據本發明之較佳實施例之DLL電路的方塊圖。 _ 如圖3中所例示，本發明之DLL電路包括：時脈產 生器500’其具有一時脈緩衝器、一延遲線、一相位比較器、 -延遲控制器及—延遲複製模型，並用於藉由執行相位更 新而產生與外部時脈之相位同步之DLL時脈irclk&ifcik ; DLL驅動器400 ,其用於驅動〇[[時脈訊號及; 及-DLL驅動控制器·，其用於回應於具有與作用中模式 相關聯之資訊之訊號來控制DLL驅動器4〇〇之操作。 圖4例示圖3中所示之本發明之DLL驅動控制器则的詳 112688.doc 1309837 .細方塊圖。 如圖4中所示，DLL驅動控制器300包括：一計數器310， 其用於對DLL時脈irclk進行計數，以產生具有複數個位元 之計數值；一比較器330，其用於比較該計數值與具有複數 個位元之設定值320，以在該兩個值相同時產生經啟動之相 等訊號equal;及一 SR鎖存器340,其用於接受相等訊號equal 及具有與作用中模式相關聯之資訊之訊號RD info，以提供 控制訊號DEN。可使用（例如）延時相關之資訊作為設定值 > 320，該資訊係模式暫存器集（MRS)之設定值。該資訊可為 叢發長度（BL)或Cas延時（CL)。 下文中將詳細描述圖3及4中所示之本發明之DLL電路的 操作。計數器310對外部DLL時脈irclk進行計數，並產生具 有複數個位元之計數值，並將其提供至比較器330。在比較 器330處，將計數值之複數個位元與設定值320之位元進行 比較，以在其彼此匹配時啟動相等訊號。SR鎖存器340接收 經啟動之相等訊號equal及具有與作用中模式相關聯之資訊 ί 之訊號RD info，並啟動控制訊號DEN。在經啟動之控制訊 號DEN作為重設訊號RST輸入至計數器310時重設計數器 3 1 0，以重新開始對DLL時脈irclk進行計數。 圖5為圖4中所示之比較器330之詳細電路圖。 如圖5中所說明，比較器330具備：多個EX-NOR閘EXNR， 其分別用於接收計數值及設定值320之對應位元；一 NAND 閘ND3，其用於接收該多個EX-NOR閘EXNR中之每一者之 輸出；及一反相器INT2，其用於基於NAND閘之輸出訊號 112688.doc 1309837 -· 而產生相等訊號equal。 • 圖6為圖4中所示之SR鎖存器340之詳細電路圖。如圖6中 所示，SR鎖存器340包括：一反相·ΙΝΤ1，其用於接收具 有與作用中模式相關聯之資訊之訊號RD inf〇，· 一第一 NAND閘ND1，丨用於經由一個輸入端子接收反相器inti 之輸出；及一第二NAND閘nd2,其用於接收相等訊號equal 及第一 NAND閘ND1之輸出，以提供輸出訊號至第一 NAND 閘ND1之另一輸入端子。此811鎖存器34〇用於在啟動具有與 • 作帛"莫式相關聯之資訊之訊號⑽info時啟動控制訊號 DEN，並在啟動相等訊號equai時撤銷控制訊號。 如上文所述，藉由執行關於甚至在正常模式中實際上是 否需要時脈及關於必要時需要多少時脈之操作，本發明之 DLL驅動控制器3〇〇僅在需要時脈時藉由致能DLL驅動器 400來選擇性輸出時脈。DLL驅動控制器1〇〇僅在不使用時 脈（例如省電模式或更新模式）之範圍中控制時脈緩衝器2〇〇 之關閉操作。因此，防止了不必要之電流消耗。 • 圖7說明例如受暫存器控制之DLL之DLL時脈產生器5〇〇 的詳細方塊圖。參看圖7，DLL時脈產生器5〇〇大體包括一 時脈緩衝器10、一除頻器2〇、一相位比較器3〇、一延遲控 制器40、延遲線50、一虛設延遲線6〇及一延遲複製模型 化部分70。 時脈緩衝器ίο接收並缓衝外部時脈clk&clkb，並產生内 部時脈訊號iDvd_clk。 除頻器20對内部時脈iDvd_cik進行除頻，以基於内部時 112688.doc .1309837 ^Dvd—clk產生DLL源時脈Dvd_clk及參考時脈时—仙。通 常’源時脈係藉由經由除頻器降低外部時脈之頻率而產 生’以減少DLL電路之功率消耗。 相位比較器30為比較DLL電路之輸入時脈與其輸出時脈 並偵測其間之相位差的裝置。即，比較來自除㈣Μ之參 考時脈ref_elk之相位與經由DLL電路的内部電路反饋回之 反饋訊號反饋時脈，從而取決於比較結果來控制延遲控制 40。 工 _ 延遲㈣11 4G包含確定輸人路徑之邏輯元件及改變路徑 方向之雙向移位暫存器。移位暫存器接收四個輸入訊號: 執行移位操作。其-初始輸入條件可藉由保持兩端而允許 初始最大/最小延遲。為右移位及左移位中之每一者輸入兩 個訊號，且該個別兩個訊號具有高位準時間間隔，以使得 對於移位操作其彼此不重疊。 延遲線50為用於延遲外部時脈之相位之電路。相位延遲 之程度係由相位比較器30確定。決定相位延遲之延遲路徑 ® 係在延遲控制器4 0控制之下確定的。延遲線包含複數個單 位延遲單元，其中NAND閘耦接。單位延遲單元中之每一者 之輸入均連接至個別對應之移位暫存器。在移位暫存器之 輸出級處之值處於高位準之路徑經確定為用於接收通過時 脈緩衝杰之時脈的路控。存在用於上升邊緣時脈及用於下 降邊緣時脈之延遲線。此係為藉由同等地處理上升邊緣及 下降邊緣而在任何一方向上最大限度地防止隨後之失真 (工作比失真（(duty ratio distortion)))。 112688.doc -10· 1309837 .虛設延遲線60係為施加至相位比較器30之反饋訊號而提 供之延遲線，且具有與延遲線5 0相同之構造。 延遲複製模型化部分70預先模型化自接收外部時脈至延 遲線50直至將延遲線50之輸出時脈配送至晶片外部的延遲 因子。正確之延遲因子係用於確定一作為DLL電路之效能 的失真值。延遲複製模型化部分70可按照原狀使用收縮、 簡化及使用基本電路的方法。可預先對其進行設計，以使 延遲複製模型化部分70按照原狀模型化時脈缓衝器、DLL > 驅動器、R/F除頻器及一輸出缓衝器。 圖8為用於描述根據本發明之DLL驅動控制方法之時序 圖。如圖8中所示，若接收到具有與作用中模式（諸如讀取 或寫入模式）相關聯之資訊之外部訊號RD info，則啟動控制 訊號DENr及DENf。若計數值B與設定值A彼此匹配，則控 制訊號DENr及DENf由經啟動之相等訊號equal予以撤銷。 僅在控制訊號DENr及DENf之啟動時間間隔期間驅動DLL 驅動器400，以觸發DLL時脈RCLK—DLL及FCLK_DLL。在 | 上升控制訊號DENr之高脈衝時間間隔的範圍内觸發上升 DLL時脈RCLK_DL，同時在下降控制訊號DENf之高脈衝時 間間隔的範圍内觸發下降DLL時脈FCLK—DLL。此時序圖可 基於DRAM之操作條件而部分地變化，且本文中所示之時 序圖為各種實例中之一項實例。 根據本發明之另一實施例，對於多種多樣之應用，若DLL 驅動器不是單個而是複數個，則亦可能相應地建構DLL驅 動控制器。 112688.doc -11 - 1309837 如上文所闡明，本發明具有之優點在於，憑藉本發明之 構造，可藉由連續控制由於時脈速度之增加而被消耗的電 流來減少無意義地流動之電流，從而大幅減少電流消耗。 本申請案含有與在2005年9月29日及12月19日於韓國專 利局申請之韓國專利申請案第2005-9165〇號及第 2005-125353號有關的發明，該等專利申請案之全文以引用 的方式併入本文中1309837 IX. Description of the Invention: The present invention relates to a semiconductor memory device; and more particularly, to a method capable of reducing current consumption by preventing unnecessary clock output A delay locked loop (DLL) drives the control circuit. [Prior Art] A semiconductor memory device operating at a high speed such as a dual data rate synchronous dynamic random access memory (ddr SDRAM) transmits a bedding material in the same manner as an external clock. For this high speed operation, clock synchronization must be established. The DLL circuit is built into the semiconductor to control the timing of the data sent from the DRAM to the outside depending on the external clock to synchronize the data with the clock. In other words, the DLL circuit is used to receive an external clock and output data based on the external clock. Figure 1 is a block diagram of a conventional DLL circuit, and Figure 2 is a diagram! The general-purpose DLL driver controller shown in Figure 1 is a circuit diagram. Referring to FIG. 1, the conventional DLL circuit includes a DLL clock generator 3, which includes a clock buffer, a delay line, a phase comparator, a delay controller, and a delayed copy. model. The dll clock generator 300 generates a DLL clock irclk and ifclk synchronized with the phase of the external clock by performing a phase update. The DLL circuit also includes a DLL driver 200 for driving the internal clock signals irclk and ifclk, and a D11 drive controller 100 for controlling the on/off operation of the DLL driver 200. As illustrated in FIG. 2, the DLL drive controller 1A includes an n〇r gate NR that accepts a signal PDM indicating whether to enter the power saving mode, and contains information about the update from 112688.doc 1309837. Signal SREF. And N0RMR provides a signal deletion to determine whether to operate the DLL driver 200. The conventional DLL circuit constructed as above allows the muscle driver to be turned off during the power saving mode of the memory to achieve low power consumption. In addition to the power save mode or the self-updating mode, once an external clock is input, the DIX driver under the control of the existing dll drive controller i (10) provides the output unconditionally. The DLL is always enabled during the feed mode interval to drive H2GG, and thus the DLL clock is triggered even during partial time intervals of the mode in which the clock is not required. In the conventional DLL circuit constructed as above, the output is coupled to a plurality of buffers and transistor gates having an output data path having a large capacitance value. The more often the output clock is triggered, the higher the current consumption in the DRAM. This current consumption can amount to a few mA in total. Therefore, the conventional DLL circuit generates a clock even when it is not used, thereby consuming energy unnecessarily. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a DLL circuit capable of preventing a dll clock from being meaninglessly triggered during any time interval in a normal mode as well as a power saving mode or a self-updating mode. Limit the trigger to the actual time interval of the DLL clock to reduce (10) Zhao's operating current. According to an aspect of the present invention, a DLL drive control circuit is provided, comprising: a DLL driver for driving a clock; and a dll drive control for responding to having a function associated with an active mode The information 112688.doc 1309837 - signal generates a control signal to control the operation of the DLL driver. The DLL driver controller includes: a counter for counting the DLL clock to generate a plurality of bits. a counter value; a comparator for comparing the count value with a set value having a plurality of bits, and generating an activated equal signal when the two values are the same; and an SR latch for using The signal is received by the equal signal and the information associated with the active mode to provide the control signal. As described above, the present invention allows the DLL to be triggered during a partial time interval of the active mode when the signal associated with the active mode (read or write) is input only when the DLL driver is turned off. pulse. Other objects and advantages of the present invention will be understood from the following description. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in which the present invention can be readily implemented by those skilled in the art. Circle 3 is a block diagram of a DLL circuit in accordance with a preferred embodiment of the present invention. As illustrated in FIG. 3, the DLL circuit of the present invention includes: a clock generator 500' having a clock buffer, a delay line, a phase comparator, a delay controller, and a delay replica model, and is used to borrow A DLL clock irclk&ifcik; DLL driver 400 for synchronizing the phase with the external clock by performing phase update, which is used to drive 〇[[clock signal and; and -DLL driver controller, which is used to respond to The signal with the information associated with the active mode controls the operation of the DLL driver. Figure 4 illustrates a detailed block diagram of the DLL drive controller of the present invention shown in Figure 3, 112688.doc 1309837. As shown in FIG. 4, the DLL driver controller 300 includes a counter 310 for counting the DLL clock irclk to generate a count value having a plurality of bits, and a comparator 330 for comparing the a count value and a set value 320 having a plurality of bits to generate an activated equal signal equal when the two values are the same; and an SR latch 340 for accepting the equal signal equal and having an active mode The associated information signal RD info is provided to provide the control signal DEN. The information related to the delay, for example, can be used as the set value > 320, which is the set value of the mode register set (MRS). This information can be burst length (BL) or Cas delay (CL). The operation of the DLL circuit of the present invention shown in Figs. 3 and 4 will be described in detail hereinafter. The counter 310 counts the external DLL clock irclk and generates a count value having a plurality of bits and supplies it to the comparator 330. At comparator 330, the plurality of bits of the count value are compared to the bits of set value 320 to initiate an equal signal when they match each other. The SR latch 340 receives the activated equal signal equal and the signal RD info having the information ί associated with the active mode, and activates the control signal DEN. When the activated control signal DEN is input to the counter 310 as the reset signal RST, the counter 3 1 0 is reset to restart counting the DLL clock irclk. FIG. 5 is a detailed circuit diagram of the comparator 330 shown in FIG. As illustrated in FIG. 5, the comparator 330 is provided with a plurality of EX-NOR gates EXNR for receiving the corresponding values of the count value and the set value 320, and a NAND gate ND3 for receiving the plurality of EX- An output of each of the NOR gates EXNR; and an inverter INT2 for generating an equal signal equal based on the NAND gate output signal 112688.doc 1309837 -. • Figure 6 is a detailed circuit diagram of the SR latch 340 shown in Figure 4. As shown in FIG. 6, the SR latch 340 includes an inversion · ΙΝΤ1 for receiving a signal RD inf 具有 having a message associated with the active mode, a first NAND gate ND1, 丨Receiving an output of the inverter inti via an input terminal; and a second NAND gate nd2 for receiving the equal signal equal and the output of the first NAND gate ND1 to provide an output signal to the other input of the first NAND gate ND1 Terminal. The 811 latch 34 is used to activate the control signal DEN when the signal (10)info having the information associated with the "" is activated, and the control signal is revoked when the equal signal equai is activated. As described above, the DLL drive controller 3 of the present invention performs only when the clock is needed by performing an operation on whether or not the clock is actually needed even in the normal mode and how many clocks are needed as necessary. The DLL driver 400 can be used to selectively output the clock. The DLL drive controller 1 controls the shutdown operation of the clock buffer 2〇〇 only in the range of no clock (e.g., power save mode or update mode). Therefore, unnecessary current consumption is prevented. • Figure 7 illustrates a detailed block diagram of a DLL clock generator 5A, such as a DLL controlled by a scratchpad. Referring to FIG. 7, the DLL clock generator 5A generally includes a clock buffer 10, a frequency divider 2A, a phase comparator 3A, a delay controller 40, a delay line 50, and a dummy delay line 6A. And a delayed copy modeling portion 70. The clock buffer ίο receives and buffers the external clock clk&clkb and generates an internal clock signal iDvd_clk. The frequency divider 20 divides the internal clock iDvd_cik to generate a DLL source clock Dvd_clk and a reference clock based on the internal time 112688.doc .1309837 ^Dvd-clk. Typically the 'source clock' is generated by reducing the frequency of the external clock via the frequency divider to reduce the power consumption of the DLL circuit. The phase comparator 30 is a device that compares the input clock of the DLL circuit with its output clock and detects the phase difference therebetween. That is, the phase of the reference clock ref_elk from (4) 与 is compared with the feedback signal feedback clock fed back via the internal circuit of the DLL circuit, thereby controlling the delay control 40 depending on the comparison result. _ Delay (4) 11 4G contains the logic elements that determine the input path and the bidirectional shift register that changes the direction of the path. The shift register receives four input signals: Performs a shift operation. Its - initial input condition allows the initial maximum/minimum delay by holding both ends. Two signals are input for each of the right shift and the left shift, and the individual two signals have a high level time interval such that they do not overlap each other for the shift operation. The delay line 50 is a circuit for delaying the phase of the external clock. The degree of phase delay is determined by phase comparator 30. The delay path ® that determines the phase delay is determined under the control of the delay controller 40. The delay line includes a plurality of unit delay units in which the NAND gates are coupled. The inputs of each of the unit delay units are coupled to respective corresponding shift registers. The path at which the value at the output stage of the shift register is at a high level is determined to be the path for receiving the clock through the clock buffer. There are delay lines for the rising edge clock and for the falling edge clock. This is to minimize the subsequent distortion (duty ratio distortion) in either direction by equally processing the rising edge and the falling edge. 112688.doc -10· 1309837. The dummy delay line 60 is a delay line provided for the feedback signal applied to the phase comparator 30, and has the same configuration as the delay line 50. The delayed copy modeling portion 70 pre-models the delay factor from the receipt of the external clock to the delay line 50 until the output clock of the delay line 50 is delivered to the outside of the wafer. The correct delay factor is used to determine a distortion value that is the performance of the DLL circuit. The delayed copy modeling portion 70 can use the method of shrinking, simplifying, and using the basic circuit as it is. It can be designed in advance so that the delayed copy modeling portion 70 models the clock buffer, the DLL > driver, the R/F divider, and an output buffer as they are. Figure 8 is a timing chart for describing a DLL drive control method according to the present invention. As shown in Fig. 8, if an external signal RD info having information associated with an active mode (such as a read or write mode) is received, the control signals DENR and DENf are activated. If the count value B and the set value A match each other, the control signals DENR and DENf are revoked by the activated equal signal equal. The DLL driver 400 is driven only during the start time interval of the control signals DENR and DENf to trigger the DLL clocks RCLK_DLL and FCLK_DLL. The rising DLL clock RCLK_DL is triggered within the range of the high pulse interval of the rising control signal DENR, and the falling DLL clock FCLK_DLL is triggered within the range of the high pulse time interval of the falling control signal DENf. This timing diagram may vary in part based on the operating conditions of the DRAM, and the timing diagrams shown herein are one example of various examples. According to another embodiment of the present invention, for a wide variety of applications, if the DLL drivers are not single but plural, it is also possible to construct the DLL drive controller accordingly. 112688.doc -11 - 1309837 As explained above, the present invention has the advantage that, by virtue of the configuration of the present invention, the current flowing insignificantly can be reduced by continuously controlling the current consumed by the increase in the clock speed, This greatly reduces current consumption. The present application contains the inventions relating to Korean Patent Application No. 2005-9165, and No. 2005-125353, filed on Sep. 29, 2005, and on December 19, 2005, the entire contents of Incorporate this article by reference
雖然已關於特定實施例描述了本發明，但熟習此項技術 者將易於瞭解，在不偏離如以下申請專利範圍中所界定之 本發明之精神及範疇的情況下，可進行各種改變及修改。 【圖式簡單說明】 圖1為習知DLL電路之方塊圖； 圖2為圖1中所示之DLL·驅動控制器之電路圖； 圖3為根據本發明一實施例之DLL電路之方塊圖； 圖4為圖3中所示之DLL驅動控制器之詳細方塊圖； 圖5為圖4中例示之比較器之詳細電路圖； 圖6為圖4中說明之SR鎖存器之詳細電路圖； 圖7為圖3中所示之DLL時脈產生器之詳細方塊圖；及 圖8為用於描述根據本發明之DLL驅動控制方 圖。 石炙日守序 【主要元件符號說明】 1〇 時脈緩衝器 2〇 除頻器 30 , 相位比較器 112688.doc -12- 1309837 40 延遲控制器 50 延遲線 60 虛設延遲線 70 延遲複製模型化部分 100 DLL驅動控制器 200 DLL驅動器 300 DLL時脈產生器/DLL驅動控制器 310 計數器 320 設定值 330 比較器 340 SR鎖存器 400 DLL驅動器 500 DLL時脈產生器While the invention has been described with respect to the specific embodiments of the present invention, it will be understood that various modifications and changes may be made without departing from the spirit and scope of the invention as defined in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a conventional DLL circuit; FIG. 2 is a circuit diagram of a DLL driver controller shown in FIG. 1; FIG. 3 is a block diagram of a DLL circuit according to an embodiment of the present invention; 4 is a detailed block diagram of the DLL drive controller shown in FIG. 3. FIG. 5 is a detailed circuit diagram of the comparator illustrated in FIG. 4. FIG. 6 is a detailed circuit diagram of the SR latch illustrated in FIG. A detailed block diagram of the DLL clock generator shown in FIG. 3; and FIG. 8 is a diagram for describing a DLL drive control map according to the present invention.石炙日守序 [Main component symbol description] 1〇clock buffer 2〇frequency divider 30, phase comparator 112688.doc -12- 1309837 40 delay controller 50 delay line 60 dummy delay line 70 delay replication modeling Portion 100 DLL Driver Controller 200 DLL Driver 300 DLL Clock Generator / DLL Driver Controller 310 Counter 320 Setpoint 330 Comparator 340 SR Latch 400 DLL Driver 500 DLL Clock Generator
112688.doc -13 -112688.doc -13 -