TWI301319B - Trapping storage flash memory cell structure with undoped source and drain regions - Google Patents

Description

I301M 16402twf.doc/006 IX. Description of the Invention: [Technical Field of the Invention] In particular, the present invention relates to a non-volatile memory package relating to a charge trapping flash memory. [Prior Art] Electrically programmable based on a charge storage structure known as electrically erasable programmable read only memory (EEPROM) and flash memory = erasable unless volatile storage technology is used in many modern applications. The flash body is a memory element that can be independently programmed and read. Flash = Body = Money Amplifier to determine the value of - or eve (four) stored in non-volatile memory. In a typical sensing scheme, the current sense transducer will sense the current through the memory and the reference current compared to the reference current. The I" structure is used for the M and flash memory. The size of the channel is reduced with the scalability of the manufacturing process and the simplicity of the memory cell of the enemy dielectric layer. The memory cell structure based on the charge trapping dielectric layer includes ^

^ )Nitride Read-Only Memory > SONGS ^ PHINES structure. Record the M-cell structure by charging her dielectric layer (eg °, 4 body early blessing light increase. Touch removal to reduce the counting unit sing. · Read the capture layer nitride read-only memory device is relatively thick For example, greater than 3 nanometers and usually about 5 to 9 nanometers to prevent electricity. 13013⁄4 replaces direct wear with 5 16402twf.doc/006, with hot hole injection (btbthh) = two: Said unit. However, 'hot hole injection causes oxide damage, , and the charge in the south start unit is difficult and the increase in the low start unit. In addition, 'attributable to the charge trapped in the charge trapping structure ^ ^ The erasing time must be gradually increased during the stylization and erasing of the loop.) Since the two injection points do not coincide with each other and the two electrons are repelled after the erasing pulse, this charge accumulation occurs. In addition, the magnetic area of the memory-only flash memory device = change (for example, channel length variation), and the erase speed of each cell = 2. This difference in wipe speed results in a large vt distribution of the erased state, i - some early read hard to erase and some cells are over erased. So after many stylization and erase loops, the target starts v t window _, . As the technology continues to scale down, this phenomenon will become more of a nitride-only read-only memory. (IV) The memory cell structure places the material-nitride-oxide layer on the conductive polycrystalline stone and the crystal stone. Between the half bottom. The substrate is a source region that is separated by a base channel region. The flash recording can be performed by bungee sensing or source sensing. For source side sensing, one or more poles face the source area of the unit, to read the specific unit in the 2 columns. Each unit of the conventional floating gate device of the u-body array only stores the 丨 bit, but now a nitride-only memory unit, in which each flash unit of each woven material read-only unit provides 2 bits. The flash cell has an electrical phase 16402 twf.doc/006 ΐΓΐ ΓΓ ΓΓ structure in which the nitride layer is used as a capture material disposed between the top two: moving layers. (10) A closed-pole dielectric in which the 0-layer structure is effectively placed. Can be used in nitride read-only memory. On the right side of the shell, the 〇n〇 dielectric with a nitride layer is captured. The outer surface of the 程式n于 程式 程式 程式 程式 程式 唯 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ In the erasing operation period a #在抹除, the common technique of the body unit is called the paired-band thermoelectric hole. The nitride-only (5) 5-body unit has a lateral electric field effect on the side different from the erased side. It is estimated that the durability and retention of the nitride read-only array, the lack of wiping ability, leads to the loss of the ring and baking. The side of the nitride-reading memory unit is floating (or connected to the ground), which can be folded to an indeterminate voltage level of 2 cases: 1 volt or 4 volts) 'This leads to the erasing of the array unit ^ This results in a wider Vt distribution after the erase operation. Uncertain changes in the voltage level ^ can result in excessive erasure. On the other hand, if the other side is connected to the "face, then when the bit line bias exceeds the punch-through voltage, the punch-through can cause the pump circuit to collapse. Therefore, during the erase operation of the block, the nitride is read only. Memory cells (some of which are left floating) can result in a lack of uniformity in the voltage level used to erase the nitride-reading cells in the nitride read-only memory array. 3 Technological advances in flash memory devices Need to design a charge trapping flash memory that provides higher packing density and better device scalability. The invention is described for manufacturing a plurality of two-element charges. A method of capturing a charge of a snap cell of a flash memory, wherein each memory cell is formed with a Si-FIN layer, the & side layer having an inverted source and a non-polar region. - each adjacent polylithic gate of the selected polycrystalline silicon in the row memory cell is used to generate an inversion region, acting as a source region or a non-polar region 'for transmitting a required voltage, In each memory The density of the memory cell is preserved in the case where the source region and the drain region of the cell are undoped. The flash memory includes a plurality of multiple 曰 矽 layers crossing a plurality of Si_Fm layers: when in-line memory Selecting a memory unit in the body unit for performing the second type, the first group of memory on the left side of the unit during the erasing, erasing operation or reading operation, and the first unit of the unit Electricity_transfer_,; = right second group of memory cells acts as the transfer gate of the voltage-transfer with the body-body. ~ wear-follow (FN) erase P-pole Fule Noltheim style And in the thermoelectric hole (HH) process for the closed gate of the selected gate=selection, the side> includes including each of the ones in the operating method domain, the unloaded_charge trapping memory array= The source and the immersion region are selected to open the channel for the hot electrons (c: for the privateization, for the selected 8 1301, the 16402twf.doc/006 gate for the hot hole erase and for each In terms of the operation steps, select the pendulum; select, the pole performs the reading operation. It is used to perform the specific memory of stylization, erasure or = two The body unit acts as a unit for transmitting the required voltage = other memory unit in the ,, with the gate electrode, the first side of the uncharged and captured memory, the two single adjacent memory unit doping The source region and the undoped two have, the pole, the non-body unit, the adjacent capture of the first memory cell, the memory cell has a gate electrode, the second drain region is not; and the Si_FIN layer Crossing the first and undoped second charge enumeration unit and the first capture unit, extending. Le-his memory memory cell orthogonal; 4Γ = invention produces a more compact charge trapping memory, Scale with the same degree 'because the source of each cell is ::::: and each cell is not reserved or occupied for the source and == under. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to Figure 1A, there is shown a block diagram showing a structure (10) having a facet flash cell structure. The junction == 15 16402 twf.doc / 006 polycrystalline germanium (or polysilicon gate) layer no, which covers the oxide-nitride-oxide (germanium) film 120, with the source region 130 on the left side and the drain region 140 on the right side . The tantalum film 120 provides a charge trapping structure for a two bit operation in which the first bit is on the left side and the second bit is on the right side. The Si-FIN layer 150 extends in a direction perpendicular to the polycrystalline layer 110. The source region 130 and the gate region 140 are not interchanged, that is, there are no implants in the source region 130 and the gate region 140. Specifically, structure 100 uses adjacent polysilicon gates 11A to create an inversion region to serve as a source/drain region ® domain for delivering the desired voltage. The source/drain regions are limited to smaller regions for inversion, which results in smaller cell sizes and higher scalability.

As shown in Fig. 1B, it is a layout diagram illustrating an array 16 of memory cells in which a polysilicon layer is placed in contact with a Si-FIN layer. The majority of the rows of polysilicon layers 170, 171, 172, and 173 are disposed substantially orthogonal to the plurality of columns of Si-FIN layers 180, 181, 182, 183, and 184. One of the mothers in the si_piN layer extends over a plurality of polycrystalline layers. For example, the 180 layers extend over the polysilicon layer 170, the polysilicon layer 171, the polysilicon layer 172, and the polycrystalline layer 173. The i-pole region 140 of Figure 1A is shown in Figure 1B, wherein a portion of the polycrystalline layer 170 intersects the Si_FlN^18. The charge trapping flash cell structure 100 is capable of performing a two bit operation, and the illustrative first type relates to FN erasing and thermoelectric hole staging, and illustrates the cavity erasing and channel hot electron stylization. There are two types: the method, the type of interpolation with FN erasure and thermoelectric hole stylization. In the brother-method, two bits on both sides of the charge trapping unit are I301U2 15 16402twf.doc/006 = status (FN wears, electrons are applied at the nitride thin cell voltage, the selected "capture" Will be about zero volts and about i 5 volts ==, with the high side of the high Vt. When the two sides of the charge trapping unit are respectively: in the method - the hole is injected into the nitride film (ie, using the hot line) Stylized. When the right side of the ~^= catching_) is respectively entered into the leftmost and rightmost of the selected unit, the volt: is applied to the side of the formula. When respectively, about zero volts = the one with the low Vt The leftmost and rightmost Japanese of the unit selected by the process, a voltage of Shida special is applied to the side of the formula. π σ is taken from the unprocessed line with Vt; heat =: and the channel hot electron element The two bits on both sides of the wiper (four) t;; square charge charge single and about zero volts voltage applied to the selected; a field ^ will be about 15 volts, read with low Vt ^ right eight, early 70 The voltage applied to the left end and the far right end is applied to the selected field knife and will be about zero volts and about 1.5 volts; there is ... left;:: the most r: r and r: Into the nitride film] If, for example, in the channel thermoelectric capture unit on one side of the unit: into: program: then, the charge is trapped and about zero volts to the return of the evil. When respectively At about the right end of the 1.5, when reading the leftmost & most significant _ of the cell selected by the & port, the leftmost >015 16402twf.doc/006 end and the rightmost end, the read has a low Vt The unprogrammed side. In Figures 2A-2C, circuit diagrams illustrating the first method of operation of the erase operation 200, the stylization operation 240, and the read operation 260 of the charge trapping flash memory array 160, respectively, are shown. In this first method of operation, the method is performed in the following manner: using Fowler-Nordheim tunneling to erase memory cells; using a hot hole to enter The memory unit is programmed; and the memory unit is read. As shown in FIG. 2A, if the gate 203 is to be erased, the remaining gate unit, that is, the gate 201 and the gate 202 , gate 204, gate 205, gate 206 and gate 207 all serve to transmit electricity The transfer gate of the voltage. The term "gate" in this specification is also referred to as "gate cell,", or "gate in charge trapping unit". The gate unit, ie the gate 2〇 1. Gate 202, gate 204, gate 2〇5, gate 2〇6, and gate 2〇7 charge f the second voltage level, for example 10 volts, and charge the gate 2〇3 unit to 咼A second voltage level, such as 20 volts, is used to erase the gate 203 cell using FN tunneling. The Si_FIN layer 21 一直 extends from the left side of the gate 2〇1 to the right side of the gate 207; extends through the gate 2 〇 1, gate pole, pole 203, gate 204, gate 205, pole 206 and gate 2〇7. The gate 2〇1, the gate 20j, the interpole 203, the interpole 2〇4, the interpole 2〇5, the closed electrode and the interpole 207 5 are again placed on the oxide layer 22〇±. Shi Xi 23〇 is deeply doped adjacent to the right side of the closed-pole technique and is disposed above the oxide layer 22〇. After the erase operation, the sequence proceeds to the stylization operation 240, using the 孰 财 财 人 电荷 电荷 电荷 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Memory single 12 1301319 P940015 16402twf.doc/006 yuan 'where the first position is on the left side and the second position is on the right side. The stylization of the gate 203 using thermowell injection is applied to the right side 203-r of the gate 203. With respect to the left side 2034 of the gate 203, it is set to about zero volts, and the right side 203-r of the gate 203 has a higher voltage potential, which is set to about 5 volts. A voltage difference of 5 volts between the right side 203-r and the left side 203-1 produces a hot hole condition on the right side, which results in storage in the nitride layer associated with the gate 2〇3.

Alternatively, the stylization of the gate 2〇3 using the thermal hole injection can be applied to the left side 203-1 of the gate 203. The right side 203-r' of the gate 2〇3 is not about zero volts, and the left side 203-1 of the gate 203 has a relatively high voltage potential, which is set to about 5 volts. A voltage difference of 5 volts between the left side 203-1 and the right side 2〇3-r creates a thermoelectric hole on the left side, which results in charge storage in the nitride layer associated with the gate 203 cell. Therefore, the stylization of the gate 203 using the hot hole injection can be applied to the right side 203-r or the left side 203-1 of the gate 2〇3.

After the stylization operation, the sequence proceeds to read operation 260 to read the gate f 203 unit. The charge is turned on the right side 2〇3_r of the gate 203, so that the reading operation is performed on the left side of the gate 203. As time changes, the starting voltage Vt will tend to drift higher. Although the above: _ 2 is on the right side of the question and the reading operation is performed on the left side of the gate 7^2_3_1, but the general-purpose person in the field 'charges the charge on the left side, and the read operation When the interpole 203 is selected on the right side to perform an erase operation, a program operation, or a read 13 I3〇13p1215 16402twf.doc/006 operation, the remaining adjacent units, that is, the interpole 2 inter-electrode 2〇2 Asahi The gate 2〇5, the interpole and the gate 2〇7 serve as the transfer idle. The advantage of this is that it reduces the memory by using adjacent cells as transfer memes, which is a conventional solution to the operation of transmitting the closed pole by requiring additional closed poles associated with each of the memory cells. Circuit in the body array = number. For example, if the gate 2〇5 is selected to be erased, the dimension 20 gate 202, the gate 2〇3, the gate, the gate, and the interpole 207 serve to pass (4) to the gate. The pole of the pole 2〇5. Fig. 3A to Fig. 3A are circuit diagrams of a second operation method in the process of erasing and reading the charge trapping array. In the second fall = two, is the stylized memory unit, erase the memory unit 3 〇Γ = as shown in Figure 3, if the gate 3 〇 3 is selected to use channel hot electrons (CHE) For the stylization operation, the paste 303_Γ of the gate 303 is about 5 volts, and the polarity is 3 〇 3 = about zero volts. On the left side of the closed-end 3〇3, the interpole 3q =

The Lt is electrically connected to the transfer pole on the left side of the interpole 303. = then zero volts is passed to the gate gauge, and gate 302 passes zero volts to the left side of gate 303. On the right side of the gate 3〇3, the gate, the gate 305, the gate 3〇6, and the gate 3〇7 serve as the transfer volts for the right side of the interpole 303: the pole 问 'question pole 3. 6 Pass 5 volts to the interpole 2 Pass 5 volts to the gate 3〇4 305 3〇3 to the right 303_Γ The idle pole 304 passes 5 volts to the interpole and passes zero volts to the left side of the gate 303-i And after transferring 5 volts i3〇im 16402twf.doc/006 to the right side 303-r of the gate 303, channel hot electrons are generated. The zero volt from the left side 303-1 accelerates the electron toward the right side 3〇3_r of about 5 volts, and is attributed to the higher potential of the polycrystalline germanium gate 3〇3 to which 7 volts is applied, called accelerated electrons of hot electrons. It is injected into the nitride layer (tantalum film 120). The right side 303-r of the gate 3〇3 is then programmed by channel hot electron injection. Figure 3B is a circuit diagram illustrating an erase operation 330 of a charge trapping flash memory array 16 through thermal cavity injection. If the gate is selected for erasing, the remaining gate cells, namely the gate 3, the gate 3, the gate 304, the gate 305, the gate 306 and the gate 307 serve to transfer the voltage. Gate. The gate unit, that is, the gate 3 闸 gate 3 〇 2, the gate 3 〇 4, the gate 305, and the gate 307 are charged to a first voltage level, that is, 1 volt, and the gate 303 -5 volts on the right side 303-r is injected into the gate 303 through a thermoelectric hole. The SkFIN 310 layer extends from the left side of the gate 301 to the right side of the gate 307' including extending through the gate 3〇1, the gate, the gate 303, the interpole 304, the gate 305, the gate 306, and the gate 307. . A gate 3A1, a transistor 302, a gate 303-, a gate 304, a gate 3〇5, a gate 3〇6, and a gate 307 are disposed on the oxide layer 32A. A flap (smc〇n Fin) 33〇 is deeply doped on the right side of the gate 307 and the left side of the gate 301. The flaps 330 are placed on top of the oxide layer 32A. After the erase operation, the sequence is read to the read operation 36 to read the gate 3〇3. The charge is stored on the right side 3〇3_r of the gate 303, so that the reading operation is performed on the left side 303-1 of the gate 303. As time changes, the initial private pressure Vt will tend to drift higher. Although the above description shows that the charge reservoir 15 13 tw 13 15 15 402 twf.doc / 006 exists on the right side 303_r of the gate 303, and the reading operation is performed on the 4 J 303 1 of the gate 3 〇 3, but the field One of ordinary skill will recognize that, where, it can be stored on the left side and the read operation is performed on the right side. One difference between the first interpolation method 200 and the second operation method 3A is the inverse relationship between the low starting voltage and the high starting voltage. First • Operation Green 200 uses FN to erase the memory unit, which will memorize • Element _ High Start. The second method of operation uses a thermocouple to erase the memory cell, which erases the memory cell to the voltage. Figure 4 is a flow diagram illustrating the process of performing the erase operation 2, the stylization operation 24, and the read operation 260 of the first method of operation of the charge trapping flash memory array 16A. At step 41, the first method of operation 4 选择 selects the gate 2〇3 in the row to be erased by using the 胄雷_诺特海式穿穿, and the other gates, ie the gate 2 The gate 2 〇 2, the gate 2 〇 4, the gate 205, the gate 206, and the gate 207 serve as transfer gates for transmitting voltage. Charging the unselected gates, ie, the gate 2, the gate 2, the gate 2, the gate 205, the gate 206, and the gate 207, to a first voltage level, such as 10 volts, The gate 4 204 is charged up to a second voltage level, such as 20 volts, to erase the gate 203 by tunneling using fn. At step 420, the first method of operation 〇〇 uses the hot hole injection in the charge trapping flash memory array 160 to program the gate 2〇3. The stylization of the gate 203 uses thermowell injection, which is applied to the right side 203-r of the gate 203. With respect to the left side 203-1 of the gate 203, it is set to about zero volts, and the right side 203-r of the gate 203 has a higher power 16 13 〇 13 di 16402 twf.doc / 006 granules whose setting domain is 5 volts. If the phase is selected, then -5 volts is applied to the interpole 203. A voltage difference of 10 volts on the right side 2 〇 3 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ In step 430, the 'first operational method' includes performing a read miss on the gate 2〇3 in the charge trapping fast complement array 160. On the right side of the electric gate 2〇3, the reading operation is performed on the left side of the pole 2〇. When the gate 2〇3 is erased, the initial voltage Vt will tend to drift higher as time passes. Although the above description shows that charge is stored on the right side 203-r of the gate 203, and the read operation is performed on the left side 2〇3_丨 of the gate 203, one of ordinary skill in the art should recognize that the charge can be Stored on the left side, and the read operation is performed on the right j. FIG. 5 is a second illustration of the operation of performing the program operation 3〇〇, the erase operation, and the read operation 360 of the charge trapping flash memory array 16〇. A flowchart of the process of operating method 500. At step 51, the second method of operation 500 includes the use of channel thermo-electronic techniques to program the selected two-to-two-stroke. The right side 3 〇 3-r of the gate 303 is about 5 volts, and the left side 303-1 of the gate 3 〇 3 is about zero volts. On the left side of the gate 3〇3, the gate 3〇i and the gate 302 serve as transfer gates for transmitting a voltage to the left side of the gate 3〇3. The gate 301 transmits zero volts to the gate 3〇2, and the gate 3〇2 transfers zero volts to the left side of the gate 303. 3〇3- is on the right side of the gate 303, the gate 304 and the gate 305 Gate 306 and gate 307 serve as pass gates for delivering a stylized voltage to the right side of gate 303. Gate 307 transfers 5 17 I3013A1 16402twf.doc/006 volts to gate 306, gate 306 transfers 5 volts to gate 3〇5, gate 305 transfers 5 volts to gate 304, gate 3〇4 Transfer 5 volts to the gate 303 # right 303_r. After passing zero volts to the left side 303-1 of the sense electrode 3〇3 and 5 volts to the right side 3〇3_γ of the gate 3〇3, a channel hot electron condition is generated. Zero volts from the left phase-1 causes the electrons to accelerate toward the right side 303_r of approximately 5 volts, and due to the higher potential of the 7 volts of the ruthenium gate 303, it will be called hot electrons. Accelerated Electron Note • 彡 into the nitride layer (ΟΝΟ film 12G). The right side 303-r of the gate 3〇3 is then programmed by channel hot electron injection. At step 520, the second method of operation 5 includes performing a charge trapping operation of the flash memory array 3GG through the hot hole injection. If the gate 303 is selected for erasing, the remaining gate cells, namely the gate 3〇1, the gate 302, the gate 304, the gate 3〇5, the gate 3〇6, and the gate 3 serve The voltage is transmitted to the transfer gate of the gate 3〇3. The gate unit, ^ gate=1, the interpole 302, the gate 304, the gate 305, and the gate 7 3〇7 are charged to the S voltage level, for example, 1 volt, and by using the note • S. PIN ^ 31 〇 303: 5 volts on the upper to erase the gate 3〇3, and _5 volts applied to the gate 53Q'. The second operation method 5()() includes performing the idle pole 303 ^ f (four). The charge is stored on the right side of the gate period _ 进行 on the left side of the gate 303. With time = the initial voltage Vt will tend to drift higher. Although the present invention has been disclosed above by way of example, it is not intended to limit the invention of 18 13013 αΐ5 16402 twf.doc/006. Anyone skilled in the art, within the circumference, may make some more; with retouching, due to this = The spirit and the scope of the application are defined as the scope of protection of the scales U. [FIG. 1AS] FIG. 1AS illustrates a structure diagram of a charge trapping flash unit according to an embodiment of the present invention. 1B is a layout diagram illustrating a charge trapping paste unit in accordance with an embodiment of the present invention. FIGS. 2A-2C are diagrams illustrating = and reading a charge trapping flash memory array in accordance with an embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS A circuit diagram of a second method of operation for staging, undividing, and term taking power to capture a flash memory ramp in accordance with one embodiment of the present invention. FIG. 4 is an embodiment of the present invention. A flowchart of a process of performing a first method of operation. / Figure 5 is a flowchart of a process of performing a second method of operation according to an embodiment of the present invention. μ / [Major component symbol description] 100 ·• Structure 110, 170 171, 172, 173: polycrystalline germanium layer 120: oxide-nitride-oxide thin film 130: source region 140: drain region 19 B〇i3ja5 16402twf.doc/006 150, 180, 18b 182, 183, 184 210: Si-: FIN layer 160: arrays 200, 330: erase operation 2 (Π, 202, 203, 204, 205, 206, 207, 301, 302, 303, 304, 305, 306, 307: gate 203-1, 303-1: 203-r, 303-r on the left side: 220 on the right side: oxide layer 230: 矽 240, 300: stylized operation 260, 360: read operation 400: first operation method 410 to 430: step 500: second operation method 510 to 530 · · steps

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Claims (1)

13〇13为015 16402twf.doc/006 X. Patent application scope: 1. A flash memory array comprising: · a first charge trapping memory unit having a gate electrode covering the first charge trapping film, undoped a second source region and an undoped drain region; a second charge trapping memory unit disposed adjacent to a first side of the first memory unit, the first memory unit having a cover; a gate electrode of the film, an undoped source region, and an undoped drain region; a second charge trapping memory cell disposed adjacent to a second side of the first memory cell, the third memory The cell has a gate electrode covering the third charge trapping film, an undoped source region, and an undoped gate region; and the flap layer 'passing the first charge trapping memory unit, the second = She remembers the unit and the (four) three electric system to capture the orthogonal extension of memory. The flash memory array of claim 1, wherein the gate _ pole of the memory unit generates an inversion region or a drain region for transmitting the first voltage to The first side of the memory-capturing memory unit.寻,中户:=, the inter-electrode electrode of the hidden unit generates reversal: the first or the bungee region is used to apply the patent for the second (four) transfer scraper The array of the body described in the third item, into the 21 • 1301319 P940015 16402twfl .doc / d production of the month ~ day repair A ° replacement 骂 including the 邑 edge layer of the said - charge trap memory unit of the gate The third portion of the insulating layer covers the second portion of the insulating layer, the gate electrode of the second charge trapping k-body unit covers the second portion of the insulating layer, and the third portion of the insulating material The flash memory array of the first aspect of the invention, wherein the first-to-doped region includes an undoped source region. 6. The flash memory array of claim 2, wherein the second undoped region comprises an undoped drain region. 7 - a plurality of charges for operation a method of capturing a morphological array of memory cells, wherein the plurality of charge trapping memory cells are (4) The Shixi layer intersects with the N-wing layer, each row has a town memory unit, and the flap layer extends over the plurality of charge trapping memory units. Each charge trapping memory unit has an overlay charge trap. The memory pole array, the undoped source region, and the undoped drain region of the film, the memory array method for having a plurality of charge trapping memory cells comprises: a charge trapping memory in a row In the body unit, the selected gate electrode is erased by using a Rayleigh-Noltheim-type tunneling erase; the selected gate is programmed by using a hot hole injection' The gate electrode covers the charge trapping film with the first position on the left side and the second position on the right side, and the first set of remaining gate electrodes are located in the selected gate electrode in the row memory unit On the first side, as the transfer terminal for transferring the first stylized voltage to the selected gate 22(S) 13013 said 15 16402twf.doc/006 pole electrode ^ ^ ^ Located in the line, master On the gate electrode side of the _T, as the use; the pass polarity of the second pole electrode of the === (four) electrode = to the selected gate, the second gate = the selected gate electrode a bit to perform a read operation on the selected gate electrode. 8. A method of applying a plurality of electric premature & memory breaks as claimed in the application for full-time (4) 7 items, Each of the 'group gate electrodes generates a first-inverted region that is tangential to the source region of the first stylized lamella or the > and the polar region. The method for operating a ticker having a plurality of electrical capture δ & early %, wherein each of the remaining gate electrodes of the two sets of nozzles produces a second inversion A region, the first: inversion region acts as a source region or a drain region for transferring the second stylized voltage. 10. The method for operating a memory having a plurality of charge trapping unit units as recited in claim 7, wherein the towel is passed through a Rayleigh-Noltheim-type wipe-off The first bit on the left side and the second bit on the right side are erased to a high state. 11. A method of operating a memory array having a plurality of charge trapping memory cells as described in claim 1G, comprising: applying a first voltage of about 15 volts to said left side First bit, and applying a second voltage of about zero volts to the second bit on the right side, and reading 23 13013 saying that 01 5 16402 twf.doc/006 takes the right side of the starting voltage The second place. A method for operating a memory array having a plurality of electrical capture memory cells, as described in claim 10, comprising: applying a first voltage of about one volt to the first of the left side - And a second voltage of ^1^5 volts is applied to the second bit of the right side and δ is taken to the first bit on the left side having a starting voltage. A method for operating a memory having a plurality of electrical: capture memory cells, wherein the gate electrodes are in a charged state, as described in claim 7 of the patent application. ^ The method for operating a recording core having a plurality of electric capturing regions, as described in the seventh paragraph of the patent application (4), wherein the selected gate electrode is in a non-charging state. k a = as described in claim 7 of the scope of the patent for operating a memory array (four) with a plurality of electric capture and warfare singles, ^ as described in the scope of the patent The method of the memory array, wherein the charge trapping on the right side of the thin film on the right side of the film is captured by the thermoelectric hole. The memory array applies a second voltage of the first light-applied rider on the left side of the 骑=_^= 骑 to the 24 13 01 view 5 ^ 6402 twf.doc associated with the selected interpole electrode /006 the second bit on the right side of the charge trapping film; and the stylized side having a low Vt starting voltage. Drinking ^ + = as described in claim 16 has a method of capturing a memory array of a memory cell, comprising: adding the said electric power to the said left side The bit, the voltage of two 1:5 volts is applied to the said . . . on the right side, δ buys the unprogrammed side with a high starting voltage. σ μΓ·-cutting operation has multiple charges The method of capturing the $= column of the memory unit's multiple charge-trapping memory cells is constructed by crossing the ί:shi shi Shiyi-wing layer, each row having multiple memories 二十 二十 * * 片 片 片 片The plurality of charge trapping memory units and the 'mother charge trapping memory unit having a gate charge trapping the second one of the methods of operating the memory having a plurality of electric trapping bodies 70 are: Hole injection to the row capture line erasing step in a row of charge trapping memory cells. The selected pole electrode of the selected pole covering electrical device is located at 5 and β is the selected gate. The left gate of the electrode is transferred == the interpole electrode is located in the row memory The second side of the gate electrode Η 丨 丨 丨 丨 丨 丨 丨 丨 右 右 右 右 右 右 右 右 右 右 右 右 右 右 右 右 右 右 右 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 .doc/006: the selected gate of the memory material is programmed to step by step, and the gate electrode is selected in the left position = the second Γ 'the first, ^ The first ^' of the selected gate electrode in the prosthesis 70 is operated as a transfer interpole for transmitting the first stylized voltage to the left bit of the selected gate The selected set of gate electrodes in the row of memory cells in the second group ==: as the electrode for transferring the second stylized voltage to the The pass gate of the right bit operates the bit in the selected gate electrode to perform a read operation on the gate electrode selected by the pin. 2. The method for operating a record dragon having a plurality of units of the capture unit (4) as described in claim 15 of the patent scope, wherein the towel is in the process of step 1 Each of the gate electrodes generates a first-inverted region that serves as a source region or a drain region for transferring the first stylized voltage. A method according to claim 20, wherein the lining operation has a plurality of methods of capturing the memory _ of the memory unit, wherein during the stylization, the remaining of the second group Each of the gate electrodes has a uniform inversion region, and the second inversion region serves as a source region or a drain region for transferring the two stylized voltages. The method for operating a memory array having a plurality of charge trapping memory cells as described in claim 21, wherein during the erasing step, the first set of remaining gates Each of the electrodes is 26 16402 twf.doc/006 to generate a third inversion region, which serves as a source region or a drain region for transmitting the first erase voltage. 23. The method of operating a memory array having a plurality of charge trapping memory cells, as recited in claim 22, wherein said second set of remaining gate electrodes during said stylizing step Each of the four inversion regions is generated as a source region or a drain region for transferring the second erase voltage. 24. The method for operating a memory array having a plurality of charge trapping memory cells as recited in claim 19, wherein said first bit on said left side and said said right side The second bit is erased to a low state. y, as described in the 专利 月 专利 专利 专利 帛 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 And about zero volts to the second bit on the right side; and reading the second bit on the right side with a low undershoot. 26. A method for a memory array for a meta as described in claim 25, wherein: "electric b is added to said first bit on said left side, and electric dragon is applied to said right The second bit on the side takes the first bit on the left side of the right low starting voltage. Jing/, has a charge "on the first bit or the right side of the operation having a plurality of instances The said ==; 27 B〇im5 16402twf.doc/006 is converted to a 'high state.' 28. The memory transfer with a plurality of charge trapping memory elements is described in the patent claim f27 (4) The method comprising: using the spur hot electrons to perform the stylization of the right side of the charge trapping film, a voltage of about 1.5 volts applied to the first bit on the left side and about zero volts The voltage is applied to the (four) bit on the right side and the stylized side with a high starting voltage. #29· as described in claim 28, for operating a multi-capacitor memory cell a method of memory_, comprising: said said charge trapping film by making a trench I", electrons The side performing the structuring step of applying a voltage of about zero volts to the first bit on the left side and applying a voltage of about 1.5 volts to the first bit on the right side; The unprogrammed side of the low starting voltage. The method for operating a memory _ having a plurality of charge trapping memory cells as described in claim 19, wherein the selected gate electrode is in a charged state. The method for operating a memory array having a plurality of charge trapping memory cells, as described in claim 19, wherein the selected gate electrode is in a non-charging state. 32. A memory cell structure comprising: a charge trapping structure; a polysilicon layer overlying the charge trapping structure; a flap layer extending substantially orthogonally relative to the polysilicon layer; a first undoped region extending The first 28 13 〇 13 to the charge trapping structure is 015 16402 twf. doc / 006 side; and the second undoped region extends to the second side of the charge trapping structure. 33. The memory cell structure of claim 32, wherein the charge trapping structure comprises an oxide-charge-oxide film. 29