TWI394369B - Circuit for improving sequence - Google Patents
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- TWI394369B TWI394369B TW95148499A TW95148499A TWI394369B TW I394369 B TWI394369 B TW I394369B TW 95148499 A TW95148499 A TW 95148499A TW 95148499 A TW95148499 A TW 95148499A TW I394369 B TWI394369 B TW I394369B
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Description
本發明涉及一種時序改善電路，尤指一種可使主機板上晶片組輸出控制電腦休眠狀態之信號時序與輸入輸出控制晶片內控制電腦休眠狀態信號時序一致之時序改善電路。 The invention relates to a timing improvement circuit, in particular to a timing improvement circuit which can make the signal timing of the chipset output control computer sleep state on the main board and the timing of controlling the sleep state of the computer in the input/output control chip.
晶片組係主機板之重要組成部分，幾乎影響著主機板之全部功能。當電腦進入休眠狀態時，要求晶片組輸出控制休眠狀態之信號時序與輸入輸出控制晶片中控制休眠狀態之信號時序相一致，然而，由於生產晶片組之廠商與生產輸入輸出控制晶片之廠商會不同，難免存在主機板上晶片組之信號時序與輸入輸出控制晶片之信號時序不能相容之狀況，而影響電腦正常運行。 The chipset is an important part of the motherboard, which affects almost all the functions of the motherboard. When the computer enters the sleep state, the signal timing of the chipset output control sleep state is consistent with the signal timing of controlling the sleep state in the input/output control chip. However, since the manufacturer of the chipset is different from the manufacturer who manufactures the input/output control chip. It is inevitable that the signal timing of the chipset on the motherboard is incompatible with the signal timing of the input/output control chip, which affects the normal operation of the computer.
鑒於以上內容，有必要提供一種可使主機板上晶片組輸出控制電腦休眠狀態之信號時序與輸入輸出控制晶片內控制休眠狀態之信號時序一致之時序改善電路。 In view of the above, it is necessary to provide a timing improvement circuit that can make the signal timing of the chipset output control computer sleep state on the motherboard and the signal timing of the input and output control wafer control sleep state.
一種時序改善電路，可將一晶片組輸出控制電腦休眠狀態之控制信號轉換為與一輸入輸出控制晶片中用於控制電腦休眠狀態之第一休眠狀態控制信號及第二休眠狀態控制信號時序一致之信號，該時序改善電路包括一控制電路及一開關電路，該控制電路包括一高電位導通、低電位截止之第一開關元件及一高電位導通、低電位截止之第二開關元件，該第一開關元件之 輸入端與一節點相連，該節點電壓在開機時為高電位，關機及休眠時為低電位，該第一開關元件之輸出端分別與該晶片組輸出之控制信號端及該第二開關元件之輸入端相連，該第二開關元件之輸出端與該輸入輸出控制晶片相連，該開關電路之輸入端與該節點相連，該開關電路之輸出端與該輸入輸出控制晶片相連並輸出一開機時為高電位、關機與休眠時為低電位之信號至該輸入輸出控制晶片。 A timing improving circuit capable of converting a control signal of a chipset output control computer sleep state into a timing corresponding to a first sleep state control signal and a second sleep state control signal for controlling a sleep state of an IC in an input/output control chip The timing improvement circuit includes a control circuit and a switch circuit, the control circuit includes a high potential conduction, a low potential cut-off first switching element, and a high potential conduction, low potential cut-off second switching element, the first Switching element The input end is connected to a node, the node voltage is high at the time of starting, and is low at the time of shutdown and sleep, and the output end of the first switching element is respectively connected to the control signal end and the second switching element outputted by the chip set The input end is connected, the output end of the second switching element is connected to the input/output control chip, the input end of the switch circuit is connected to the node, and the output end of the switch circuit is connected to the input/output control chip and outputs a power-on A signal of low potential at high potential, shutdown, and sleep to the input and output control chip.
相對習知技術，本發明時序改善電路借助該主機板輔助電源端、該電源輸入端及該電源啟動信號端，將晶片組輸出之用於控制電腦休眠狀態之控制信號轉換為與輸入輸出控制晶片內用於控制電腦休眠狀態之第一休眠狀態控制信號及第二休眠狀態控制信號時序一致之兩信號，使該晶片組與該輸入輸出控制晶片之信號時序相容，保證電腦能夠正常運行。 Compared with the prior art, the timing improvement circuit of the present invention converts the control signal outputted by the chipset for controlling the sleep state of the computer into the input and output control chip by means of the auxiliary power supply end of the motherboard, the power input end and the power start signal end. The two signals for controlling the sleep state of the first sleep state control signal and the second sleep state control signal of the computer sleep state are compatible with the signal timing of the chip set and the input/output control chip to ensure normal operation of the computer.
10‧‧‧輸入輸出控制晶片 10‧‧‧Input and output control chip
11‧‧‧節點 11‧‧‧ nodes
20‧‧‧比較器 20‧‧‧ comparator
21‧‧‧節點 21‧‧‧ nodes
23‧‧‧節點 23‧‧‧ nodes
30‧‧‧開關電路 30‧‧‧Switch circuit
31‧‧‧信號 31‧‧‧ signal
50‧‧‧控制電路 50‧‧‧Control circuit
51‧‧‧信號 51‧‧‧ signal
100‧‧‧主機板輔助電源端 100‧‧‧ motherboard auxiliary power supply
300‧‧‧電源輸入端 300‧‧‧Power input
500‧‧‧電源啟動信號端 500‧‧‧Power start signal terminal
700‧‧‧電源供電端 700‧‧‧Power supply terminal
R1‧‧‧電阻 R1‧‧‧ resistance
R2‧‧‧電阻 R2‧‧‧ resistance
R3‧‧‧電阻 R3‧‧‧ resistance
R4‧‧‧電阻 R4‧‧‧ resistance
R5‧‧‧電阻 R5‧‧‧ resistance
R6‧‧‧電阻 R6‧‧‧ resistance
R7‧‧‧電阻 R7‧‧‧ resistance
R8‧‧‧電阻 R8‧‧‧ resistance
R9‧‧‧電阻 R9‧‧‧ resistance
C1‧‧‧電容 C1‧‧‧ capacitor
C2‧‧‧電容 C2‧‧‧ capacitor
Q1‧‧‧第一場效應電晶體 Q1‧‧‧First field effect transistor
Q2‧‧‧第二場效應電晶體 Q2‧‧‧Second field effect transistor
Q3‧‧‧第三場效應電晶體 Q3‧‧‧ third field effect transistor
Q4‧‧‧場效應電晶體 Q4‧‧‧ Field Effect Transistor
Q5‧‧‧電晶體 Q5‧‧‧Optoelectronics
S3‧‧‧第一休眠狀態控制信號 S3‧‧‧First sleep state control signal
S4‧‧‧第二休眠狀態控制信號 S4‧‧‧Second sleep state control signal
S3’‧‧‧控制信號 S3’‧‧‧ control signal
圖1為本發明時序改善電路較佳實施方式之電路圖。 1 is a circuit diagram of a preferred embodiment of a timing improvement circuit of the present invention.
圖2為圖1中輸入輸出控制晶片之信號時序圖。 2 is a signal timing diagram of the input/output control chip of FIG. 1.
圖3為一晶片組輸出之控制信號時序圖。 Figure 3 is a timing diagram of control signals for a chipset output.
請參閱圖1，本發明時序改善電路用於當電腦進入休眠狀態時，可將一晶片組輸出之用於控制電腦休眠狀態之控制信號S3’轉換為一信號31及一信號51，使該兩信號31、51與一輸入輸出控制晶片10內之第一休眠狀態控制信號S3及第二休眠狀態控制信號S4之時序一致。該第一休眠狀態控制信號S3用於將電腦運行之程式保存於記憶體中，其在電腦關機時處於低電位，開機時處於高電位，第一休眠狀態及第二休眠狀態時處於低電位；該第二休眠狀態控制信號S4用於將電腦運行之程式保存於硬碟機中，其在電腦關機時處於低電位，開機及第一休眠狀態時處於高電位，第二休眠狀態時處於 低電位；該控制信號S3’在電腦關機及開機時處於高電位，第一休眠狀態時處於低電位，第二休眠狀態時處於高電位。 Referring to FIG. 1, the timing improvement circuit of the present invention is configured to convert a control signal S3' outputted by a chipset for controlling a sleep state of a computer into a signal 31 and a signal 51 when the computer enters a sleep state, so that the two The signals 31, 51 coincide with the timing of the first sleep state control signal S3 and the second sleep state control signal S4 in the input and output control wafer 10. The first sleep state control signal S3 is used to save the program running in the computer in the memory, which is at a low level when the computer is turned off, at a high level when the computer is turned on, and at a low level when the first sleep state and the second sleep state are; The second sleep state control signal S4 is used to save the program running on the computer in the hard disk drive, which is at a low level when the computer is turned off, at a high level when the computer is turned on and in the first sleep state, and at a high state when the second sleep state is present. Low potential; the control signal S3' is at a high potential when the computer is turned off and on, and is at a low potential in the first sleep state and at a high potential in the second sleep state.
該時序改善電路包括一主機板輔助電源端100、一電源輸入端300、一電源啟動信號端500、一比較器20、一開關元件、一開關電路30、一控制電路50及該控制信號S3’輸入端。該控制電路50包括一高電位導通、低電位截止之第一開關元件及一高電位導通、低電位截止之第二開關元件，該開關電路30包括一第三開關元件及一第四開關元件。在本實施方式中，該開關元件為一第一場效應電晶體Q1，該第一開關元件及該第二開關元件為一場效應電晶體Q4及一電晶體Q5，該第一開關元件之輸入端及輸出端分別為該場效應電晶體Q4之閘極及汲極，該第二開關元件之輸入端及輸出端分別為該電晶體Q5之基極及集極，第三開關元件及第四開關元件分別為一第二場效應電晶體Q2及一第三場效應電晶體Q3。 The timing improvement circuit includes a motherboard auxiliary power terminal 100, a power input terminal 300, a power enable signal terminal 500, a comparator 20, a switching component, a switch circuit 30, a control circuit 50, and the control signal S3'. Input. The control circuit 50 includes a high-potential on-time, low-potential cut-off first switching element and a high-potential on-time, low-potential-off second switching element. The switch circuit 30 includes a third switching element and a fourth switching element. In this embodiment, the switching element is a first field effect transistor Q1, and the first switching element and the second switching element are a field effect transistor Q4 and a transistor Q5, and the input end of the first switching element And the output terminals are respectively the gate and the drain of the field effect transistor Q4, and the input end and the output end of the second switching element are respectively the base and the collector of the transistor Q5, and the third switching element and the fourth switch The components are a second field effect transistor Q2 and a third field effect transistor Q3, respectively.
該主機板輔助電源端100與一電阻R2之一端相連，該電阻R2之另一端藉由一節點21與比較器20之反向輸入端相連，該電源輸入端300與一電阻R3之一端相連，該電阻R3之另一端藉由一節點23與比較器20之正向輸入端相連，該節點21藉由一電阻R1接地，該節點23藉由一電阻R4接地，該節點23還藉由一電容C1接地。該比較器20之其中一端接一電源供電端700，一端接地，其輸出端藉由一節點11連接該第一場效應電晶體Q1之汲極，該第一場效應電晶體Q1之閘極與該電源啟動信號端500相連，其閘極還藉由一電容C2接地，其源極接地。該節點11藉由一電阻R5與該電源供電端700相連，該節點11與該開關電路30中第二場效應電晶體Q2之閘極相連，該第二場效應電晶體Q2之汲極藉由一電阻R6連接該電源供電端700，其源極接地。該第三場效應電晶體Q3之閘極與該第二場效應電晶體Q2之汲極相連，該第三場效應電晶體Q3之汲極藉由一電阻R7連接該電源供電端700，其源極接地 。該第三場效應電晶體Q3之汲極即該信號31之輸出端與該輸入輸出控制晶片10之第一休眠狀態控制信號S3端相連。 The auxiliary power terminal 100 of the motherboard is connected to one end of a resistor R2. The other end of the resistor R2 is connected to the inverting input terminal of the comparator 20 via a node 21, and the power input terminal 300 is connected to one end of a resistor R3. The other end of the resistor R3 is connected to the forward input terminal of the comparator 20 via a node 23. The node 21 is grounded via a resistor R1. The node 23 is grounded via a resistor R4. The node 23 also has a capacitor. C1 is grounded. One end of the comparator 20 is connected to a power supply terminal 700, one end is grounded, and the output end thereof is connected to the drain of the first field effect transistor Q1 by a node 11, and the gate of the first field effect transistor Q1 is The power-on signal terminal 500 is connected, and its gate is also grounded by a capacitor C2, and its source is grounded. The node 11 is connected to the power supply terminal 700 via a resistor R5. The node 11 is connected to the gate of the second field effect transistor Q2 of the switch circuit 30. The drain of the second field effect transistor Q2 is A resistor R6 is connected to the power supply terminal 700, and its source is grounded. The gate of the third field effect transistor Q3 is connected to the drain of the second field effect transistor Q2, and the drain of the third field effect transistor Q3 is connected to the power supply terminal 700 by a resistor R7. Polar ground . The drain of the third field effect transistor Q3, that is, the output of the signal 31 is connected to the first sleep state control signal S3 of the input/output control wafer 10.
該控制信號S3’端藉由一電阻R8與該控制電路50中場效應電晶體Q4之汲極相連，該場效應電晶體Q4之閘極連接該節點11，其源極接地。該電晶體Q5之基極與該場效應電晶體Q4之汲極相連，該電晶體Q5之集極藉由一電阻R9連接該電源供電端，其射極接地。該電晶體Q5之集極即該信號51之輸出端與該輸入輸出控制晶片10之第二休眠狀態控制信號S4端相連。 The control signal S3' is connected to the drain of the field effect transistor Q4 of the control circuit 50 by a resistor R8. The gate of the field effect transistor Q4 is connected to the node 11, and its source is grounded. The base of the transistor Q5 is connected to the drain of the field effect transistor Q4. The collector of the transistor Q5 is connected to the power supply terminal by a resistor R9, and the emitter is grounded. The collector of the transistor Q5, that is, the output of the signal 51 is connected to the second sleep state control signal S4 of the input/output control wafer 10.
請參閱圖2，圖2為該輸入輸出控制晶片10中第一休眠狀態控制信號S3及第二休眠狀態控制信號S4之時序圖。當電腦處於關機狀態時，該第一休眠狀態控制信號S3及該第二休眠狀態控制信號S4均為低電位；當電腦開機後，該第一休眠狀態控制信號S3及該第二休眠狀態控制信號S4變為高電位；當電腦進入第一休眠狀態時，該第一休眠狀態控制信號S3變為低電位，該第二休眠狀態控制信號S4仍然保持高電位；當電腦進入第二休眠狀態時，該第一休眠狀態控制信號S3保持低電位不變，該第二休眠狀態控制信號S4變為低電位。 Please refer to FIG. 2. FIG. 2 is a timing diagram of the first sleep state control signal S3 and the second sleep state control signal S4 in the input/output control wafer 10. When the computer is in the off state, the first sleep state control signal S3 and the second sleep state control signal S4 are both low; when the computer is turned on, the first sleep state control signal S3 and the second sleep state control signal S4 becomes high; when the computer enters the first sleep state, the first sleep state control signal S3 becomes low, and the second sleep state control signal S4 remains high; when the computer enters the second sleep state, The first sleep state control signal S3 remains at a low potential, and the second sleep state control signal S4 becomes a low potential.
請繼續參閱圖3，圖3為該晶片組輸出之控制信號S3’時序圖，當電腦處於關機狀態時，該控制信號S3’為高電位；當電腦開機後，該控制信號S3’保持高電位不變；當電腦進入第一休眠狀態時，該控制信號S3’變為低電位；當電腦進入第二休眠狀態時，該控制信號S3’變為高電位。 Please continue to refer to FIG. 3. FIG. 3 is a timing diagram of the control signal S3' outputted by the chip set. When the computer is in the off state, the control signal S3' is high; when the computer is turned on, the control signal S3' remains high. The control signal S3' becomes low when the computer enters the first sleep state; when the computer enters the second sleep state, the control signal S3' becomes high.
下面詳細介紹本發明時序改善電路之工作過程。 The operation of the timing improvement circuit of the present invention will be described in detail below.
該主機板輔助電源端100輸入+5V電壓至主機板，用於給主機板上元件供電，該電源輸入端300輸入+12V主電壓供電腦運行，當關機時，該主機板輔助電源端100及該電源輸入端300均為低電位輸入，因此該節點11之電壓為 一低電位，只有當開機時，待該節點23之電壓高於該節點21之電壓時，該節點11之電壓才為一高電位。該電源啟動信號端500之信號為一低電位有效信號，即當電腦處於開機狀態時，該電源啟動信號端500為一低電位輸入，當電腦處於關機及休眠狀態時，該電源啟動信號端500為一高電位輸入。 The auxiliary power terminal 100 of the motherboard inputs a voltage of +5V to the motherboard, and is used for supplying power to components on the motherboard. The power input terminal 300 inputs a +12V main voltage for the computer to operate. When the power is turned off, the motherboard auxiliary power terminal 100 and The power input terminal 300 is a low potential input, so the voltage of the node 11 is A low potential, only when the voltage of the node 23 is higher than the voltage of the node 21 when the power is turned on, the voltage of the node 11 is a high potential. The signal of the power-on signal terminal 500 is a low-potential effective signal, that is, when the computer is in the power-on state, the power-on signal terminal 500 is a low-potential input, and when the computer is in the shutdown state and the sleep state, the power-on signal terminal 500 For a high potential input.
當電腦處於關機狀態時，該電源啟動信號端500為一高電位輸入，該第一場效應電晶體Q1導通，其汲極輸出低電位，因此該節點11之電壓為一低電位，該第二場效應電晶體Q2截止，其汲極輸出高電位至該第三場效應電晶體Q3之閘極，該第三場效應電晶體Q3導通，其汲極輸出低電位，即該信號31為一低電位；該控制信號S3’為一高電位，該節點11之電壓為一低電位，該場效應電晶體Q4截止，其汲極輸出一高電位至該晶體管Q5之基極，因此該電晶體Q5導通，其集極輸出低電位，即該信號51為一低電位。 When the computer is in the off state, the power start signal terminal 500 is a high potential input, the first field effect transistor Q1 is turned on, and the drain output thereof is low, so the voltage of the node 11 is a low potential, the second The field effect transistor Q2 is turned off, and its drain outputs a high potential to the gate of the third field effect transistor Q3. The third field effect transistor Q3 is turned on, and its drain output is low, that is, the signal 31 is low. Potential; the control signal S3' is a high potential, the voltage of the node 11 is a low potential, the field effect transistor Q4 is turned off, and the drain thereof outputs a high potential to the base of the transistor Q5, so the transistor Q5 Turned on, its collector output is low, that is, the signal 51 is a low potential.
當電腦處於開機狀態時，該主機板輔助電源端100及該電源輸入端300均為高電位輸入，該電源啟動信號端500為一低電位輸入，當該節點23之電壓高於該節點21之電壓時，該比較器20輸出一高電位，即該節點11之電壓為一高電位，由於該第一場效應電晶體Q1截止，該節點11之高電位輸入至該第二場效應電晶體Q2之閘極，該第二場效應電晶體Q2導通，其汲極輸出低電位至該第三場效應電晶體Q3之閘極，該第三場效應電晶體Q3截止，其汲極輸出高電位，即該信號31為一高電位；由於該節點11之電壓為一高電位，因此該場效應電晶體Q4導通，其汲極輸出低電位至該電晶體Q5之基極，該電晶體Q5截止，其集極輸出高電位，即該信號51為一高電位。 When the computer is in the power-on state, the motherboard auxiliary power terminal 100 and the power input terminal 300 are both high-potential inputs, and the power-on signal terminal 500 is a low-potential input. When the voltage of the node 23 is higher than the node 21 When the voltage is applied, the comparator 20 outputs a high potential, that is, the voltage of the node 11 is a high potential. Since the first field effect transistor Q1 is turned off, the high potential of the node 11 is input to the second field effect transistor Q2. a gate of the second field effect transistor Q2, the drain of which outputs a low potential to the gate of the third field effect transistor Q3, the third field effect transistor Q3 is turned off, and the drain of the third field effect transistor is high, That is, the signal 31 is a high potential; since the voltage of the node 11 is a high potential, the field effect transistor Q4 is turned on, and its drain output is low to the base of the transistor Q5, and the transistor Q5 is turned off. Its collector output is high, that is, the signal 51 is at a high potential.
當電腦處於第一休眠狀態時，該電源輸入端300輸入一低電位，該節點11之電壓為低電位，因此該第三場效應電晶體Q3之汲極輸出低電位，即該信號31為一低電位；由於該控制信號S3’為低電位，該電晶體Q5截止，其集極輸出高電位，即該信號51為一高電位。 When the computer is in the first sleep state, the power input terminal 300 inputs a low potential, and the voltage of the node 11 is low, so the drain of the third field effect transistor Q3 outputs a low potential, that is, the signal 31 is one. Low potential; since the control signal S3' is low, the transistor Q5 is turned off, and its collector output is high, that is, the signal 51 is at a high potential.
當電腦處於第二休眠狀態時，該電源輸入端300輸入一低電位，該節點11之電壓為低電位，因此該第三場效應電晶體Q3之汲極輸出低電位，即該信號31為一低電位；由於該控制信號S3’為高電位，且該場效應電晶體Q4截止，因此該電晶體Q5導通，其集極輸出低電位，即該信號51為一低電位。 When the computer is in the second sleep state, the power input terminal 300 inputs a low potential, and the voltage of the node 11 is low, so the drain output of the third field effect transistor Q3 is low, that is, the signal 31 is one. Low potential; since the control signal S3' is at a high potential and the field effect transistor Q4 is turned off, the transistor Q5 is turned on, and its collector output is low, that is, the signal 51 is at a low potential.
在本發明時序改善電路中，可藉由其他電路來實現該信號31之時序與該第一休眠狀態控制信號S3之時序一致。 In the timing improvement circuit of the present invention, the timing of the signal 31 can be synchronized with the timing of the first sleep state control signal S3 by other circuits.
本發明時序改善電路借助該主機板輔助電源端100、該電源輸入端300及該電源啟動信號端500，將晶片組輸出之控制信號S3’轉換為與該輸入輸出控制晶片10內用於控制電腦休眠狀態之第一休眠狀態控制信號S3及第二休眠狀態控制信號S4時序一致之兩信號31、51，使該晶片組與該輸入輸出控制晶片10之時序相容，則電腦能夠正常運行。 The timing improvement circuit of the present invention converts the control signal S3' outputted by the chipset into and out of the input/output control chip 10 by using the motherboard auxiliary power supply terminal 100, the power input terminal 300, and the power activation signal terminal 500. The two signals 31, 51 in which the first sleep state control signal S3 and the second sleep state control signal S4 in the sleep state coincide with each other, so that the timing of the chip set and the input/output control chip 10 are compatible, the computer can operate normally.
10‧‧‧輸入輸出控制晶片 10‧‧‧Input and output control chip
11‧‧‧節點 11‧‧‧ nodes
20‧‧‧比較器 20‧‧‧ comparator
21‧‧‧節點 21‧‧‧ nodes
23‧‧‧節點 23‧‧‧ nodes
30‧‧‧開關電路 30‧‧‧Switch circuit
31‧‧‧信號 31‧‧‧ signal
50‧‧‧控制電路 50‧‧‧Control circuit
51‧‧‧信號 51‧‧‧ signal
100‧‧‧主機板輔助電源端 100‧‧‧ motherboard auxiliary power supply
300‧‧‧電源輸入端 300‧‧‧Power input
500‧‧‧電源啟動信號端 500‧‧‧Power start signal terminal
700‧‧‧電源供電端 700‧‧‧Power supply terminal
R1‧‧‧電阻 R1‧‧‧ resistance
R2‧‧‧電阻 R2‧‧‧ resistance
R3‧‧‧電阻 R3‧‧‧ resistance
R4‧‧‧電阻 R4‧‧‧ resistance
R5‧‧‧電阻 R5‧‧‧ resistance
R6‧‧‧電阻 R6‧‧‧ resistance
R7‧‧‧電阻 R7‧‧‧ resistance
R8‧‧‧電阻 R8‧‧‧ resistance
R9‧‧‧電阻 R9‧‧‧ resistance
C1‧‧‧電容 C1‧‧‧ capacitor
C2‧‧‧電容 C2‧‧‧ capacitor
Q1‧‧‧第一場效應電晶體 Q1‧‧‧First field effect transistor
Q2‧‧‧第二場效應電晶體 Q2‧‧‧Second field effect transistor
Q3‧‧‧第三場效應電晶體 Q3‧‧‧ third field effect transistor
Q4‧‧‧場效應電晶體 Q4‧‧‧ Field Effect Transistor
Q5‧‧‧電晶體 Q5‧‧‧Optoelectronics
S3‧‧‧第一休眠狀態控制信號 S3‧‧‧First sleep state control signal
S4‧‧‧第二休眠狀態控制信號 S4‧‧‧Second sleep state control signal
S3’‧‧‧控制信號 S3’‧‧‧ control signal
Claims (7)
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| TW95148499A TWI394369B (en) | 2006-12-22 | 2006-12-22 | Circuit for improving sequence |
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| TW95148499A TWI394369B (en) | 2006-12-22 | 2006-12-22 | Circuit for improving sequence |
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| TW200828803A TW200828803A (en) | 2008-07-01 |
| TWI394369B true TWI394369B (en) | 2013-04-21 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5664204A (en) * | 1993-03-22 | 1997-09-02 | Lichen Wang | Apparatus and method for supplying power and wake-up signal using host port's signal lines of opposite polarities |
| TW498194B (en) * | 1999-11-05 | 2002-08-11 | Intel Corp | Sleep state transitioning |
| US6523128B1 (en) * | 1999-08-31 | 2003-02-18 | Intel Corporation | Controlling power for a sleeping state of a computer to prevent overloading of the stand-by power rails by selectively asserting a control signal |
| US6691238B1 (en) * | 1999-07-23 | 2004-02-10 | Intel Corporation | System for disabling remote wake events on a remote wake line that is coupled to a front panel switch wake line |
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2006
- 2006-12-22 TW TW95148499A patent/TWI394369B/en not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5664204A (en) * | 1993-03-22 | 1997-09-02 | Lichen Wang | Apparatus and method for supplying power and wake-up signal using host port's signal lines of opposite polarities |
| US6691238B1 (en) * | 1999-07-23 | 2004-02-10 | Intel Corporation | System for disabling remote wake events on a remote wake line that is coupled to a front panel switch wake line |
| US6523128B1 (en) * | 1999-08-31 | 2003-02-18 | Intel Corporation | Controlling power for a sleeping state of a computer to prevent overloading of the stand-by power rails by selectively asserting a control signal |
| TW498194B (en) * | 1999-11-05 | 2002-08-11 | Intel Corp | Sleep state transitioning |
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