[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

TWI393271B - Optoelectronic semiconductor device - Google Patents

Optoelectronic semiconductor device Download PDF

Info

Publication number
TWI393271B
TWI393271B TW98118503A TW98118503A TWI393271B TW I393271 B TWI393271 B TW I393271B TW 98118503 A TW98118503 A TW 98118503A TW 98118503 A TW98118503 A TW 98118503A TW I393271 B TWI393271 B TW I393271B
Authority
TW
Taiwan
Prior art keywords
electrical contact
semiconductor device
optoelectronic semiconductor
contact
layer
Prior art date
Application number
TW98118503A
Other languages
Chinese (zh)
Other versions
TW201013984A (en
Inventor
Chien Fu Shen
Chien Kai Chung
Schang Jing Hon
Hui Chen Yeh
Tsun Kai Ko
An Ju Lin
Chen Ou
Original Assignee
Epistar Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Epistar Corp filed Critical Epistar Corp
Priority to TW98118503A priority Critical patent/TWI393271B/en
Priority to US12/562,917 priority patent/US9508902B2/en
Publication of TW201013984A publication Critical patent/TW201013984A/en
Application granted granted Critical
Publication of TWI393271B publication Critical patent/TWI393271B/en
Priority to US15/256,263 priority patent/US9876146B2/en
Priority to US15/839,160 priority patent/US10529895B2/en

Links

Landscapes

  • Led Devices (AREA)

Description

光電半導體裝置Photoelectric semiconductor device

本發明係關於一種光電半導體裝置,尤其關於一種具有接觸層與不連續區之光電半導體裝置,以及與不連續區相關之圖案佈局。The present invention relates to an optoelectronic semiconductor device, and more particularly to an optoelectronic semiconductor device having a contact layer and a discontinuous region, and a pattern layout associated with the discontinuous region.

習知發光二亟體之一種結構係包含成長基板、n型半導體層、p型半導體層、與位於此二半導體層間之發光層。用以反射源自於發光層光線之反射層可選擇性地形成於此結構中。為提高發光二極體之光學、電學、及力學特性之至少其一,一種經適當選擇之材料會用以替代成長基板以作為承載除成長基板外之其他結構之載體,例如:金屬或矽可用於取代成長氮化物之藍寶石基板。成長基板可使用蝕刻、研磨、或雷射移除等方式移除。然而,成長基板亦可能被全部或僅部分保留並與載體結合。此外,透光氧化物亦可整合於發光二極體結構中以提升電流分散表現。A structure of a conventional light-emitting diode includes a growth substrate, an n-type semiconductor layer, a p-type semiconductor layer, and a light-emitting layer between the two semiconductor layers. A reflective layer for reflecting light from the luminescent layer is selectively formed in the structure. In order to improve at least one of the optical, electrical, and mechanical properties of the light-emitting diode, a suitably selected material may be used to replace the growth substrate as a carrier for carrying other structures other than the growth substrate, such as metal or germanium. Instead of growing a nitride sapphire substrate. The growth substrate can be removed using etching, grinding, or laser removal. However, the growth substrate may also be retained wholly or only partially and combined with the carrier. In addition, the light-transmissive oxide can also be integrated into the light-emitting diode structure to enhance the current dispersion performance.

本案申請人之第I237903號台灣專利中揭露一種高發光效率之發光元件100。如第1圖所示,發光元件100之結構包含藍寶石基板110、氮化物緩衝層120、n型氮化物半導體疊層130、氮化物多重量子井發光層140、p型氮化物半導體疊層150、及氧化物透明導電層160。另外,並在p型氮化物半導體疊層150面向氧化物透明導電層160之表面上形成六角錐孔穴構造1501。六角錐孔穴構造1501之內表面較易與如氧化銦錫(ITO)、氧化鎘錫、氧化銻錫、氧化銦鋅、氧化鋅鋁、與氧化鋅錫等之氧化物透明導電層160形成歐姆接觸。因此,發光元件100之順向電壓得以維持於一個較低的水準,且藉由六角錐孔穴構造1501也可提升光摘出效率。A high luminous efficiency light-emitting element 100 is disclosed in Taiwan Patent No. I237903. As shown in FIG. 1, the structure of the light-emitting element 100 includes a sapphire substrate 110, a nitride buffer layer 120, an n-type nitride semiconductor stack 130, a nitride multiple quantum well light-emitting layer 140, and a p-type nitride semiconductor stack 150. And an oxide transparent conductive layer 160. Further, a hexagonal taper hole structure 1501 is formed on the surface of the p-type nitride semiconductor layer 150 facing the oxide transparent conductive layer 160. The inner surface of the hexagonal taper hole structure 1501 is apt to be in ohmic contact with the oxide transparent conductive layer 160 such as indium tin oxide (ITO), cadmium tin oxide, antimony tin oxide, indium zinc oxide, zinc aluminum oxide, and zinc tin oxide. . Therefore, the forward voltage of the light-emitting element 100 is maintained at a lower level, and the light extraction efficiency can also be improved by the hexagonal taper hole structure 1501.

ITO可藉由電子束蒸鍍法(Electron Beam Evaporation)或濺鍍法(Sputtering)形成於六角錐孔穴構造1501、半導體層或其二者之上。不同製造方式所形成之ITO層所表現出之光學、電學特性、或其二者也可能不盡相同,相關文獻可參閱本案申請人之第096111705號台灣專利申請案,並援引其為本申請案之一部份。於掃描式電子顯微鏡(Scanning Electron Microscope;SEM)之下,以電子束蒸鍍法形成之ITO顆粒1601並未完全填滿六角錐孔穴構造1501,而呈現出諸多存在於ITO顆粒間之空隙,如第2圖所示。此些空隙可能使光線被侷限其中無法脫離發光元件,而逐漸被周圍之ITO所吸收。或者因此些空隙中所存在具有小於ITO折射係數之介質,如空氣,使得進入ITO之光線會在材料邊界處遭遇全反射而無法離開ITO層,而逐漸為ITO所吸收。The ITO may be formed on the hexagonal taper hole structure 1501, the semiconductor layer, or both by electron beam evaporation (Sputtering) or sputtering. The optical, electrical properties, or both of the ITO layers formed by different manufacturing methods may also be different. For related documents, refer to the Taiwan Patent Application No. 096111705, which is hereby incorporated by reference. One part. Under the Scanning Electron Microscope (SEM), the ITO particles 1601 formed by electron beam evaporation method do not completely fill the hexagonal cone cavity structure 1501, and present a plurality of voids existing between the ITO particles, such as Figure 2 shows. These voids may cause light to be confined out of the illuminating element and gradually absorbed by the surrounding ITO. Or, therefore, a medium having a refractive index smaller than ITO, such as air, is present in the voids such that light entering the ITO encounters total reflection at the material boundary and cannot leave the ITO layer, but is gradually absorbed by the ITO.

由C.H.Kuo等於西元2004年在Materials Science and Engineering B所提出”Nitride-based near-ultraviolet LEDs with an ITO transparent contact”一文中曾針對ITO之穿透率(transmittance)與波長間之關係進行研究。其發現當波長約低於420nm時,ITO穿透率有急遽下降的趨勢,在350nm時甚至可能低於70%。對於藍光波段,ITO具有高於80%的穿透率,但是,在近紫外光或紫外光波段的穿透率卻不盡理想。The relationship between the transmittance and the wavelength of ITO has been studied by C.H. Kuo in the article "Nitride-based near-ultraviolet LEDs with an ITO transparent contact" proposed by Materials Science and Engineering B in 2004. It was found that when the wavelength is lower than about 420 nm, the ITO penetration rate tends to drop sharply, and may even be lower than 70% at 350 nm. For the blue light band, ITO has a transmittance higher than 80%, but the transmittance in the near ultraviolet or ultraviolet band is not ideal.

由是,ITO等透明氧化物作為半導體發光元件常用之材料,對於元件之光學與電學表現上仍有許多的改善空間。Therefore, transparent oxides such as ITO are commonly used as materials for semiconductor light-emitting elements, and there is still much room for improvement in optical and electrical performance of the elements.

依據本發明一實施例之一種光電半導體裝置包括一轉換部,包括一第一側;一電性接點;一接觸層,具有一外邊界;及至少連續三個不連續區,係沿外邊界形成,且具有至少一個不相同之要素;其中,電性接點、接觸層、及不連續區係形成於轉換部之第一側。An optoelectronic semiconductor device according to an embodiment of the invention includes a conversion portion including a first side; an electrical contact; a contact layer having an outer boundary; and at least three consecutive discontinuous regions along the outer boundary Forming, and having at least one different element; wherein the electrical contact, the contact layer, and the discontinuous region are formed on the first side of the conversion portion.

依據本發明之其他數實施例之光電半導體裝置揭露如下:光電半導體裝置中之要素包括角度、長度、寬度、深度、與間距其中之一。光電半導體裝置中之電性接點包括一根部、一支部、及一端部。光電半導體裝置中之電性接點包括一區域用以與一外部電路連接。光電半導體裝置中之電性接點與不連續區在一投影方向上具有至少一交點。An optoelectronic semiconductor device according to other embodiments of the present invention is disclosed as follows: The elements in the optoelectronic semiconductor device include one of an angle, a length, a width, a depth, and a pitch. The electrical contact in the optoelectronic semiconductor device includes a portion, a portion, and an end portion. The electrical contacts in the optoelectronic semiconductor device include an area for connection to an external circuit. The electrical contacts and discontinuous regions in the optoelectronic semiconductor device have at least one intersection in a projection direction.

光電半導體裝置更包括一電流阻障區,位於不連續區至少其一下方。光電半導體裝置中各不連續區在外邊界上僅具有一個開口。光電半導體裝置中不連續區包括至少一電流阻障區。The optoelectronic semiconductor device further includes a current blocking region located at least below one of the discontinuous regions. Each discontinuous region in the optoelectronic semiconductor device has only one opening on the outer boundary. The discontinuous region in the optoelectronic semiconductor device includes at least one current blocking region.

依據本發明另一實施例之一種光電半導體裝置包括一轉換部;一第一電性接點,係靠近轉換部;一第二電性接點,係與第一電性接點構成一電流通道之兩端;一接觸層,具有一外邊界;及複數個不連續區,係源自外邊界,並大體上符合電性接點之外型。An optoelectronic semiconductor device according to another embodiment of the present invention includes a conversion portion; a first electrical contact is adjacent to the conversion portion; and a second electrical contact is formed between the first electrical contact and the first electrical contact The two ends; a contact layer having an outer boundary; and a plurality of discontinuous regions originating from the outer boundary and substantially conforming to the electrical contact type.

依據本發明之其他數實施例之光電半導體裝置揭露如下:光電半導體裝置中各個不連續區與相鄰最近之電性接點間之間距大體上相同。光電半導體裝置中第一電性接點與第二電性接點可分別位於轉換部之相對側。光電半導體裝置中之第一電性接點與第二電性接點可位於轉換部之同側。光電半導體裝置更包括一歐姆接觸區,位於接觸層、不連續區、或其二者下方。An optoelectronic semiconductor device according to other embodiments of the present invention is disclosed as follows: the distance between each discontinuous region in the optoelectronic semiconductor device and the nearest nearest electrical contact is substantially the same. The first electrical contact and the second electrical contact in the optoelectronic semiconductor device are respectively located on opposite sides of the conversion portion. The first electrical contact and the second electrical contact in the optoelectronic semiconductor device may be located on the same side of the conversion portion. The optoelectronic semiconductor device further includes an ohmic contact region located under the contact layer, the discontinuous region, or both.

光電半導體裝置中不連續區中至少其一偏離一總體變化趨勢。光電半導體裝置中之第一電性接點與第二電性接點至少其一為左右對稱。光電半導體裝置中之不連續區中至少其二在外邊界上具有一共同開口。At least one of the discontinuous regions in the optoelectronic semiconductor device deviates from an overall trend. At least one of the first electrical contact and the second electrical contact in the optoelectronic semiconductor device is bilaterally symmetric. At least two of the discontinuous regions in the optoelectronic semiconductor device have a common opening on the outer boundary.

依據本發明又一實施例之一種光電半導體裝置包括一轉換部,包括一第一側;一電性接點,位於轉換部之第一側;一接觸層,具有一外邊界;及複數個不連續區,係由外邊界朝向電性接點,並在一個維度上呈現不規則變化。An optoelectronic semiconductor device according to still another embodiment of the present invention includes a conversion portion including a first side, an electrical contact on a first side of the conversion portion, a contact layer having an outer boundary, and a plurality of The contiguous zone is oriented from the outer boundary towards the electrical contact and exhibits an irregular change in one dimension.

依據本發明之其他數實施例之光電半導體裝置揭露如下:光電半導體裝置中之接觸層與不連續區位於電性接點與轉換部之間。光電半導體裝置中之不連區包括幾何、材料、物理特性、及化學特性中至少其一之不連續。光電半導體裝置更包括一歐姆接觸區,位於接觸層、不連續區、或其二者下方,並包括一凸起空間、凹陷空間、或其二者,此空間之幾何形狀係包括角錐、圓錐、與平頭截體中至少其一。The optoelectronic semiconductor device according to other embodiments of the present invention is disclosed as follows: The contact layer and the discontinuous region in the optoelectronic semiconductor device are located between the electrical contact and the conversion portion. The discontinuous region in the optoelectronic semiconductor device includes at least one of geometric, material, physical, and chemical properties that are discontinuous. The optoelectronic semiconductor device further includes an ohmic contact region located under the contact layer, the discontinuous region, or both, and includes a convex space, a recessed space, or both, and the geometry of the space includes a pyramid, a cone, At least one of the flat heads.

依據本發明一實施例之一種光電半導體裝置包括一基板,其面積係大於或等於45mil×45mil;一第一電性接點,包含:一第一根部,係與二或多個端部電性相連;及一第二根部,係與第一根部分離,且與二或多個端部電性相連;一第二電性接點,包含至少二個根部及數個端部;及一轉換部,係介於基板與第二電性接點之間;其中第一電性接點之任二個相鄰端部間係至少存在第二電性接點之數個端部之其一。An optoelectronic semiconductor device according to an embodiment of the invention includes a substrate having an area greater than or equal to 45 mils by 45 mils; a first electrical contact comprising: a first root portion and two or more end portions And a second root portion separated from the first root portion and electrically connected to the two or more ends; a second electrical contact comprising at least two root portions and a plurality of end portions; and a conversion portion And being between the substrate and the second electrical contact; wherein at least two of the ends of the second electrical contact are between the two adjacent ends of the first electrical contact.

此外,本發明之實施例亦揭露如下:第一電性接點之第一根部及第二根部係彼此相連。In addition, the embodiment of the present invention also discloses that the first root portion and the second root portion of the first electrical contact are connected to each other.

光電半導體裝置中之第一電性接點之第一根部及第二根部中至少其一係藉由至少一支部與多個端部中至少其一電性相連。At least one of the first root portion and the second root portion of the first electrical contact in the optoelectronic semiconductor device is electrically connected to at least one of the plurality of ends by at least one portion.

光電半導體裝置中之第二電性接點更包括一支部,係具有一第一端、一第二端、與一主幹,第一端係連接至二根部中至少其一,主幹係與數個端部中至少其一相連。The second electrical contact in the optoelectronic semiconductor device further includes a first portion, a first end, a second end, and a trunk, the first end is connected to at least one of the two portions, the backbone and the plurality At least one of the ends is connected.

光電半導體裝置更包括一電流阻障區,係位於第二電性接點之下。The optoelectronic semiconductor device further includes a current blocking region located below the second electrical contact.

光電半導體裝置更包括一平台,第一電性接點係形成於平台之上。The optoelectronic semiconductor device further includes a platform, and the first electrical contact is formed on the platform.

光電半導體裝置更包括一接觸層,係介於第二電性接點與轉換部之間,並包含一不連續區。The optoelectronic semiconductor device further includes a contact layer between the second electrical contact and the conversion portion and including a discontinuous region.

依據本發明又一實施例之一種電流通道,係提供電流通過一轉換部,包括一第一電性接點;及一第二電性接點,包含至少二個根部及數個端部;其中第一電性接點包括一第一根部,係與二或多個端部電性相連;及一第二根部,係與第一根部分離,且與二或多個端部電性相連;且第一電性接點之任二個相鄰端部間係至少存在第二電性接點之數個端部之其一。A current channel according to another embodiment of the present invention provides a current through a conversion portion, including a first electrical contact; and a second electrical contact, including at least two roots and a plurality of ends; The first electrical contact includes a first root electrically connected to the two or more ends; and a second root separated from the first root and electrically connected to the two or more ends; At least two of the ends of the second electrical contact are present between any two adjacent ends of the first electrical contact.

本發明之實施例亦揭露如下:電流通道中之轉換部係包含一第一面與一第二面,第一面係電性連接至第一電性接點,第二面係電性連接至第二電性接點。The embodiment of the present invention is also disclosed as follows: the conversion portion in the current channel includes a first surface and a second surface, the first surface is electrically connected to the first electrical contact, and the second surface is electrically connected to The second electrical contact.

電流通道中之第二電性接點之二個根部係彼此相連。The two roots of the second electrical contact in the current path are connected to each other.

以下配合圖式說明本發明之實施例。Embodiments of the invention are described below in conjunction with the drawings.

如第3圖所示之光電半導體裝置10包含一個形成於基板11上之半導體系統。半導體系統係包含可以進行或誘發光電能轉換之半導體元件、裝置、產品、電路、或應用。具體而言,半導體系統係包含發光二極體(Light-Emitting Diode;LED)、雷射二極體(Laser Diode;LD)、太陽能電池(Solar Cell)、液晶顯示器(Liquid Crystal Display)、有機發光二極體(Organic Light-Emitting Diode)中至少其一。於本說明書中「半導體系統」一詞並非限制該系統內所有次系統或單元皆以半導體材料製成,其他非半導體材料,例如:金屬、氧化物、絕緣體等皆可選擇性地整合於此半導體系統之中。The optoelectronic semiconductor device 10 as shown in FIG. 3 includes a semiconductor system formed on a substrate 11. Semiconductor systems include semiconductor components, devices, products, circuits, or applications that can perform or induce photovoltaic energy conversion. Specifically, the semiconductor system includes a light-emitting diode (LED), a laser diode (LD), a solar cell (Solar Cell), a liquid crystal display (Liquid Crystal Display), and an organic light emitting device. At least one of the Organic Light-Emitting Diodes. The term "semiconductor system" in this specification does not limit that all subsystems or units in the system are made of semiconductor materials. Other non-semiconductor materials such as metals, oxides, insulators, etc. can be selectively integrated into the semiconductor. In the system.

於本發明之一實施例中,半導體系統最少包含一第一電性層13、一轉換部14、以及一第二電性層15。第一電性層13及一第二電性層15係彼此中至少二個部分之電性、極性或摻雜物相異、或者係分別用以提供電子與電洞之材料單層或多層(「多層」係指二層或二層以上,以下同。)若第一電性層13及一第二電性層15係由半導導體材料構成,則其電性選擇可以為p型、n型、及i型中至少任意二者之組合。轉換部14係位於第一電性層13及第二電性層15之間,為電能與光能可能發生轉換或被誘發轉換之區域。電能轉變或誘發光能者係如發光二極體、液晶顯示器、有機發光二極體;光能轉變或誘發電能者係如太陽能電池、光電二極體。In one embodiment of the invention, the semiconductor system includes at least a first electrical layer 13, a conversion portion 14, and a second electrical layer 15. The first electrical layer 13 and the second electrical layer 15 are different in electrical, polarity or dopant of at least two of the two, or are used to provide a single layer or multiple layers of electrons and holes, respectively. "Multilayer" means two or more layers, the same applies below.) If the first electrical layer 13 and the second electrical layer 15 are composed of a semiconducting conductor material, the electrical selection may be p type, n A combination of at least any of the type and the i type. The conversion portion 14 is located between the first electrical layer 13 and the second electrical layer 15 and is a region where electrical energy and light energy may be converted or induced to be converted. Those who convert or induce light energy are such as light-emitting diodes, liquid crystal displays, and organic light-emitting diodes; those that convert or induce light energy are such as solar cells and photodiodes.

以發光二極體而言,轉換後光之發光頻譜可以藉由改變半導體系統中一層或多層之物理或化學配置進行調整。常用之材料係如磷化鋁鎵銦(AlGaInP)系列、氮化鋁鎵銦(AlGaInN)系列、氧化鋅(ZnO)系列等。轉換部14之結構係如:單異質結構(single heterostructure;SH)、雙異質結構(double heterostructure;DH)、雙側雙異質結構(double-side double heterostructure;DDH)、或多層量子井(multi-quantum well;MQW)。再者,調整量子井之對數亦可以改變發光波長。In the case of a light-emitting diode, the spectral spectrum of the converted light can be adjusted by changing the physical or chemical configuration of one or more layers in the semiconductor system. Commonly used materials are such as aluminum gallium indium phosphide (AlGaInP) series, aluminum gallium indium nitride (AlGaInN) series, zinc oxide (ZnO) series and the like. The structure of the conversion portion 14 is, for example, a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multi-layer quantum well (multi- Quantum well; MQW). Furthermore, adjusting the logarithm of the quantum well can also change the wavelength of the illumination.

基板11係用以成長或承載半導體系統,適用之材料係包含但不限於鍺(Ge)、砷化鎵(GaAs)、銦化磷(InP)、藍寶石(Sapphire)、碳化矽(SiC)、矽(Si)、鋁酸鋰(LiAlO2 )、氧化鋅(ZnO)、氮化鎵(GaN)、氮化鋁(AlN)、玻璃、複合材料(Composite)、鑽石、CVD鑽石、與類鑽碳(Diamond-Like Carbon;DLC)等。The substrate 11 is used to grow or carry a semiconductor system. Suitable materials include, but are not limited to, germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), sapphire, bismuth carbide (SiC), germanium. (Si), lithium aluminate (LiAlO 2 ), zinc oxide (ZnO), gallium nitride (GaN), aluminum nitride (AlN), glass, composite, diamond, CVD diamond, and diamond-like carbon ( Diamond-Like Carbon; DLC), etc.

基板11與半導體系統之間更可選擇性地包含一過渡層12。過渡層12係介於二種材料系統之間,使基板之材料系統”過渡”至半導體系統之材料系統。對發光二極體之結構而言,一方面,過渡層12係例如緩衝層(Buffer Layer)等用以降低二種材料間晶格不匹配之材料層。另一方面,過渡層12亦可以是用以結合二種材料或二個分離結構之單層、多層或結構,其可選用之材料係如:有機材料、無機材料、金屬、及半導體等;其可選用之結構係如:反射層、導熱層、導電層、歐姆接觸(ohmic contact)層、抗形變層、應力釋放(stress release)層、應力調整(stress adjustment)層、接合(bonding)層、波長轉換層、及機械固定構造等。A transition layer 12 is more selectively included between the substrate 11 and the semiconductor system. The transition layer 12 is interposed between the two material systems to "transition" the material system of the substrate to the material system of the semiconductor system. For the structure of the light-emitting diode, on the one hand, the transition layer 12 is a material layer such as a buffer layer or the like for reducing the lattice mismatch between the two materials. On the other hand, the transition layer 12 may also be a single layer, a plurality of layers or a structure for combining two materials or two separate structures, such as organic materials, inorganic materials, metals, and semiconductors; Optional structures such as: reflective layer, thermally conductive layer, conductive layer, ohmic contact layer, anti-deformation layer, stress release layer, stress adjustment layer, bonding layer, A wavelength conversion layer, a mechanical fixing structure, and the like.

第二電性層15上更可選擇性地形成一接觸層16。接觸層16係設置於第二電性層15遠離轉換部14之一側。具體而言,接觸層16可以為光學層、電學層、或其二者之組合。光學層係可以改變來自於或進入轉換部14的電磁輻射或光線。在此所稱之「改變」係指改變電磁輻射或光之至少一種光學特性,前述特性係包含但不限於頻率、波長、強度、通量、效率、色溫、演色性(rendering index)、光場(light field)、及可視角(angle of view)。電學層係可以使得接觸層16之任一組相對側間之電壓、電阻、電流、電容中至少其一之數值、密度、分布發生變化或有發生變化之趨勢。接觸層16之構成材料係包含氧化物、導電氧化物、透明氧化物、具有50%或以上穿透率之氧化物、金屬、相對透光金屬、具有50%或以上穿透率之金屬、有機質、無機質、螢光物、磷光物、陶瓷、半導體、摻雜之半導體、及無摻雜之半導體中至少其一。於某些應用中,接觸層16之材料係為氧化銦錫、氧化鎘錫、氧化銻錫、氧化銦鋅、氧化鋅鋁、與氧化鋅錫中至少其一。若為相對透光金屬,其厚度係約為0.005μm~0.6μm,或0.005μm~0.5μm,或0.005μm~0.4μm,或0.005μm~0.3μm,或0.005μm~0.2μm,或0.2μm~0.5μm,或0.3μm~0.5μm,或0.4μm~0.5μm,或0.2μm~0.4μm,或0.2μm~0.3μm。A contact layer 16 is more selectively formed on the second electrical layer 15. The contact layer 16 is disposed on a side of the second electrical layer 15 away from the conversion portion 14 . In particular, the contact layer 16 can be an optical layer, an electrical layer, or a combination of both. The optical layer can change the electromagnetic radiation or light from or into the conversion portion 14. As used herein, "change" means changing at least one optical property of electromagnetic radiation or light, including but not limited to frequency, wavelength, intensity, flux, efficiency, color temperature, rendering index, light field. (light field), and angle of view. The electrical layer may cause at least one of the voltage, resistance, current, and capacitance of the opposite side of the contact layer 16 to change or change in value, density, or distribution. The constituent material of the contact layer 16 comprises an oxide, a conductive oxide, a transparent oxide, an oxide having a transmittance of 50% or more, a metal, a relatively light-transmissive metal, a metal having a transmittance of 50% or more, an organic substance. At least one of inorganic, phosphor, phosphor, ceramic, semiconductor, doped semiconductor, and undoped semiconductor. In some applications, the material of the contact layer 16 is at least one of indium tin oxide, cadmium tin oxide, antimony tin oxide, indium zinc oxide, zinc aluminum oxide, and zinc tin oxide. In the case of a relatively light-transmissive metal, the thickness is about 0.005 μm to 0.6 μm, or 0.005 μm to 0.5 μm, or 0.005 μm to 0.4 μm, or 0.005 μm to 0.3 μm, or 0.005 μm to 0.2 μm, or 0.2 μm. 0.5 μm, or 0.3 μm to 0.5 μm, or 0.4 μm to 0.5 μm, or 0.2 μm to 0.4 μm, or 0.2 μm to 0.3 μm.

在某些情況下第二電性層15之上可以形成歐姆接觸區151。第二電性層15與接觸層16若經由歐姆接觸區151直接或間接接觸,其間可能形成歐姆接觸,或者使得光電半導體裝置10之驅動電壓(driving voltage)、臨限電壓(threshold voltage)及正向電壓(forward voltage)中至少其一下降。歐姆接觸區151之可能型態為凹陷或凸起。凹陷係如第3圖之歐姆接觸區151所例示;凸起係如第4圖之歐姆接觸區151所例示。凹陷空間之可能幾何形狀為角錐、圓錐、平頭截體、柱體、圓柱、半球形、不規則體或其任意組合。凸起之可能幾何形狀為角錐、圓錐、平頭截體、柱體、圓柱、半球形、不規則體或其任意組合。此外,歐姆接觸區151除如圖所示般係皆由單一或近似之凸起或凹陷所構成,但並未排除其亦可能由凸起與凹陷之組合所構成。於一特定實施例中,凸起、凹陷空間、或其二者係為六角錐。接觸層16與歐姆接觸區151相接觸之至少一部分係形成歐姆接觸。角錐上之斜面所具有之特定晶格方向或表面能態為造成歐姆接觸或較低位能障之可能原因之一。另一方面,第二電性層15表面上未形成歐姆接觸區151之部分與接觸層16間可能會形成較差之歐姆接觸、非歐姆接觸、或蕭基(Schottky)接觸,然而此部份與接觸層16間並不排除有形成歐姆接觸之可能。歐姆接觸區151之可能形成背景以及某些實施方式可參考本案申請人之第I237903號台灣專利,其並援引為本申請案之一部份。An ohmic contact region 151 may be formed over the second electrical layer 15 in some cases. When the second electrical layer 15 and the contact layer 16 are in direct or indirect contact via the ohmic contact region 151, an ohmic contact may be formed therebetween, or a driving voltage, a threshold voltage, and a positive voltage of the optoelectronic semiconductor device 10 may be formed. At least one of the forward voltage drops. The possible form of the ohmic contact region 151 is a depression or a bump. The recess is exemplified as the ohmic contact region 151 of Fig. 3; the bump is exemplified by the ohmic contact region 151 of Fig. 4. Possible geometries of the recessed space are pyramids, cones, truncated cones, cylinders, cylinders, hemispheres, irregularities or any combination thereof. Possible geometries of the protrusions are pyramids, cones, truncated cones, cylinders, cylinders, hemispheres, irregularities or any combination thereof. In addition, the ohmic contact regions 151 are formed of a single or similar protrusion or depression as shown, but are not excluded and may be composed of a combination of protrusions and depressions. In a particular embodiment, the raised, recessed spaces, or both are hexagonal cones. At least a portion of the contact layer 16 in contact with the ohmic contact region 151 forms an ohmic contact. The particular lattice direction or surface energy state of the bevel on the pyramid is one of the possible causes of ohmic contact or lower energy barrier. On the other hand, a portion of the surface of the second electrical layer 15 where the ohmic contact region 151 is not formed may form a poor ohmic contact, a non-ohmic contact, or a Schottky contact with the contact layer 16, however, this portion is The possibility of forming an ohmic contact is not excluded between the contact layers 16. The ohmic contact region 151 may form a background and some embodiments may be referred to the applicant's Taiwan Patent No. I237903, which is incorporated herein by reference.

除連續之單層或多層外,接觸層16可以為不連續或具有圖案之單層或多層。相關專利可參閱本案申請人之第096111705號台灣專利申請案,並援引其為本申請案之一部份。「不連續」係指幾何、材料、物理性質、及化學性質中至少其一之不連續。幾何不連續係指長度、厚度、深度、寬度、週期、外部形狀、及內部結構至少其一之不連續。材料不連續係指密度、組成、濃度、及製造方式至少其一之不連續。物理性質不連續係指電學、光學、熱力、及力學性質中至少其一之不連續。化學性質不連續係指摻雜物、活性、酸性、及鹼性中至少其一之不連續。如第3圖及第4圖中所示,接觸層16上形成有不連續區161。若為材料不連續,不連續區161中之材料可能無法與第二電性層15、歐姆接觸區151或其二者形成歐姆接觸。不連續區161之光學性質亦可能與接觸層16相異。光學性質係如穿透率、折射率、與反射率。藉由選擇適當的不連續區161材料可以提高離開或進入轉換部14之能量流或光強度。例如,不連續區161係為空氣缺口,來自於轉換部14之光線可以經由此空氣缺口在不被接觸層16吸收之下離開光電半導體裝置10。若第一電性層13、轉換部14、及第二電性層15至少其一上形成有規則圖形結構、不規則圖形結構、粗糙化結構、光子晶體、或其任何組合亦可能提高由不連續區161進出之能量流或光強度。如第3圖與第4圖所示,若與不連續區161相接觸之第二電性層15之材料具有較大之折射率,歐姆接觸區151可能破壞光線在此折射率介面處之全反射而提高不連續區161之光摘出。The contact layer 16 may be a discontinuous or patterned single layer or multiple layers in addition to a continuous single layer or multiple layers. For a related patent, reference is made to the Taiwan Patent Application No. 096111705, which is hereby incorporated by reference. "Discontinuous" means at least one of geometry, material, physical properties, and chemical properties that is discontinuous. Geometric discontinuity refers to at least one of discontinuity in length, thickness, depth, width, period, outer shape, and internal structure. Discontinuity of the material means that at least one of the density, composition, concentration, and manufacturing method is discontinuous. Physical discontinuity refers to at least one of electrical, optical, thermal, and mechanical properties that are discontinuous. Chemical discontinuity refers to discontinuity of at least one of dopant, activity, acidity, and alkalinity. As shown in FIGS. 3 and 4, a discontinuous region 161 is formed on the contact layer 16. If the material is discontinuous, the material in the discontinuous region 161 may not be in ohmic contact with the second electrical layer 15, the ohmic contact region 151, or both. The optical properties of the discontinuous region 161 may also be different from the contact layer 16. Optical properties such as transmittance, refractive index, and reflectivity. The energy flow or light intensity exiting or entering the conversion portion 14 can be increased by selecting a suitable discontinuous region 161 material. For example, the discontinuous region 161 is an air gap through which light from the conversion portion 14 can exit the optoelectronic semiconductor device 10 without being absorbed by the contact layer 16. If at least one of the first electrical layer 13, the conversion portion 14, and the second electrical layer 15 is formed with a regular pattern structure, an irregular pattern structure, a roughened structure, a photonic crystal, or any combination thereof may also be improved by The energy flow or light intensity of the continuous zone 161. As shown in FIGS. 3 and 4, if the material of the second electrical layer 15 in contact with the discontinuous region 161 has a large refractive index, the ohmic contact region 151 may destroy the entire light at the refractive index interface. The reflection increases the light extraction of the discontinuous area 161.

若光電半導體裝置10係如第3圖或第4圖所示之結構,於第二電性層15或接觸層16之上可選擇性地形成一第二電性接點17,於第一電性層13上可以選擇性地形成一第一電性接點18。電性接點係單層或多層之結構,並為光電半導體裝置10與外部線路電性相連之介面。電性接點可以藉由接線(wiring)與外部線路相連,或直接固著於外部線路之上。If the optoelectronic semiconductor device 10 is configured as shown in FIG. 3 or FIG. 4, a second electrical contact 17 can be selectively formed on the second electrical layer 15 or the contact layer 16 for the first A first electrical contact 18 can be selectively formed on the layer 13. The electrical contact is a single layer or a multi-layer structure, and is an interface in which the optoelectronic semiconductor device 10 is electrically connected to an external line. Electrical contacts can be connected to external lines by wiring or directly to external lines.

此外,電性接點亦可設置於光電半導體裝置10之其他側。例如,第一電性接點18可設置於第一電性層13、過渡層12、或基板11之下,或設置於第一電性層13、過渡層12、及基板11中至少其一之側面。換言之,第一電性接點18與第二電性接點17係分別位於彼此相對或垂直之表面上。於又一實施例中,第二電性接點17可設置於第二電性層之側面。於再一實施例中,第一電性接點18、第二電性接點17、或其二者可藉由穿孔、絕緣材料、或其二者等方式設置於第一電性層13、過渡層12、或基板11之側或表面。In addition, electrical contacts may also be disposed on other sides of the optoelectronic semiconductor device 10. For example, the first electrical contact 18 may be disposed under the first electrical layer 13 , the transition layer 12 , or the substrate 11 , or at least one of the first electrical layer 13 , the transition layer 12 , and the substrate 11 . The side. In other words, the first electrical contact 18 and the second electrical contact 17 are respectively located on surfaces opposite or perpendicular to each other. In still another embodiment, the second electrical contact 17 can be disposed on a side of the second electrical layer. In a further embodiment, the first electrical contact 18, the second electrical contact 17, or both of them may be disposed on the first electrical layer 13 by using a via, an insulating material, or both. The transition layer 12, or the side or surface of the substrate 11.

以下介紹電性接點、歐姆接觸區與不連續區之數種實施例。圖式中雖以第二電性層15與第二電性接點17為例,但並不排除以下實施例亦可以適用於第一電性層13與第一電性接點18,或其他種類之光電半導體裝置。Several embodiments of electrical contacts, ohmic contact regions, and discontinuous regions are described below. Although the second electrical layer 15 and the second electrical contact 17 are taken as an example, the following embodiments are not applicable to the first electrical layer 13 and the first electrical contact 18, or other A type of optoelectronic semiconductor device.

如第5圖所示,接觸層16形成於第二電性層15之上,第二電性接點17形成於接觸層16之上,不連續區161分布於第二電性接點17之周圍。其分布方式當以使來自於電性接點17之電流儘可能地側向流動至接觸層16之外緣,或使得電性接點17下方與接觸層16外緣間之電流密度差值百分比小於60%、50%、40%、30%、20%、或10%。例如,電性接點下方之電流密度為xA/cm2 ,接觸層16外緣之電流密度為yA/cm2 ,其電流密度差值百分比為∣x-y∣/(x與y中較大者)%。As shown in FIG. 5, the contact layer 16 is formed on the second electrical layer 15, the second electrical contact 17 is formed on the contact layer 16, and the discontinuous region 161 is distributed on the second electrical contact 17. around. The distribution is such that the current from the electrical contact 17 flows as much as possible laterally to the outer edge of the contact layer 16, or the percentage of current density difference between the lower of the electrical contact 17 and the outer edge of the contact layer 16 Less than 60%, 50%, 40%, 30%, 20%, or 10%. For example, the current density under the electrical contact is xA/cm 2 , the current density of the outer edge of the contact layer 16 is yA/cm 2 , and the percentage of the current density difference is ∣xy∣/(the greater of x and y) %.

第5(a)圖揭露二種不連續區161之型態,此二種型態可以併存或獨自存在。第二電性接點17右側之接觸層16未與不連續區161重疊;第二電性接點17左側之接觸層16則與不連續區161重疊,且接觸層16與第二電性層15間存在有第三種物質或結構。具體而言,不連續區161或第三種物質或結構係例如空氣、氧化物等絕緣材,或相對於接觸層為非良導體,或布拉格反射鏡(Bragg reflector)、抗反射(anti-reflection)層。此外,第三種物質之折射係數可以介於第二電性層15與接觸層16之間。第二電性接點17下方之接觸層16、第二電性層15、轉換部14、第一電性層13、過渡層12、及基板11中至少其一更可以選擇性地形成一絕緣區152以使來自於第二電性接點17之電流向外分散。然而,圖式中絕緣區152之位置僅為例示,非用以限制本發明之實施方式。第二電性接點17下方之接觸層16與絕緣區152中至少其一之尺寸係約等於或略大於第二電性接點17之尺寸,其中,第二電性接點17下方之接觸層16尺寸係指位於第二電性接點17周圍或下方之接觸層16為不連續區161所包圍之最小虛擬圓之直徑。如第5(b)圖所示,第二電性接點17係埋入接觸層16之中。如第5(c)圖所示,第二電性接點17係埋入接觸層16之中,且電性接點17與接觸層16相接觸之任一表面上係形成為規則表面結構、不規則表面結構、或其二者以增加電性接點17與接觸層16間之接觸面積。例如,電性接點17與接觸層16間之接觸面171係形成為粗糙面以增加彼此間之接觸面積。較大之接觸面積或可增加電性接點17之結構穩固性,或可允許更多的電流通過。Figure 5(a) discloses the pattern of two discontinuous regions 161, which may coexist or exist alone. The contact layer 16 on the right side of the second electrical contact 17 does not overlap with the discontinuous region 161; the contact layer 16 on the left side of the second electrical contact 17 overlaps the discontinuous region 161, and the contact layer 16 and the second electrical layer There is a third substance or structure in the 15th. Specifically, the discontinuous region 161 or the third substance or structure is an insulating material such as air or oxide, or a non-conductor with respect to the contact layer, or a Bragg reflector or anti-reflection. )Floor. Further, the refractive index of the third substance may be between the second electrical layer 15 and the contact layer 16. At least one of the contact layer 16 , the second electrical layer 15 , the conversion portion 14 , the first electrical layer 13 , the transition layer 12 , and the substrate 11 under the second electrical contact 17 can selectively form an insulation. The region 152 is such that the current from the second electrical contact 17 is outwardly dispersed. However, the position of the insulating region 152 in the drawings is merely illustrative and is not intended to limit the embodiments of the present invention. The size of at least one of the contact layer 16 and the insulating region 152 under the second electrical contact 17 is approximately equal to or slightly larger than the size of the second electrical contact 17, wherein the contact under the second electrical contact 17 The layer 16 size refers to the diameter of the smallest virtual circle surrounded by the discontinuity 161 by the contact layer 16 located around or below the second electrical contact 17. As shown in FIG. 5(b), the second electrical contact 17 is buried in the contact layer 16. As shown in FIG. 5(c), the second electrical contact 17 is buried in the contact layer 16, and the surface of the electrical contact 17 in contact with the contact layer 16 is formed into a regular surface structure. The irregular surface structure, or both, increases the contact area between the electrical contacts 17 and the contact layer 16. For example, the contact surface 171 between the electrical contact 17 and the contact layer 16 is formed as a rough surface to increase the contact area with each other. A larger contact area may increase the structural stability of the electrical contacts 17, or may allow more current to pass.

第6(a)~第6(c)圖揭露另一種電性接點之配置型態,其中不連續區161之配置或實施方式請參考第5圖之相關說明。第二電性接點17係直接形成於第二電性層15之上,換言之,在電性接點17與第二電性層15間沒有接觸層16。電性接點17與接觸層16、第二電性層15、或其二者相接觸之任一表面上係形成為規則表面結構、不規則表面結構、或其二者之組合以增加電性接點17與其他部分間之接觸面積。較大之接觸面積或可增加電性接點17之結構穩固性,或可容許更多的電流通過。第二電性接點17下方更可以形成絕緣區152。絕緣區152係約等於或略大於第二電性接點17之尺寸。6(a) to 6(c) disclose another configuration of electrical contacts. For the configuration or implementation of the discontinuous region 161, please refer to the related description of FIG. The second electrical contact 17 is formed directly on the second electrical layer 15 , in other words, there is no contact layer 16 between the electrical contact 17 and the second electrical layer 15 . The surface of the electrical contact 17 in contact with the contact layer 16, the second electrical layer 15, or both is formed as a regular surface structure, an irregular surface structure, or a combination of both to increase electrical properties. The contact area between the contact 17 and other parts. A larger contact area may increase the structural stability of the electrical contacts 17 or allow more current to pass. An insulating region 152 may be formed under the second electrical contact 17. The insulating region 152 is approximately equal to or slightly larger than the size of the second electrical contact 17.

第7圖係揭露依據本發明之另一種實施例之光電半導體裝置。於本實施例中,不連續區161中包含填充質162以填充一或多個歐姆接觸區151中之至少部分空間。藉由調整歐姆接觸區151中填充質162分佈之圖案可以改變來自於或進入轉換部14的電磁輻射或光線之光學特性、電學特性、或其二者。填充質162係如絕緣材、金屬、半導體、摻雜之半導體、波長轉換物質中至少之一。絕緣材係如氧化物、惰性氣體、空氣等。波長轉換物質係如螢光體、磷光體、染料、半導體等。填充質162之折射率亦可以介於其上下物質之間。填充質162若係顆粒,其尺寸應以能夠填入歐姆接觸區151或小於歐姆接觸區151之寬度、深度、或其二者為佳。第7(a)圖中,與電性接點17下方之接觸層16相接之歐姆接觸區151中皆填入填充質162。第7(b)圖中,與電性接點17下方之接觸層16相接之部分歐姆接觸區151中亦填入填充質162,然其他部分之歐姆接觸區151中並未無填充質162存在。如圖所示,接觸層16之外緣部份係延伸入歐姆接觸區151之中。第7(c)圖中,不連續區161(虛線處)中係包含與接觸層16相同之物質,但更包含填充質162。Figure 7 is a diagram showing an optoelectronic semiconductor device in accordance with another embodiment of the present invention. In the present embodiment, the discontinuous region 161 includes a filler 162 to fill at least a portion of the one or more ohmic contact regions 151. The optical, electrical, or both of the electromagnetic radiation or light from or into the conversion portion 14 can be varied by adjusting the pattern of the fill 162 distribution in the ohmic contact region 151. The filling material 162 is at least one of an insulating material, a metal, a semiconductor, a doped semiconductor, and a wavelength converting substance. The insulating material is such as an oxide, an inert gas, air or the like. The wavelength converting substance is a phosphor, a phosphor, a dye, a semiconductor, or the like. The refractive index of the filler 162 can also be between the upper and lower materials. If the filler 162 is a particle, it should preferably be sized to fill the ohmic contact region 151 or less than the width, depth, or both of the ohmic contact region 151. In the figure 7(a), the ohmic contact region 151 which is in contact with the contact layer 16 under the electrical contact 17 is filled with the filling material 162. In the figure 7(b), the portion of the ohmic contact region 151 which is in contact with the contact layer 16 under the electrical contact 17 is also filled with the filling material 162, but the other portions of the ohmic contact region 151 are not filled with the filling material 162. presence. As shown, the outer edge portion of the contact layer 16 extends into the ohmic contact region 151. In the seventh (c) diagram, the discontinuous region 161 (at the dotted line) contains the same material as the contact layer 16, but further contains the filler 162.

如第8圖所示,電性接點17之至少一部分係埋入第二電性層15之中。於(a)圖中,不連續區161下方可選擇性形成歐姆接觸區151、規則表面結構(未顯示)、不規則表面結構(未顯示)、或其組合。於(b)圖中,不連續區161下方不存在歐姆接觸區151。若歐姆接觸區151係藉磊晶成長法形成於第二電性層15之上,可以在不連續區161內之歐姆接觸區151中填入填充質162以使其平坦化(未顯示)。若歐姆接觸區151係藉由濕蝕刻法、乾蝕刻法、或其二混合者形成於第二電性層15之上,可以使用蝕刻遮罩覆蓋預計形成不連續區161之部分以避免第二電性層15表面被蝕刻。於(c)圖中,電性接點17與接觸層16、第二電性層15、或其二者相接觸之任一表面上係形成為規則表面結構、不規則表面結構、或其二者之組合以增加電性接點17與其他部分間之接觸面積。As shown in FIG. 8, at least a portion of the electrical contacts 17 are buried in the second electrical layer 15. In (a), an ohmic contact region 151, a regular surface structure (not shown), an irregular surface structure (not shown), or a combination thereof may be selectively formed under the discontinuous region 161. In the (b) diagram, the ohmic contact region 151 is not present under the discontinuous region 161. If the ohmic contact region 151 is formed on the second electrical layer 15 by epitaxial growth, the filling material 162 may be filled in the ohmic contact region 151 in the discontinuous region 161 to be flattened (not shown). If the ohmic contact region 151 is formed on the second electrical layer 15 by wet etching, dry etching, or a combination thereof, an etching mask may be used to cover a portion of the discontinuous region 161 that is expected to be formed to avoid the second portion. The surface of the electrical layer 15 is etched. In (c), any surface of the electrical contact 17 that is in contact with the contact layer 16, the second electrical layer 15, or both is formed as a regular surface structure, an irregular surface structure, or two thereof. The combination is to increase the contact area between the electrical contacts 17 and other parts.

如第9圖所示,電性接點17之至少一部分係埋入第二電性層15之中,且不連續區161下方亦不存在歐姆接觸區151。於一實施例中,接觸層16係先覆蓋於形成有歐姆接觸區151之第二電性層15之上表面後,再依照預定圖案移除接觸層16之部分區域直到該些區域內之歐姆接觸區151幾乎被移除。如此,形成不連續區161與移除歐姆接觸區151結合於同一系列之製程步驟之中。於另一實施例中,如(b)圖所示,不連續區161之任一內表面上可以形成規則表面結構、不規則表面結構、或其二者之組合。電性接點17與接觸層16、第二電性層15、或其二者相接觸之任一表面上係形成為規則表面結構、不規則表面結構、或其二者以增加電性接點17與其他部分間之接觸面積。As shown in FIG. 9, at least a portion of the electrical contact 17 is buried in the second electrical layer 15, and the ohmic contact region 151 is not present under the discontinuous region 161. In one embodiment, the contact layer 16 first covers the upper surface of the second electrical layer 15 on which the ohmic contact region 151 is formed, and then removes a portion of the contact layer 16 according to a predetermined pattern until the ohms in the regions. The contact area 151 is almost removed. Thus, the formation of the discontinuous region 161 and the removal of the ohmic contact region 151 are combined in the same series of process steps. In another embodiment, as shown in (b), a regular surface structure, an irregular surface structure, or a combination of both may be formed on any of the inner surfaces of the discontinuous regions 161. The electrical contact 17 is formed on either surface of the contact layer 16, the second electrical layer 15, or both to form a regular surface structure, an irregular surface structure, or both to increase the electrical contact. 17 contact area with other parts.

如第10圖所示,歐姆接觸區151係以不同尺寸形成於第二電性層15之上,歐姆接觸區151之型態可以參考前述之說明。於特定狀況下,歐姆接觸區151之內表面或外表面之條件決定接觸層16與第二電性層15間歐姆接觸之質與量。例如,較大範圍之表面可以提供較多的面積以形成歐姆接觸。(a)圖中,歐姆接觸區151之寬度與深度係由電性接點17向外逐漸擴大。(b)圖中,電性接點17下與特定位置處之歐姆接觸區151中係填入填充質162,填充質162之相關事項可參閱前述之說明與圖式。(c)圖中,電性接點17下方並未形成歐姆接觸區151。在此,「尺寸」包含但不限於長度、寬度、深度、高度、厚度、半徑、角度、曲度、間距、面積、體積。As shown in FIG. 10, the ohmic contact regions 151 are formed on the second electrical layer 15 in different sizes, and the type of the ohmic contact regions 151 can be referred to the foregoing description. Under certain conditions, the condition of the inner or outer surface of the ohmic contact region 151 determines the quality and quantity of ohmic contact between the contact layer 16 and the second electrical layer 15. For example, a larger range of surfaces can provide more area to form an ohmic contact. (a) In the figure, the width and depth of the ohmic contact region 151 are gradually enlarged outward from the electrical contact 17. (b) In the figure, the ohmic contact area 151 under the electrical contact 17 and the specific position is filled with the filling material 162. For the matters related to the filling quality 162, refer to the foregoing description and drawings. (c) In the figure, the ohmic contact region 151 is not formed under the electrical contact 17. Here, "size" includes, but is not limited to, length, width, depth, height, thickness, radius, angle, curvature, pitch, area, volume.

以上圖式僅為各個實施例之示意,非用以限制表面結構之形成位置、數量、或型態。「規則表面結構」係指一種結構,其在一表面之任一方向上可辨識出重複性特徵,此重複性特徵之型態可為定週期、變週期、準週期(quasiperodicity)、或其組合。「不規則表面結構」係指一種結構,其在一表面之任一方向上無法辨識出重複性特徵,此結構或可稱為「隨機粗糙表面」。The above figures are merely illustrative of various embodiments and are not intended to limit the location, number, or configuration of surface structures. "Regular surface structure" means a structure that recognizes a repeating feature in either direction of a surface, and the pattern of such repeating features may be a fixed period, a variable period, a quasiperodicity, or a combination thereof. "Irregular surface structure" means a structure that does not recognize a repeating feature in either direction of a surface, and this structure may be referred to as a "random rough surface."

第11圖及第12圖係顯示光電半導體裝置部分區域之上視圖。於第11圖中,不連續區161之圖案係為圓形,並可配置如(a)圖之常規陣列,或如(b)圖之交錯陣列。符號P1表示圓形之間距,符號D1表示圓形直徑。於第12圖中,不連續區161之圖案係為正方形,並可配置如(a)圖之常規陣列,或如(b)圖之交錯陣列。符號P2表示正方形之間距,符號D2表示正方形之邊長。然而不連續區161之形狀並不限於此,其他如矩形、菱形、平行四邊形、橢圓形、三角形、五角形、六角形、梯形、或不規則形亦可以為本發明所採納。11 and 12 are views showing a top view of a partial region of the optoelectronic semiconductor device. In Fig. 11, the pattern of discontinuous regions 161 is circular and may be arranged as a conventional array of (a) or as a staggered array of (b). Symbol P1 denotes a circular distance, and symbol D1 denotes a circular diameter. In Fig. 12, the pattern of discontinuous regions 161 is square and may be arranged as a conventional array of (a) or as a staggered array of (b). Symbol P2 represents the distance between squares, and symbol D2 represents the length of the sides of the square. However, the shape of the discontinuous region 161 is not limited thereto, and other shapes such as a rectangle, a diamond, a parallelogram, an ellipse, a triangle, a pentagon, a hexagon, a trapezoid, or an irregular shape may also be adopted for the present invention.

表1係數個實驗結果之彙整。實驗係採用台灣晶元光電公司所生產之45mil×45mil藍光晶粒,其結構係近似第3圖之光電半導體裝置10,其上並再加工形成如第11(a)圖、第11(b)圖、與第12(a)圖之不連續區與接觸層,即圓形常規陣列、圓形交錯陣列、與正方形常規陣列。接觸層16之材料係電子束蒸鍍之氧化銦錫,其顆粒尺寸約為50nm~80nm,折射率約為2。D1、D2、P1、及P2之單位係為um。Vf係正向電壓。面積比係不連續區之總面積與接觸層面積之百分比。如表1所示,吾人當可發現為獲取亮度增加與降低Vf,不連續區之面積必須適當控制。此外,不連續區在接觸層中之密度亦為一個控制參數。由X. Guo等人於Applied Physics Letters,Vol.78,No.21,p.3337所提之論文中曾提供計算發光二極體之二個電極間電流分散距離(Ls)之方法,此文獻並援引為本申請案之一部分。以上述文獻之估算作為假設,不連續區之尺寸若落於電流分散距離之尺度內,電流可藉由流經第二電性區跨越一個不連續區後再流入接觸層之中。藉此,電流可在接觸層中傳遞較遠的距離。Table 1 summarizes the results of the experimental results. The experiment system uses 45 mil × 45 mil blue crystal grains produced by Taiwan Jingyuan Optoelectronics Co., Ltd., and its structure is similar to that of the photoelectric semiconductor device 10 of Fig. 3, which is processed and formed into a pattern as shown in Fig. 11(a) and 11(b). The discontinuous regions and contact layers of Fig. 12 and Fig. 12(a) are circular conventional arrays, circular staggered arrays, and square conventional arrays. The material of the contact layer 16 is electron beam evaporated indium tin oxide having a particle size of about 50 nm to 80 nm and a refractive index of about 2. The units of D1, D2, P1, and P2 are um. Vf is the forward voltage. The area ratio is the percentage of the total area of the discontinuous area and the area of the contact layer. As shown in Table 1, when we can find that the brightness is increased and the Vf is lowered, the area of the discontinuous area must be appropriately controlled. In addition, the density of the discontinuous regions in the contact layer is also a control parameter. A method for calculating the current dispersion distance (Ls) between two electrodes of a light-emitting diode has been provided in a paper by X. Guo et al., Applied Physics Letters, Vol. 78, No. 21, p. 3337. And cited as part of this application. Taking the estimation of the above literature as a hypothesis, if the size of the discontinuous region falls within the scale of the current dispersion distance, the current can flow into the contact layer by flowing through the second electrical region across a discontinuous region. Thereby, the current can travel a greater distance in the contact layer.

本發明之另數個實施例中,光電半導體裝置10或接觸層16之上視圖係如分別如第13圖~第18圖所示。標號153表示一平台。然各圖中之圖案、數量、比例僅為例示,非用以限制本發明之實施方式,其他依照本文所述之準則、原理、原則、指引、或其他教示皆可合理地應用於本發明之中。In still other embodiments of the present invention, the top view of the optoelectronic semiconductor device 10 or the contact layer 16 is as shown in Figs. 13 to 18, respectively. Reference numeral 153 denotes a platform. The drawings, the quantities, and the ratios in the drawings are merely illustrative and are not intended to limit the embodiments of the present invention, and other criteria, principles, principles, guidelines, or other teachings described herein may be reasonably applied to the present invention. in.

於第13圖中,第二電性接點17包含根部171、支部172、及端部173,其共同構成一電流網路,導引電流朝向預定的方向。根部171係支部172與端部173外觀上之發源處,並通常係外型上之顯著點,可作為製程或檢測過程中之基準點,亦常做為與外部電路連接之處。端部173係網路末端部分,即未再有其他分支。支部172係介於根部171與端部173之間。任二部係彼此電性相連,或者選擇性地實體上彼此相連。例如,任二部間可藉由外部導線、接觸層16、不連續區161、中間材料、或下方區彼此電性相連,其中,「中間材料」係指形成於相鄰二部間隙中之材料,此中間材料或由與至少一部相異之材料形成,或形成於其他製程步驟之中;下方區係指位於三部中任一部下方可以作為電流通道之電性層或電性區,例如第二電性層15或高摻雜區。In Fig. 13, the second electrical contact 17 includes a root portion 171, a branch portion 172, and an end portion 173 which together form a current network for directing current in a predetermined direction. The root portion 171 is the origin of the branch portion 172 and the end portion 173, and is usually a prominent point on the outer shape, and can be used as a reference point in the process or the detection process, and is often used as a connection with an external circuit. The end 173 is the end portion of the network, i.e., there are no more branches. The branch 172 is interposed between the root 171 and the end 173. The two parts are electrically connected to each other or selectively physically connected to each other. For example, any two portions may be electrically connected to each other by external wires, contact layers 16, discontinuous regions 161, intermediate materials, or lower regions, wherein "intermediate material" refers to materials formed in adjacent two gaps. The intermediate material is either formed of at least one different material or formed in other process steps; the lower area refers to an electrical layer or an electrical region which can be used as a current path under any of the three portions. For example, the second electrical layer 15 or a highly doped region.

於一實施例中,第二電性接點17可僅包含根部171與端部173。於他實施例中,各個根部171、支部172、及端部173可使用相同或不同的方式與下方材料相連接,連接方式可參考前述諸實施例與圖式之描述。此外,各部下方可選擇性地形成電流阻障(current blocking)區,以造成電流向下方材料流動的障礙,或調整電流朝向下方流動的形態。電流阻障區係藉由於目標部下方形成絕緣或不良導電材料以達成上述功效。圖式中,根部171、支部172、及端部173的數量、形狀、與佈局僅為例示,非用以限制本發明。例如,第二電性接點17可包括二或多個根部171,根部171間可選擇性形成支部172、端部173、或其二者。一個根部171外可圍繞二或多個支部172或端部173。一個支部172上可分支出二或多個端部173。In an embodiment, the second electrical contact 17 may only include the root portion 171 and the end portion 173. In other embodiments, each of the root portion 171, the branch portion 172, and the end portion 173 may be connected to the underlying material in the same or different manners. The manner of connection may be described with reference to the foregoing embodiments and drawings. In addition, a current blocking region may be selectively formed under each portion to cause an obstacle to current flow to the underlying material, or to adjust a form in which the current flows downward. The current blocking region achieves the above effects by forming an insulating or poor conductive material under the target portion. In the drawings, the number, shape, and layout of the root portion 171, the branch portion 172, and the end portion 173 are merely illustrative and are not intended to limit the present invention. For example, the second electrical contact 17 can include two or more roots 171, and the roots 171 can selectively form a branch 172, an end 173, or both. One or more of the roots 171 may surround two or more of the branches 172 or 173. Two or more ends 173 can be branched from one branch 172.

不連續區161係自接觸層16之外邊界163向內形成,且此些不連續區161並未穿越接觸層16,亦即,各個不連續區161在外邊界163上僅有一個開口164。且二或多個之不連續區161可共用一開口164,如虛線區所示。由上視圖觀之,不連續區161可與第二電性接點17相交(未顯示)或不相交。當與第二電性接點17相交之不連續區161係由絕緣或不良導電材料構成,此相交之不連續區161可與前述之電流阻障區165相整合,如第14圖斜線(hatch)處所示。圖式中電流阻障區165之位置與大小僅為例示,非用以限制本發明之實施。The discontinuous regions 161 are formed inwardly from the outer boundary 163 of the contact layer 16, and such discontinuous regions 161 do not traverse the contact layer 16, i.e., each discontinuous region 161 has only one opening 164 on the outer boundary 163. And two or more discontinuous regions 161 may share an opening 164 as indicated by the dashed area. Viewed from the top view, the discontinuous region 161 can intersect (not shown) or disjoint with the second electrical contact 17. When the discontinuous region 161 intersecting the second electrical contact 17 is made of an insulating or poorly conductive material, the intersecting discontinuous region 161 can be integrated with the aforementioned current blocking region 165, as shown in Figure 14 (hatch) ) as shown. The position and size of the current blocking region 165 in the drawings are merely exemplary and are not intended to limit the implementation of the present invention.

於一實施例中,沿著外邊界163上任意或部分範圍中連續至少三個不連續區161之角度、長度、寬度、深度、與間距中至少一個要素係不相同。如第13圖所示,不連續區1611、1612、與1613具有相同之角度、長度、與寬度,但其間距並不相同,換言之,在不考慮深度之下,此區中不連續區161之配置係呈現一維度之不規則變化。此不規則變化包括局部或全體之不規則變化,例如,位於兩規則變化區之間的不規則變化區。「規則變化」係指等比變化或等差變化。又如不連續區1614、1615、與1616具有不同之角度、長度、寬度、與間距。In one embodiment, at least one of the angle, length, width, depth, and spacing of at least three consecutive discontinuous regions 161 in any or a portion of the outer boundary 163 is different. As shown in Fig. 13, the discontinuous regions 1611, 1612, and 1613 have the same angle, length, and width, but the pitches are not the same, in other words, the discontinuous region 161 in this region is not considered under the depth. The configuration system presents an irregular change in one dimension. This irregular change includes a partial or total irregular change, for example, an irregular change zone located between two rule change zones. "Regular change" refers to a change in equivalence or an increase in equivalence. As another example, the discontinuous regions 1614, 1615, and 1616 have different angles, lengths, widths, and spacings.

於第13與第14圖中,第二電性接點17係左右對稱(bilateral symmetry)。第15圖中,第二電性接點17係非對稱(asymmetry)。第13圖~第15圖中第一電性接點18係左右對稱,但並不限於此,換言之,第一電性接點18亦可為非對稱。於一實施例中,不連續區之總體變化趨勢係符合第二電性接點17之外型,但並不排除少數不連續區161會偏離該變化趨勢。如圍繞根部171或端部173之二個較長不連續區161中仍間或有長度較短者。於另一實施例中,至少部分不連續區161與第二電性接點17間之間隔係約維持於定值或穩定區間內,例如,排列於支部172兩側之各個不連續區161與支部172間之間距即大致相同,亦即間距之大小係落於合理之製程公差範圍內。In the 13th and 14th figures, the second electrical contact 17 is bilateral symmetry. In Fig. 15, the second electrical contact 17 is asymmetry. The first electrical contacts 18 in FIGS. 13 to 15 are bilaterally symmetrical, but are not limited thereto. In other words, the first electrical contacts 18 may also be asymmetric. In an embodiment, the overall variation trend of the discontinuous regions conforms to the second electrical contact 17 appearance, but does not exclude that a few discontinuous regions 161 may deviate from the changing trend. For example, there may still be a shorter length between the two longer discontinuous regions 161 surrounding the root portion 171 or the end portion 173. In another embodiment, the interval between the at least partially discontinuous region 161 and the second electrical contact 17 is maintained within a fixed or stable interval, for example, each discontinuous region 161 arranged on both sides of the branch portion 172 and The distance between the branches 172 is substantially the same, that is, the spacing is within a reasonable tolerance of the process.

第16圖所示之光電半導體裝置10之上視圖揭示一第一電性接點18a、一第一電性接點18b、及一第二電性接點17。第一電性接點18a及18b係形成於平台153之上,並分別包含一根部181、及二個端部183,且各個根部181係分別接近平台153之一個角落。第二電性接點17係形成於接觸層16之上,並包含二個彼此相鄰之根部171、及數個端部173,其中,二個端部173係與根部171直接相連;其餘端部173則係個別連接至三個支部172。第一電性接點18a與18b係物理分離,且又分別與第二電性接點17相叉合。具體而言,第一電性接點18a及18b之各個端部183係形成在平台153之上,並朝向第二電性接點17之根部171延伸,且係介入第二電性接點17之支部172-端部173、支部172-支部172、或端部173-端部173之中。然而,圖示中之數量僅為例示,非用以限制本發明。The top view of the optoelectronic semiconductor device 10 shown in FIG. 16 reveals a first electrical contact 18a, a first electrical contact 18b, and a second electrical contact 17. The first electrical contacts 18a and 18b are formed on the platform 153 and respectively include a portion 181 and two end portions 183, and each of the root portions 181 is adjacent to a corner of the platform 153. The second electrical contact 17 is formed on the contact layer 16 and includes two root portions 171 adjacent to each other and a plurality of end portions 173, wherein the two end portions 173 are directly connected to the root portion 171; The portion 173 is individually connected to the three branches 172. The first electrical contacts 18a and 18b are physically separated and respectively coupled to the second electrical contacts 17. Specifically, each end portion 183 of the first electrical contacts 18a and 18b is formed on the platform 153 and extends toward the root portion 171 of the second electrical contact 17 and is interposed between the second electrical contacts 17 The branch portion 172 - the end portion 173, the branch portion 172 - the branch portion 172, or the end portion 173 - the end portion 173. However, the quantities in the figures are merely illustrative and are not intended to limit the invention.

第一電性接點18a與18b之物理分離使得電性接點之配置更加彈性。例如:第一電性接點18a與18b可以設置於不同水平之平台153之上、第一電性接點18a與18b可以設置於不同之座向、以及二個電性接點間不需要用以連接之支部172、端部173、或其二者。若根部171、支部172、及端部173中至少其一係使用會遮蔽或耗損進入或離開光電半導體裝置10光能之材料,減少此種材料的使用應可以提高光電半導體裝置10的運作效能。此外,圖示中之第一電性接點18a及18b雖係以左右對稱(bilateral symmetry)之形式與第二電性接點17於一電流通道中形成互動,但是,本發明並不以此為限。第一電性接點18a及18b亦可以形成為輻射對稱(radial symmetry)或非對稱之形式。The physical separation of the first electrical contacts 18a and 18b makes the configuration of the electrical contacts more flexible. For example, the first electrical contacts 18a and 18b can be disposed on different levels of the platform 153, and the first electrical contacts 18a and 18b can be disposed in different seating directions and between the two electrical contacts. The connecting branch 172, the end 173, or both. If at least one of the root portion 171, the branch portion 172, and the end portion 173 is used to shield or deplete material entering or leaving the optical energy of the optoelectronic semiconductor device 10, reducing the use of such a material should improve the operational efficiency of the optoelectronic semiconductor device 10. In addition, although the first electrical contacts 18a and 18b in the figure interact with the second electrical contact 17 in a current path in the form of bilateral symmetry, the present invention does not Limited. The first electrical contacts 18a and 18b may also be formed in a form of radial symmetry or asymmetry.

第一電性接點18與第二電性接點17之整體或局部圖樣或係人工編造、或係師法自然生物或現象,諸如:植物葉脈、昆蟲翅脈等、或係具象化一數學函數,諸如:碎型(fractal)。圖示中之第一電性接點18a與18b雖僅分別包括端部183,但本發明並不以此為限,亦即,第一電性接點18a與18b中至少其一也可以包含支部(未顯示)。於一實施例中,不同電性接點之相鄰二部間相隔較大之距離或面積時,藉由合理增加支部、端部、或其二者之數量可以提高電流分散之均勻性。然而,電性接點形成之電流網路若過度密集亦可能降低有效進出光電半導體裝置10之光能量。The whole or partial pattern of the first electrical contact 18 and the second electrical contact 17 is artificially fabricated, or is a natural creature or phenomenon, such as: a plant vein, an insect wing vein, or the like, or a mathematical function. Such as: fractal (fractal). The first electrical contacts 18a and 18b in the figure only include the end portion 183, respectively, but the invention is not limited thereto, that is, at least one of the first electrical contacts 18a and 18b may also include Branch (not shown). In an embodiment, when the adjacent two portions of different electrical contacts are separated by a large distance or area, the uniformity of current dispersion can be improved by reasonably increasing the number of branches, ends, or both. However, if the current network formed by the electrical contacts is excessively dense, the light energy that efficiently enters and exits the optoelectronic semiconductor device 10 may be reduced.

各個支部或端部可以自根部呈等間距、非等間距、等角、或非等角型態向外放射。端部可以自支部呈等間距、非等間距、或交錯型態向外放射。各個支部與端部之幾何外型係可以為直線、曲線、或其組合。曲線之種類至少包含雙曲線、拋物線、橢圓線、圓形線、冪級數曲線、及螺旋線中至少其一。Each branch or end may radiate outwardly from the root at equal intervals, non-equal spacing, isometric, or non-equal angle. The ends may radiate outward from the branch at equal intervals, non-equal spacing, or staggered patterns. The geometric profile of each branch and end can be a straight line, a curve, or a combination thereof. The type of the curve includes at least one of a hyperbola, a parabola, an elliptical line, a circular line, a power series curve, and a spiral.

如第16圖所示,第一電性接點18a與18b之所有端部183數量係少於第二電性接點17之端部173(直接連接至根部171)與支部172(介於根部171與端部173之間)之數量和,然而,本發明並不以此為限。換言之,第一電性接點18a與18b主要叉合部分之數量可以多於或等於第二電性接點17主要叉合部分之數量。再者,第一電性接點18a主要叉合部分之數量亦可以多於、等於、或少於第一電性接點18b主要叉合部分之數量。As shown in FIG. 16, the number of all the ends 183 of the first electrical contacts 18a and 18b is less than the end 173 of the second electrical contact 17 (directly connected to the root 171) and the branch 172 (between the roots) The sum of 171 and the end 173), however, the invention is not limited thereto. In other words, the number of main interdigitated portions of the first electrical contacts 18a and 18b may be greater than or equal to the number of main interdigitated portions of the second electrical contacts 17. Moreover, the number of main interdigitated portions of the first electrical contact 18a may also be greater than, equal to, or less than the number of main interdigitated portions of the first electrical contact 18b.

根部、支部、及端部的高度、寬度、或其二者可以設定為定值、漸變、或隨機。例如:根部、支部、與端部等高、根部最寬,支部次之,端部最細。再者,第一電性接點18a、18b、與第二電性接點17中任二者之尺寸規格可以相同、相異、或部分相同。於一實施例中,如第16圖所示之電性接點係形成於一45mil×45mil或更大之發光二極體晶粒之上,其中,根部、支部、與端部之高度均為2μm,第二電性接點17之支部172與端部173的寬度分別為9μm與7μm,第一電性接點18a與18b之端部寬度為9μm。The height, width, or both of the roots, branches, and ends can be set to a fixed value, a gradual change, or a random. For example, the root, the branch, and the end are the same, the root is the widest, the branch is the second, and the end is the thinnest. Furthermore, the dimensions of the first electrical contacts 18a, 18b and the second electrical contacts 17 may be the same, different, or partially identical. In one embodiment, the electrical contacts as shown in FIG. 16 are formed on a 45 mil x 45 mil or larger illuminating diode die, wherein the height of the root, the branch, and the end are both 2 μm, the width of the branch portion 172 and the end portion 173 of the second electrical contact 17 are 9 μm and 7 μm, respectively, and the width of the end portions of the first electrical contacts 18a and 18b is 9 μm.

圖示中,第二電性接點17之下方更形成電流阻障區165(虛線)以造成電流向下方材料流動的障礙,或調整電流流動的形態。電流阻障區165係藉由於目標部(如第16圖中之第二電性接點17)下方形成絕緣或不良導電材料以達成上述功效。電流阻障區165之尺寸以稍大於上方電性接點尤佳,但本發明並不以此為限。但是,尺寸不當之電流阻障區165可能過分提高光電半導體裝置10之操作電壓。例如,前段所述之45mil×45mil發光二極體之電流阻障區165由自第二電性接點17外擴7μm縮小為5μm,其順向電壓(forward voltage)可以下降0.02伏特。此外,電流阻障區165可以選擇形成於電性接點下方任一單層、多層、或不連續層之中。若電流阻障區165係形成於多層之中,各層中之電流阻障區165之圖樣、尺寸則不以相同為必要。In the figure, a current blocking region 165 (dashed line) is formed under the second electrical contact 17 to cause an obstacle to current flow to the underlying material, or to adjust the form of current flow. The current blocking region 165 achieves the above effects by forming an insulating or poor conductive material under the target portion (such as the second electrical contact 17 in FIG. 16). The size of the current blocking region 165 is preferably slightly larger than the upper electrical contact, but the invention is not limited thereto. However, the improperly sized current barrier region 165 may excessively increase the operating voltage of the optoelectronic semiconductor device 10. For example, the current blocking region 165 of the 45 mil x 45 mil light emitting diode described in the previous paragraph is reduced from 7 μm to 5 μm from the second electrical contact 17, and its forward voltage can be decreased by 0.02 volt. In addition, the current blocking region 165 can be selectively formed in any single layer, multiple layers, or discontinuous layers below the electrical contacts. If the current blocking region 165 is formed in a plurality of layers, the pattern and size of the current blocking region 165 in each layer are not necessarily the same.

如第17圖所示,依據本發明另一實施例之光電半導體裝置10包括第一電性接點18a與18b、及第二電性接點17。第一電性接點18a及18b係分別包含一根部181、及二個端部183。第二電性接點17係包含二個彼此相鄰之根部171、六個支部172、及數個分別由相應支部172向外延伸之端部173。詳言之,支部172包含一主幹174、一第一端175、及一第二端176。第一端175係連接至根部171。第二端176係選擇性地為一開放端。端部173係連接至主幹174。其中,位於圖示中間部位之二個支部172於視覺上係有部分區域相連。除此以外,各部分之解說可以參考第16圖之說明。As shown in FIG. 17, an optoelectronic semiconductor device 10 according to another embodiment of the present invention includes first electrical contacts 18a and 18b and a second electrical contact 17. The first electrical contacts 18a and 18b respectively include a single portion 181 and two end portions 183. The second electrical contact 17 includes two root portions 171 adjacent to each other, six branch portions 172, and a plurality of end portions 173 extending outward from the respective branch portions 172, respectively. In detail, the branch 172 includes a trunk 174, a first end 175, and a second end 176. The first end 175 is coupled to the root 171. The second end 176 is selectively an open end. End 173 is coupled to backbone 174. The two branches 172 located at the middle of the figure are visually connected to a partial area. In addition, the explanation of each part can be referred to the description of Fig. 16.

如第18圖所示,依據本發明再一實施例之光電半導體裝置10包括第一電性接點18a與18b、及第二電性接點17。第一電性接點18a及18b係形成於平台153之上,並分別包含一根部181、及二個端部183,且各個根部181係分別遠離平台153之一個角落。第二電性接點17係形成於接觸層16之上,並包含二個彼此相鄰之根部171及六個支部172。其中,位於圖示中間部位之二個支部172於視覺上係有部分區域相連。接觸層16並形成離散隨機分布(discrete random distribution)之不連續區161。關於不連續區161之其他實施例請參考前述說明。除此以外,各部分之解說可以參考第16圖之說明。As shown in FIG. 18, an optoelectronic semiconductor device 10 according to still another embodiment of the present invention includes first electrical contacts 18a and 18b and a second electrical contact 17. The first electrical contacts 18a and 18b are formed on the platform 153 and respectively include a portion 181 and two end portions 183, and each of the root portions 181 is away from a corner of the platform 153. The second electrical contact 17 is formed on the contact layer 16 and includes two root portions 171 and six branches 172 adjacent to each other. The two branches 172 located at the middle of the figure are visually connected to a partial area. The layer 16 is contacted and forms a discontinuous region 161 of discrete random distribution. For other embodiments of the discontinuous area 161, please refer to the foregoing description. In addition, the explanation of each part can be referred to the description of Fig. 16.

以上各圖式與說明雖僅分別對應特定實施例,然而,各個實施例中所說明或揭露之元件、實施方式、設計準則、及技術原理除在彼此顯相衝突、矛盾、或難以共同實施之外,吾人當可依其所需任意參照、交換、搭配、協調、或合併。The above figures and descriptions are only corresponding to specific embodiments, however, the elements, embodiments, design criteria, and technical principles described or disclosed in the various embodiments are inconsistent, contradictory, or difficult to implement together. In addition, we may use any reference, exchange, collocation, coordination, or merger as required.

雖然本發明已說明如上,然其並非用以限制本發明之範圍、實施順序、或使用之材料與製程方法。對於本發明所作之各種修飾與變更,皆不脫本發明之精神與範圍。Although the invention has been described above, it is not intended to limit the scope of the invention, the order of implementation, or the materials and process methods used. Various modifications and variations of the present invention are possible without departing from the spirit and scope of the invention.

10...光電半導體裝置10. . . Photoelectric semiconductor device

11...基板11. . . Substrate

12...過渡層12. . . Transition layer

13...第一電性層13. . . First electrical layer

14...轉換部14. . . Conversion department

15...第二電性層15. . . Second electrical layer

151...歐姆接觸區151. . . Ohmic contact zone

152...絕緣區152. . . Insulating area

153...平台153. . . platform

16...接觸層16. . . Contact layer

161...不連續區161. . . Discontinuous zone

1611...不連續區1611. . . Discontinuous zone

1612...不連續區1612. . . Discontinuous zone

1613...不連續區1613. . . Discontinuous zone

1614...不連續區1614. . . Discontinuous zone

1615...不連續區1615. . . Discontinuous zone

1616...不連續區1616. . . Discontinuous zone

162...填充質162. . . Filler

163...外邊界163. . . Outer boundary

164...開口164. . . Opening

165...電流阻障區165. . . Current blocking zone

17...第二電性接點17. . . Second electrical contact

171...根部171. . . Root

172...支部172. . . Branch

173...端部173. . . Ends

18...第一電性接點18. . . First electrical contact

18a...第一電性接點18a. . . First electrical contact

18b...第一電性接點18b. . . First electrical contact

181...根部181. . . Root

182...支部182. . . Branch

183...端部183. . . Ends

100...發光元件100. . . Light-emitting element

110...藍寶石基板110. . . Sapphire substrate

120...氮化物緩衝層120. . . Nitride buffer layer

130...n型氮化物半導體疊層130. . . N-type nitride semiconductor stack

140...氮化物多重量子丼發光層140. . . Nitride multiple quantum luminescent layer

150...p型氮化物半導體疊層150. . . P-type nitride semiconductor stack

1501...六角錐孔穴構造1501. . . Hexagonal cone cavity structure

160...氧化物透明導電層160. . . Oxide transparent conductive layer

1601...ITO顆粒1601. . . ITO particles

第1圖係顯示本案申請人之第I237903號台灣專利中所揭露之一種高發光效率之發光元件;Fig. 1 is a view showing a high luminous efficiency light-emitting element disclosed in Japanese Patent No. I237903 of the present applicant;

第2圖係顯示掃描式電子顯微鏡(Scanning Electron Microscope;SEM)下,以電子束蒸鍍法形成之ITO顆粒於六孔錐孔穴中之照片;Figure 2 is a photograph showing the ITO particles formed by electron beam evaporation in a six-hole cone cavity under a scanning electron microscope (SEM);

第3圖係顯示依據本發明一實施例之光電半導體裝置之示意圖;3 is a schematic view showing an optoelectronic semiconductor device according to an embodiment of the present invention;

第4圖係顯示依據本發明一實施例之光電半導體裝置之示意圖;4 is a schematic view showing an optoelectronic semiconductor device according to an embodiment of the present invention;

第5圖係顯示依據本發明一實施例之光電半導體裝置之部分結構之示意圖;Figure 5 is a view showing a part of the structure of an optoelectronic semiconductor device according to an embodiment of the present invention;

第6圖係顯示依據本發明一實施例之光電半導體裝置之部分結構之示意圖;Figure 6 is a view showing a part of the structure of an optoelectronic semiconductor device according to an embodiment of the present invention;

第7圖係顯示依據本發明一實施例之光電半導體裝置之部分結構之示意圖;Figure 7 is a view showing a part of the structure of an optoelectronic semiconductor device according to an embodiment of the present invention;

第8圖係顯示依據本發明一實施例之光電半導體裝置之部分結構之示意圖;Figure 8 is a view showing a part of the structure of an optoelectronic semiconductor device according to an embodiment of the present invention;

第9圖係顯示依據本發明一實施例之光電半導體裝置之部分結構之示意圖;Figure 9 is a view showing a part of the structure of an optoelectronic semiconductor device according to an embodiment of the present invention;

第10圖係顯示依據本發明一實施例之光電半導體裝置之部分結構之示意圖;Figure 10 is a view showing a part of the structure of an optoelectronic semiconductor device according to an embodiment of the present invention;

第11圖係顯示依據本發明一實施例之光電半導體裝置之部分結構之上視圖;Figure 11 is a top plan view showing a portion of a structure of an optoelectronic semiconductor device in accordance with an embodiment of the present invention;

第12圖係顯示依據本發明一實施例之光電半導體裝置之部分結構之上視圖;Figure 12 is a top plan view showing a portion of a structure of an optoelectronic semiconductor device in accordance with an embodiment of the present invention;

第13圖係顯示依據本發明一實施例之光電半導體裝置之接觸層之上視圖;Figure 13 is a top plan view showing a contact layer of an optoelectronic semiconductor device in accordance with an embodiment of the present invention;

第14圖係顯示依據本發明一實施例之光電半導體裝置之接觸層之上視圖;Figure 14 is a top plan view showing a contact layer of an optoelectronic semiconductor device in accordance with an embodiment of the present invention;

第15圖係顯示依據本發明一實施例之光電半導體裝置之接觸層之上視圖;Figure 15 is a top plan view showing a contact layer of an optoelectronic semiconductor device in accordance with an embodiment of the present invention;

第16圖係顯示依據本發明一實施例之光電半導體裝置之上視圖;Figure 16 is a top plan view showing an optoelectronic semiconductor device in accordance with an embodiment of the present invention;

第17圖係顯示依據本發明一實施例之光電半導體裝置之上視圖;及Figure 17 is a top plan view showing an optoelectronic semiconductor device in accordance with an embodiment of the present invention;

第18圖係顯示依據本發明一實施例之光電半導體裝置之上視圖。Figure 18 is a top plan view showing an optoelectronic semiconductor device in accordance with an embodiment of the present invention.

15...第二電性層15. . . Second electrical layer

153...平台153. . . platform

16...接觸層16. . . Contact layer

161...不連續區161. . . Discontinuous zone

1611...不連續區1611. . . Discontinuous zone

1612...不連續區1612. . . Discontinuous zone

1613...不連續區1613. . . Discontinuous zone

1614...不連續區1614. . . Discontinuous zone

1615...不連續區1615. . . Discontinuous zone

1616...不連續區1616. . . Discontinuous zone

163...外邊界163. . . Outer boundary

164...開口164. . . Opening

17...第二電性接點17. . . Second electrical contact

171...根部171. . . Root

172...支部172. . . Branch

173...端部173. . . Ends

18...第一電性接點18. . . First electrical contact

Claims (28)

一種光電半導體裝置,包含:一轉換部,包含一第一側;一電性接點,與該轉換部電性連接;一接觸層與該電性接點相接觸,具有一外邊界;及至少連續三個不連續區,係源自該外邊界,且具有至少一個不相同之要素,其中,該電性接點、該接觸層、及該不連續區係形成於該轉換部之該第一側。 An optoelectronic semiconductor device comprising: a conversion portion including a first side; an electrical contact electrically connected to the conversion portion; a contact layer in contact with the electrical contact, having an outer boundary; and at least Three consecutive discontinuous regions originating from the outer boundary and having at least one different element, wherein the electrical contact, the contact layer, and the discontinuous region are formed in the first portion of the conversion portion side. 如請求項1所述之光電半導體裝置,其中該要素係包含角度、長度、寬度、深度、與間距其中之一。 The optoelectronic semiconductor device of claim 1, wherein the element comprises one of an angle, a length, a width, a depth, and a pitch. 如請求項1所述之光電半導體裝置,其中該電性接點包含一根部、一支部、及一端部。 The optoelectronic semiconductor device of claim 1, wherein the electrical contact comprises a portion, a portion, and an end portion. 如請求項1所述之光電半導體裝置,其中該電性接點包含一區域用以與一外部電路連接。 The optoelectronic semiconductor device of claim 1, wherein the electrical contact comprises an area for connection to an external circuit. 如請求項1所述之光電半導體裝置,其中該電性接點與該不連續區在一投影方向上具有至少一交點。 The optoelectronic semiconductor device of claim 1, wherein the electrical contact and the discontinuous region have at least one intersection in a projection direction. 如請求項1所述之光電半導體裝置,更包含:一電流阻障區,位於該不連續區至少其一下方。 The optoelectronic semiconductor device of claim 1, further comprising: a current blocking region located at least below the discontinuous region. 如請求項1所述之光電半導體裝置,其中各該不連續區在該外邊界上僅具有一個開口。 The optoelectronic semiconductor device of claim 1, wherein each of the discontinuous regions has only one opening on the outer boundary. 如請求項1所述之光電半導體裝置,其中該不連續區係包含至少一電流阻障區。 The optoelectronic semiconductor device of claim 1, wherein the discontinuous region comprises at least one current blocking region. 一種光電半導體裝置,包含:一轉換部;一第一電性接點,與該轉換部電性連接;一第二電性接點,係與該第一電性接點構成一電流通道之兩端; 一接觸層與該第二電性接點相接觸,具有一外邊界;及複數個不連續區,係源自該外邊界,並大體上符合該第二電性接點之外型。 An optoelectronic semiconductor device comprising: a conversion portion; a first electrical contact electrically connected to the conversion portion; and a second electrical contact forming a current path with the first electrical contact end; A contact layer is in contact with the second electrical contact and has an outer boundary; and a plurality of discontinuous regions are derived from the outer boundary and substantially conform to the second electrical contact profile. 如請求項9所述之光電半導體裝置,其中各個該不連續區與相鄰最近之該電性接點間之間距係大體上相同。 The optoelectronic semiconductor device of claim 9, wherein the distance between each of the discontinuous regions and the nearest nearest electrical contact is substantially the same. 如請求項9所述之光電半導體裝置,其中該第一電性接點與該第二電性接點係分別位於該轉換部之相對側。 The optoelectronic semiconductor device of claim 9, wherein the first electrical contact and the second electrical contact are respectively located on opposite sides of the conversion portion. 如請求項9所述之光電半導體裝置,更包含:一歐姆接觸區,位於該接觸層、該不連續區、或其二者下方。 The optoelectronic semiconductor device of claim 9, further comprising: an ohmic contact region located under the contact layer, the discontinuous region, or both. 如請求項9所述之光電半導體裝置,其中該不連續區中至少其一係偏離一總體變化趨勢。 The optoelectronic semiconductor device of claim 9, wherein at least one of the discontinuous regions deviates from an overall trend. 如請求項9所述之光電半導體裝置,其中該第一電性接點與該第二電性接點至少其一係為左右對稱。 The optoelectronic semiconductor device of claim 9, wherein at least one of the first electrical contact and the second electrical contact is bilaterally symmetric. 如請求項9所述之光電半導體裝置,其中該不連續區中至少其二係在該外邊界上具有一共同開口。 The optoelectronic semiconductor device of claim 9, wherein at least two of the discontinuous regions have a common opening on the outer boundary. 一種光電半導體裝置,包含:一轉換部,包含一第一側;一電性接點,位於該轉換部之該第一側,與該轉換部電性連接;一接觸層與該電性接點相接觸,具有一外邊界;及複數個不連續區,係源自該外邊界,由該外邊界朝向該電性接點,並在一個維度上呈現不規則變化。 An optoelectronic semiconductor device comprising: a conversion portion including a first side; an electrical contact on the first side of the conversion portion, electrically connected to the conversion portion; a contact layer and the electrical contact Contacting, having an outer boundary; and a plurality of discontinuous regions originating from the outer boundary, the outer boundary being toward the electrical contact and exhibiting an irregular change in one dimension. 如請求項16所述之光電半導體裝置,其中該接觸層與該不連續區係位於該電性接點與該轉換部之間。 The optoelectronic semiconductor device of claim 16, wherein the contact layer and the discontinuous region are between the electrical contact and the conversion portion. 如請求項16所述之光電半導體裝置,其中該不連續區係包含幾何、材料、物理特性、及化學特性中至少其一之不連續。 The optoelectronic semiconductor device of claim 16, wherein the discontinuous region comprises discontinuities of at least one of geometry, material, physical properties, and chemical properties. 如請求項16所述之光電半導體裝置,更包含:一歐姆接觸區,位於該接觸層、該不連續區、或其二者下方, 並包含一凸起空間、一凹陷空間、或其二者,該空間之幾何形狀係包含角錐、圓錐、與平頭截體中至少其一。 The optoelectronic semiconductor device of claim 16, further comprising: an ohmic contact region, located in the contact layer, the discontinuous region, or both of them, And comprising a raised space, a recessed space, or both, the geometric shape of the space comprising at least one of a pyramid, a cone, and a flat head. 一種光電半導體裝置,包含:一基板,其面積係大於或等於45mil×45mil;一第一電性接點,包含:一第一根部,係與二或多個端部電性相連;及一第二根部,係與該第一根部分離,且與二或多個端部電性相連;一第二電性接點,包含至少二個根部及數個端部;及一轉換部,係介於該基板與該第二電性接點之間;其中該第一電性接點之任二個相鄰端部間係至少存在該第二電性接點之該數個端部之其一。 An optoelectronic semiconductor device comprising: a substrate having an area greater than or equal to 45 mils by 45 mils; a first electrical contact comprising: a first root portion electrically connected to two or more ends; and a first a second portion separated from the first root and electrically connected to two or more ends; a second electrical contact comprising at least two roots and a plurality of ends; and a conversion portion Between the substrate and the second electrical contact; wherein any one of the plurality of ends of the second electrical contact exists between any two adjacent ends of the first electrical contact. 如請求項20所述之光電半導體裝置,其中該第二電性接點之該二個根部係彼此相連。 The optoelectronic semiconductor device of claim 20, wherein the two root portions of the second electrical contact are connected to each other. 如請求項20所述之光電半導體裝置,其中該第二電性接點之該二個根部中至少其一係藉由至少一支部與該多個端部中至少其一電性相連。 The optoelectronic semiconductor device of claim 20, wherein at least one of the two root portions of the second electrical contact is electrically connected to at least one of the plurality of ends by at least one portion. 如請求項20所述之光電半導體裝置,其中該第二電性接點更包含:一支部,係具有一第一端、一第二端、與一主幹,該第一端係連接至該二根部中至少其一,該主幹係與該數個端部中至少其一相連。 The optoelectronic semiconductor device of claim 20, wherein the second electrical contact further comprises: a portion having a first end, a second end, and a trunk, the first end being connected to the second At least one of the roots, the backbone being connected to at least one of the plurality of ends. 如請求項20所述之光電半導體裝置,更包含:一電流阻障區,係位於該第二電性接點之下。 The optoelectronic semiconductor device of claim 20, further comprising: a current blocking region located below the second electrical contact. 如請求項20所述之光電半導體裝置,更包含:一平台,該第一電性接點係形成於該平台之上。 The optoelectronic semiconductor device of claim 20, further comprising: a platform, the first electrical contact being formed on the platform. 如請求項20所述之光電半導體裝置,更包含: 一接觸層,係介於該第二電性接點與該轉換部之間,並包含一不連續區。 The optoelectronic semiconductor device of claim 20, further comprising: A contact layer is interposed between the second electrical contact and the conversion portion and includes a discontinuous region. 一種電流通道,係提供電流通過一轉換部,包含:一第一電性接點,包含:一第一根部,係與二或多個端部電性相連;及一第二根部,係與該第一根部分離,且與二或多個端部電性相連;及一第二電性接點,包含至少二個根部及數個端部,其中該第一電性接點之任二個相鄰端部間係至少存在該第二電性接點之該數個端部之其一;其中該轉換部係包含一第一面與一第二面,該第一面係電性連接至該第一電性接點,該第二面係電性連接至該第二電性接點。 A current channel is provided for passing a current through a conversion portion, comprising: a first electrical contact, comprising: a first root portion electrically connected to two or more end portions; and a second root portion The first portion is separated and electrically connected to the two or more ends; and the second electrical contact includes at least two roots and a plurality of ends, wherein any two of the first electrical contacts Between the adjacent ends, at least one of the plurality of ends of the second electrical contact; wherein the converting portion includes a first surface and a second surface, the first surface is electrically connected to the The first electrical contact is electrically connected to the second electrical contact. 如請求項27所述之電流通道,其中該第二電性接點之該二個根部係彼此相連。 The current channel of claim 27, wherein the two roots of the second electrical contact are connected to each other.
TW98118503A 2005-02-21 2009-06-03 Optoelectronic semiconductor device TWI393271B (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
TW98118503A TWI393271B (en) 2008-09-18 2009-06-03 Optoelectronic semiconductor device
US12/562,917 US9508902B2 (en) 2005-02-21 2009-09-18 Optoelectronic semiconductor device
US15/256,263 US9876146B2 (en) 2005-02-21 2016-09-02 Optoelectronic semiconductor device
US15/839,160 US10529895B2 (en) 2005-02-21 2017-12-12 Optoelectronic semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW97135936 2008-09-18
TW98118503A TWI393271B (en) 2008-09-18 2009-06-03 Optoelectronic semiconductor device

Publications (2)

Publication Number Publication Date
TW201013984A TW201013984A (en) 2010-04-01
TWI393271B true TWI393271B (en) 2013-04-11

Family

ID=44838196

Family Applications (2)

Application Number Title Priority Date Filing Date
TW98118503A TWI393271B (en) 2005-02-21 2009-06-03 Optoelectronic semiconductor device
TW102105142A TWI517444B (en) 2008-09-18 2009-06-03 Optoelectronic semiconductor device

Family Applications After (1)

Application Number Title Priority Date Filing Date
TW102105142A TWI517444B (en) 2008-09-18 2009-06-03 Optoelectronic semiconductor device

Country Status (1)

Country Link
TW (2) TWI393271B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9147808B2 (en) 2012-10-19 2015-09-29 National Sun Yat-Sen University III-nitride quantum well structure and a light-emitting unit using the same

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101859856B (en) 2010-06-04 2016-06-15 清华大学 Light emitting diode
TWI553911B (en) * 2010-08-09 2016-10-11 廣鎵光電股份有限公司 Light-emitting device structure
TWI632700B (en) * 2013-05-24 2018-08-11 晶元光電股份有限公司 Light-emitting element having a reflective structure with high efficiency
TWM648765U (en) * 2022-01-25 2023-12-01 日揚科技股份有限公司 Semiconductor structure and processing device of the semiconductor structure

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5869849A (en) * 1995-10-05 1999-02-09 Industry Technology Research Institute Light-emitting diodes with high illumination
US6885036B2 (en) * 1999-12-01 2005-04-26 Cree, Inc. Scalable LED with improved current spreading structures
US20070045640A1 (en) * 2005-08-23 2007-03-01 Erchak Alexei A Light emitting devices for liquid crystal displays

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5869849A (en) * 1995-10-05 1999-02-09 Industry Technology Research Institute Light-emitting diodes with high illumination
US6885036B2 (en) * 1999-12-01 2005-04-26 Cree, Inc. Scalable LED with improved current spreading structures
US20070045640A1 (en) * 2005-08-23 2007-03-01 Erchak Alexei A Light emitting devices for liquid crystal displays

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9147808B2 (en) 2012-10-19 2015-09-29 National Sun Yat-Sen University III-nitride quantum well structure and a light-emitting unit using the same

Also Published As

Publication number Publication date
TW201334224A (en) 2013-08-16
TW201013984A (en) 2010-04-01
TWI517444B (en) 2016-01-11

Similar Documents

Publication Publication Date Title
US10529895B2 (en) Optoelectronic semiconductor device
JP6262778B2 (en) Light emitting diode and method of manufacturing the same
US8878220B2 (en) Light emitting diode with improved luminous efficiency
JP6324706B2 (en) Light emitting device and method for manufacturing the same
US12068433B2 (en) Light-emitting device and manufacturing method thereof
TWI393271B (en) Optoelectronic semiconductor device
CN101685842B (en) Optoelectronic semiconductor device
TWI744622B (en) Optoelectronic device
TWI731163B (en) Semiconductor device
TWI585941B (en) Light emitting diode and method of fabricating the same
KR20110111799A (en) Light emitting diode employing non-polar substrate
KR20110132161A (en) Semiconductor light emitting diode and method of manufacturing thereof
CN112997324A (en) Semiconductor light emitting device
TWI405352B (en) Optoelectronic semiconductor device
TWI539620B (en) Optoelectronic semiconductor device
CN102938438B (en) Optoelectronic semiconductor device
CN102024884B (en) Optoelectronic semiconductor device
KR102217128B1 (en) Light emitting diode and method of fabricating the same
TWI446588B (en) Semiconductor light-emitting device having stacked transparent electrodes
TWI570967B (en) Patterned substrate and semiconductor device
TW202135329A (en) Semiconductor device