13641051364105
九、發明說明： 【發明所屬之技術領域】 本發明係有關一種封膠技術，尤其是指一種利用特殊 之模板设計，以對具有晶片以及電子元件之基板進行封膠 製程之一種晶片模組之封膠模板及其封膠方法。 / 【先前技術】 現代消費性電子產品已經逐漸走向輕薄短小以 及整合多功能於一身的潮流。為了滿足上述的需求， 電子封裝技術無不精益求精，力求在有限空間内整合 不同功能之電子電路元件或晶片，以圖在市場上佔^ 一席之地。因此，封裝技術的輔助是不可或缺的，而 在這類型的封裝技術中，可以分為好幾種，其中較為 人知的為多晶片模組（multi chip module, MCM)封 或者是晶片直接封裝（chip on board, COB)等，為了 方便說明封裝後之結構，本發明以”晶片模組，，來作 統稱。前述之晶片模組的封裝技術，主要為在一基板 上整合多元之訊號處理電路，以運用於現代的各種電 子產品，如電腦、手機或數位相機等類之消費性電子 產品。 、 以C0B晶片模組為例，其關鍵技術在於打線 (wire bonding)以及封膠成形（molding)，主要方法 疋將裸晶片直接黏在電路板或基板上，並結合晶片黏 著、導線連接以及應用封膠技術等基本製程，將晶片 1364105 製造的封裝與測試步驟轉移到基板組裝階段。請參閱 圖一 A所示’一般而言c〇B封裝為將裸露的積體電路 晶二(ic Chip)10封裝於一基板n上，其中晶片1〇 藉由金屬線12,將其I/O經封裝體的線路延伸出來。 在圖一 A中僅一晶片10作代表，因為實際上為了整 合多元性之功能，該基板丨丨上可具有複數個晶片 接著，如圖一 B所示，在基板u上覆蓋一模板 13 ’杈板13上開設有通孔14以提供容置該晶片} 〇。 然後利用印刷（printing)的方式將封膠材料 15(encapsulation material)覆蓋於該晶片 1〇 之上 方，然後取下模板13以形成如圖一 c的結果 - C中’該晶片10上方便覆蓋有一層封膠材 二 保護該晶片10。接著如圖一 D所示，在該基板"上 利用表面黏著（surfaee m_ting。訂， π# 16(例如：被動元件)等配置於佈局之位 下列2之過程為典型印刷封膠的製程，不過卻具有 的成本加上料的成本，遠大於夢 件16。因此，如果：：=11上的電子元 的話，當黏著電 ^丁曰曰片10的貼合程序 Ϊ 件16之製程失敗而造成 ,報廢整個模組時，會造成成本的增加。 (2)進行晶片1()接合需 再進行黏著電子元件〗订一次熱處理，然後 6時又必須再進行一次 w'’藉由先焊好之電子元 本發日月提#一二/少晶片封農時基板變形的問題。 板上黏著電供H晶片模組之封膠方法，其係可先於基 好電子元件， 月封裳，由於基板已經先黏著 熱衝擊，另外# ;可以減少對封裝晶片所造成的焊爐 產良率與品質減少報廢原物料之成本 ’進而提^生 板：係I:::面=明提供-種晶片模組之封膠模 通該頂面以及底二該封膠模板上開設有貫 之晶片，在該底 提:容置該晶片模組上 晶片模組上之電子元^成有）、—溝槽，以提供容置該 =另實施例t，本發明提供一種晶片模組之封膠方 、卜八係匕括有下列步驟：提供一基板；以一接著程序將 複數個電子元件電性連接於該基板上；將至少-晶片與該 基板作電性連接；提供一封膠模板，其係具有一頂面以及 一底面，該封膠模板上開設有貫通該頂面以及底面之至少 一通孔以分別提供容置該至少一晶片，在該底面上更形成 有至少一溝槽，以提供容置該複數個電子元件；以及利用 一封膠程序將膠材填入該至少一通孔内以封膠該至少一晶 片。 ^ 【實施方式】 為使貴審查委員能對本發明之特徵、目的及功能有 更進一步的認知與瞭解，下文特將本發明之裝置的相關細 9 1364105 ^结構以及輯的理念原錢行朗，以使得$查委員可 以了解本發明之特點，詳細說明陳述如下： . 請參閱圖二所示，該圖係為⑽基材示意圖。該⑽ 基材2上具有複數個⑽晶片模組20，每一個模組20上 具有至少一個晶片201以及複數個電子元件2〇2。該至少IX. INSTRUCTIONS: [Technical Field] The present invention relates to a sealing technology, and more particularly to a wafer module that utilizes a special template design to seal a substrate having a wafer and an electronic component. Sealing template and sealing method thereof. / [Prior Art] Modern consumer electronics products have gradually moved toward a light, short, and versatile trend. In order to meet the above requirements, electronic packaging technology is constantly improving, and it is necessary to integrate electronic circuit components or chips with different functions in a limited space in order to occupy a place in the market. Therefore, the encapsulation technology is indispensable, and in this type of packaging technology, it can be divided into several types, among which the multi-chip module (MCM) or the wafer is directly packaged. (chip on board, COB), etc., in order to facilitate the description of the packaged structure, the present invention is collectively referred to as a "wafer module." The above-mentioned chip module packaging technology mainly integrates multi-signal processing on a substrate. Circuits are used in modern electronic products such as computers, mobile phones or digital cameras. For example, in the case of C0B chip modules, the key technologies are wire bonding and molding. The main method is to directly bond the bare wafer to the circuit board or substrate, and combine the wafer bonding, wire bonding and application of the sealing technology to transfer the package and test steps made by the wafer 1364105 to the substrate assembly stage. As shown in FIG. 1A, in general, the c〇B package is to package the bare integrated circuit ic chip 10 on a substrate n, wherein the wafer 1〇 The I/O is extended by the wiring of the package by the metal line 12. Only one wafer 10 is represented in FIG. A because, in fact, in order to integrate the function of the plurality of layers, the substrate may have a plurality of The wafer is then covered with a template 13' on the substrate u, and a through hole 14 is formed in the substrate 13 to provide the wafer. The film is then printed by means of printing. An encapsulation material is overlaid on the wafer 1 and then the template 13 is removed to form a result as shown in FIG. 1C. The wafer 10 is conveniently covered with a layer of sealing material to protect the wafer 10. As shown in a D, the process of arranging the surface of the substrate by using the surface adhesion (surfaee m_ting, π# 16 (for example, passive components), etc., is the typical printing sealant process, but has The cost plus the cost of the material is much larger than that of the dream piece 16. Therefore, if the electronic element on the ::=11 is caused by the failure of the process of the bonding process of the bonding device 10, the scrapping is caused. Cost of the entire module (2) Performing wafer 1 () bonding requires further heat treatment of the adhesive electronic component, and then must be performed once again at 6 o'clock. The problem of deformation of the substrate when the wafer is sealed is small. The sealing method of the H chip module is adhered to the board, and the system can be preceded by the base electronic component, the moon seal skirt, because the substrate has been adhered to the thermal shock first, and Reducing the yield and quality of the soldering furnace caused by the packaged wafers and reducing the cost of scrapping the raw materials. Further improving the board: the I::: surface = Ming provides - the sealing mold of the wafer module passes the top surface and The bottom of the sealing template is provided with a continuous chip, and the bottom layer: the electronic component on the chip module is received, and the groove is provided to provide the housing. The present invention provides a sealing method for a wafer module, and the following steps: providing a substrate; electrically connecting a plurality of electronic components to the substrate in a subsequent process; at least - the wafer and the substrate Electrical connection; provide a glue template with a top surface to And a bottom surface, the at least one through hole penetrating the top surface and the bottom surface is provided to respectively receive the at least one wafer, and at least one groove is further formed on the bottom surface to provide the plurality of holes The electronic component; and filling the at least one through hole with a glue program to seal the at least one wafer. ^ [Embodiment] In order to enable the reviewing committee to have a further understanding and understanding of the features, objects and functions of the present invention, the following is a detailed description of the structure and the concept of the device of the present invention. In order to make the members of the invention understand the characteristics of the present invention, the detailed description is as follows: . Referring to Figure 2, the figure is (10) schematic diagram of the substrate. The (10) substrate 2 has a plurality of (10) wafer modules 20, each of which has at least one wafer 201 and a plurality of electronic components 2〇2. At least
:晶片201係與基板203作電性接合，在本實施例中該c〇B 模、’且20上之晶片201雖以圖示顯示三個，但是實際上之數 • 里可根據設計而定，並不以圖示之數量為限。該複數個電 子元件202係佈設於該基板203上，在本實施例中，該複 數個電子元件202係為被動元件，例如：電阻、電容或者 是電感等。該COB晶片模組20係為習用之結構在此不作贅 述。 如圖三A所示，該圖係為本發明之晶片模組之封膠模 板立體示意圖。在本實施例中，該封膠模板3係與圖二之 基材2大小對應’該封膠模板3上具有一頂面3〇以及一底 鲁面31，該封膠模板3上具有複數個模板區塊32，每一個模 板區塊32對應耆圖二中的COB晶片模組20。另外該封膠 模板3之本體所使用之材料也是根據需求而定，材料選擇 可為金屬或者是非金屬材料，在本實施例中之封膠模板3 材料係為鋼板材料。每一個模板區塊3 2可以具有至少一個 通孔320,其係貫通該頂面30以及底面31，在本實施例中， 該通孔320係具有三個，但其數量係為根據需要而定，並 不以本實施例之圖示為限。 請參閱圖三B所示，該圖係為本發明之封膠模板底面 結構立體示意圖。該封膠模板3之底面31上之每個模板區 1364105 塊32更具有複數個溝槽321與322，其設計與配置是根據 需求而定’在本發明之實施例申，凹槽321係沿著該通孔 320之外圍設置，使得每一個通孔320與該凹槽321間以 一凸部結構323作區隔。另外，在該模板區塊32之其他位 置上也開設有凹槽322。由於圖三A與圖三B中之模板區 塊323係與圖二中之COB晶片模組相對應，為了方便說明， 請參閱圖四所示’該圖係為其中之一模組區塊與其對應之 COB晶片模組剖面示意圖。每一個通孔320可提供容置晶 片201，而底面上之凹槽321，則可以提供容置設置於該基 板203上之電子元件202。由於該通孔320係可容置晶片 201’而該凹槽321係可容置電子元件202,因此該通孔320 與該凹槽321之位置分佈是根據基板203上的電路佈局而 定，因此並不以本發明之實施例為限。 請參閱圖五所示’該圖係為本發明之晶片模組之封膠 方法流程示意圖。在本實施例+，該封膠方法其係包括有 下列步驟：首先進行步驟40，提供一基板，其係具有複數 個COB晶片模組之佈局’該基板内係具有電路結構之佈 局’以與晶片與電子元件作電性連接，在本實施例中，該 基板係為一印刷電路板（printed circuit board, PCB)。 如圖六A所示’為了方便說明，僅以代表一 COB模組20之 基板203作說明。接著進行步驟41，以一接著程序，將複 數個電子元件202接者於§亥基板203上之對應位置。該複 數個電子元件202係可為被動元件，如：電阻、電威咬者 是電容等，但不以此為限。該接著程序係可選擇為手焊戋 者是自動焊接的方式來達成。在本實施例中，該接著程序 1364105 係利用表面黏著技術（surface mounting technology, SMT) 將複數個電子元件202接著於該基板203上，其結果如圖 六B所示。至於表面黏著技術係屬於習用技術，在此不作 贅述。 步驟41之後’接著進行步驟42,將至少一晶片201與The wafer 201 is electrically connected to the substrate 203. In the present embodiment, the c〇B mode, and the wafer 201 on the 20 are shown as three in the figure, but the actual number can be determined according to the design. , not limited to the number shown. The plurality of electronic components 202 are disposed on the substrate 203. In the embodiment, the plurality of electronic components 202 are passive components, such as resistors, capacitors, or inductors. The structure of the COB wafer module 20 is conventional and will not be described herein. As shown in FIG. 3A, the figure is a perspective view of a sealing mold of the wafer module of the present invention. In this embodiment, the sealant template 3 corresponds to the size of the substrate 2 of FIG. 2, and the sealant template 3 has a top surface 3〇 and a bottom surface 31, and the sealant template 3 has a plurality of The template block 32, each of the template blocks 32 corresponds to the COB chip module 20 in FIG. In addition, the material used for the body of the sealant template 3 is also determined according to requirements, and the material selection may be metal or non-metal material. In the embodiment, the sealant template 3 material is a steel plate material. Each of the template blocks 32 may have at least one through hole 320 extending through the top surface 30 and the bottom surface 31. In this embodiment, the through holes 320 have three, but the number is determined according to needs. It is not limited to the illustration of the embodiment. Please refer to FIG. 3B, which is a perspective view of the bottom structure of the sealing template of the present invention. Each of the template regions 1364105 on the bottom surface 31 of the sealant template 3 has a plurality of grooves 321 and 322, which are designed and configured according to requirements. In the embodiment of the present invention, the groove 321 is along the line. The periphery of the through hole 320 is disposed such that each of the through holes 320 and the groove 321 are separated by a convex structure 323. In addition, a recess 322 is also formed in other locations of the template block 32. Since the template block 323 in FIG. 3A and FIG. 3B corresponds to the COB chip module in FIG. 2, for convenience of explanation, please refer to FIG. 4, which is one of the module blocks and Corresponding schematic diagram of the COB chip module. Each of the through holes 320 can provide the accommodating wafer 201, and the recess 321 on the bottom surface can provide the electronic component 202 disposed on the substrate 203. Since the through hole 320 can accommodate the chip 201 ′ and the groove 321 can accommodate the electronic component 202 , the position distribution of the through hole 320 and the groove 321 is determined according to the circuit layout on the substrate 203 , so It is not limited to the embodiments of the present invention. Please refer to FIG. 5, which is a schematic flow chart of the sealing method of the wafer module of the present invention. In this embodiment, the encapsulation method includes the following steps: First, step 40 is performed to provide a substrate having a layout of a plurality of COB wafer modules, wherein the substrate has a layout of a circuit structure to The chip is electrically connected to the electronic component. In this embodiment, the substrate is a printed circuit board (PCB). As shown in Fig. 6A, for the sake of convenience of explanation, only the substrate 203 representing a COB module 20 will be described. Next, in step 41, a plurality of electronic components 202 are connected to corresponding positions on the CMOS substrate 203 in a subsequent process. The plurality of electronic components 202 can be passive components, such as: resistors, electric powers, and the like, but not limited thereto. This follow-up procedure can be achieved by means of automatic soldering for hand soldering. In the present embodiment, the following procedure 1364105 uses a surface mounting technology (SMT) to place a plurality of electronic components 202 on the substrate 203. The result is shown in Figure 6B. As for the surface adhesion technology, it is a conventional technique and will not be described here. After step 41, then proceeding to step 42, the at least one wafer 201 is
該基板203作電性連接。如圖六c所示，在步驟42主要是 先將晶片201接著於該基板203上之特定位置，然後再進 行打線（wire bonding)，以使該晶片2〇1上之接腳與基板 203上之電性板作連接。至於如何接著晶片以及打線之技 術係為習用之技術，在此不作贅述。接下來進行步驟43， 提供一封膠模板3罩覆於該基板203上，該封膠模板3之 特徵係如同前述圖三A與圖三B所示。如圖六！）所示，為 了方便說明，圖六D中僅顯示著單—之模組區塊32，但實 際上該封膠模板是由複數個模板區塊32以陣列的形式排 列，以利進行大量生產。在步驟43中，當該封膠模板上罩 覆於基板203上時，COB晶片模組2〇上之晶片2〇1則容置 於對應之通孔320内，COB晶片模級2〇上之電子元件2〇2 則容置於對應之凹槽321内。 再回到圖五所示’隨後進行步驟44，利用一封膠程序 將膠材填入該至少-通孔内以封膠該至少—晶片。請來閱 =六E所示’在本實施例中，該封膠程序係為一印刷封膠 的程序，其主要在該封膠模板上提供一封膠材料 ，腦卿此on)，然後利用刮刀91進行一位移運動， =封膠材料填入至該通孔320内，以將該通孔32〇内之 曰曰片2〇1封住。由於該通孔320與該凹槽321之間具有凸 12 1364105 部結構323,在刮刀91施壓於該封膠模板之頂面3〇上時， 該凸部結構323可抵靠於該基板203上，因此充填的封膠 . 材料90於通孔320的過程中，該封膠材料9〇不會流入凹 ' · 槽内321損害電子元件202，並確保通孔内之晶片2〇1可 以完全被封住。最後，再將該封膠模板取出，以形成如圖 六F之結構。 如圖七A與圖七B所示，該圖係為本發明之晶片模組 φ 之封膠模版另一實施例示意圖。在本實施例中，封膠模板 3主要疋針對具有尚度比封膠模板3厚度還大的雷早开株 2〇4時的設料式。频_上3 具有至少-個中空凸罩33 ’其内之容置空間開口係位於該 底面31上，以提供容置電子元件204。本實施例中之每一 個模板區塊32上之中空凸罩33雖然顯示一個，但是實際 上中空凸罩之數量可根據電子元件204之數量而定，並^ 以本發明圖七A與圖七B之實施例為限。至於在圖七a之 • 實施例中，刮刀91之設計可以具有開口 910，以避開中空 . 凸罩33。另外，也可以將過大之電子元件2〇4在佈局設二 - 時，避開封膠刮刀91行進的路線。 在這裡需強調的是，雖然步驟41與步驟42係分別為 習用之技術，但是本發明之方式與習用技術不同的是在於 透過本發明之封裝程序，由於步驟41是先黏著電子元件於 基板上，因此增加了基板的強度，減低了因為步驟44之封 膠程序，造成基板變形的問題。另外，因為先利用表面黏 著將電子元件黏著於基板上，再進行步驟42之貼合晶片的 時候，被封裝之晶片可以減少額外的回焊爐所產生的熱衝The substrate 203 is electrically connected. As shown in FIG. 6c, in step 42, the wafer 201 is first placed on a specific position on the substrate 203, and then wire bonding is performed to make the pads on the wafer 2〇1 and the substrate 203. The electrical board is connected. As for the technique of how to follow the wafer and the technology of the wire, it will not be described here. Next, in step 43, a glue template 3 is provided to cover the substrate 203, and the seal template 3 is characterized as shown in the foregoing FIG. 3A and FIG. 3B. Figure 6! As shown in the figure, for the convenience of description, only the module block 32 of the single-block is shown in FIG. 6D, but in practice, the sealant template is arranged in an array by a plurality of template blocks 32 for mass production. . In step 43, when the encapsulant is overlaid on the substrate 203, the wafer 2〇1 on the COB wafer module 2 is placed in the corresponding via 320, and the COB wafer module is on the top of the substrate. The electronic component 2〇2 is accommodated in the corresponding recess 321 . Returning to Figure 5, step 44 is followed by filling a glue into the at least through-hole using a glue procedure to seal the at least wafer. Please refer to =6E'. In this embodiment, the sealing process is a printing and sealing process, which mainly provides a glue material on the sealing template, and then uses it. The scraper 91 performs a displacement movement, and the sealing material is filled into the through hole 320 to seal the cymbal 2〇1 in the through hole 32〇. Since the through hole 320 and the groove 321 have a convex 12 1364105 structure 323, the convex structure 323 can abut against the substrate 203 when the blade 91 is pressed on the top surface 3 of the seal template. The encapsulating material is filled. During the process of the material 90 in the through hole 320, the sealing material 9〇 does not flow into the concave portion. The inside of the groove 321 damages the electronic component 202, and ensures that the wafer 2〇1 in the through hole can be completely Was sealed. Finally, the sealant template is taken out to form a structure as shown in Fig. 6F. As shown in FIG. 7A and FIG. 7B, the figure is a schematic view of another embodiment of the sealing stencil of the wafer module φ of the present invention. In the present embodiment, the sealant stencil 3 is mainly used for the design of the ridge early opening 2 〇 4 which is still larger than the thickness of the seal stencil 3 . The frequency_upper 3 has at least one hollow convex cover 33' on which the accommodating space opening is located to provide the accommodating electronic component 204. Although the hollow convex cover 33 on each of the template blocks 32 in this embodiment shows one, the number of the hollow convex covers can be determined according to the number of the electronic components 204, and the present invention is shown in FIG. 7A and FIG. The embodiment of B is limited. As for the embodiment of Fig. 7a, the blade 91 may be designed to have an opening 910 to avoid the hollow cover 33. In addition, it is also possible to avoid the route traveled by the sealant blade 91 when the oversized electronic component 2〇4 is set to two. It should be emphasized here that although steps 41 and 42 are respectively conventional techniques, the method of the present invention differs from the conventional technology in that the package process of the present invention is adopted, since step 41 is to adhere the electronic component to the substrate first. Therefore, the strength of the substrate is increased, and the problem of deformation of the substrate due to the sealing process of step 44 is reduced. In addition, since the electronic component is first adhered to the substrate by surface adhesion, and then the wafer is bonded in step 42, the packaged wafer can reduce the thermal shock generated by the additional reflow furnace.
13 :C S ^進而減少晶片損壞的機率。此外 :黏著電子元件再進行貼合程序，因發明是先進 為:著電子元件失敗報廢整個基 容置電子元件，^ 有凹槽之設計’因為可以提供 不會影—著·/可以增加基板上電路佈局的多元性， 4者電子元件之製程自動化。 制本述Γ僅為本發明之實施例’當不能以之限 變化及修#卩大凡依本發明_請專鄉圍所做之均等 明之於袖仍將不失本發明之要義所在，亦不脫離本發 :砷和範圍，故都應視為本發明的進一步實施狀況。 膠方、上述’本發明提供之晶片模組之封膠模板及其封 夕'’可以使得晶片模組之佈局設計更有彈性以提昇量 產之逮度以及減少晶片封膠時的生產成本進而提昇生產良 品質。因此可以滿足業界之需求，進而提高該產業之 競:力以及帶動週遭產業之發展’誠已符合發明專利法所 規=申請發明所需具備之要件’故爰依法呈提發明專利之 申f ’謹請責審查委員允撥時間惠予審視，並賜准專利 為禱。 1364105 【圖式簡單說明】 圖一 A至圖一 D係為習用之晶片模組封裝流程示意圖。 圖一 E係為習用之封裝晶片模組基板變形示意圖。 圖二係為C0B基材示意圖。 圖三A係為本發明之晶片模組之封膠模板立體示意圖。 圖三B係為本發明之封膠模板底面結構立體示意圖。 圖四係為其中之一模組區塊與其對應之C0B晶片模組剖面 示意圖。 圖五係為本發明之晶片模組之封膠方法流程示意圖。 圖六A至圖六F係為本發明之晶片模組之封膠方法流程中 各階段之結構剖面示意圖。 圖七A與圖七B係為本發明之晶片模組之封膠模版另一實 施例示意圖。 【主要元件符號說明】 10_晶片 11-基板 12 -金屬線 13- 模板 14- 通孔 15- 封膠材料 16- 電子元件 2-C0B基材 15 1364105 20-COB晶片模組 201-晶片 ’ - 202-電子元件 ' . 203-基板 204-電子元件 3- 封膠模板 30-頂面 籲 31_底面 32- 模板區塊 320-通孔 321、322-溝槽 323-凸部結構 33- 中空凸罩 4- 晶片模組之封膠方法 籲 40〜44-步驟 90- 封膠材料 91- 刮刀 910-開口13 : C S ^ in turn reduces the chance of wafer damage. In addition: Adhesive electronic components and then the bonding process, because the invention is advanced: the failure of the electronic components to scrap the entire base of the electronic components, ^ the design of the groove 'because it can provide no shadow - / / can increase the substrate The diversity of the circuit layout, the automation of the process of the four electronic components. The description of the present invention is only an embodiment of the present invention 'When it is not possible to change and repair it. #卩大凡 according to the invention _ Please do the uniforms made by the township will not lose the essence of the invention, nor Deviation from the present invention: arsenic and range, should be considered as further implementation of the present invention. The glue side, the above-mentioned "sealing template of the wafer module provided by the invention and its sealing" can make the layout design of the wafer module more flexible to increase the mass production and reduce the production cost when the wafer is sealed. Improve the quality of production. Therefore, it can meet the needs of the industry, and thus improve the competition of the industry: force and drive the development of the surrounding industry. 'Sheng has met the requirements of the invention patent law = the necessary requirements for applying for an invention' I would like to ask the review committee to allow time for the review and grant the patent as a prayer. 1364105 [Simple description of the diagram] Figure 1A to Figure 1D is a schematic diagram of the package process of the conventional wafer module. Figure 1 E is a schematic diagram of the deformation of a conventional packaged wafer module substrate. Figure 2 is a schematic view of the C0B substrate. FIG. 3A is a schematic perspective view of a sealing template of the wafer module of the present invention. Figure 3B is a perspective view showing the structure of the bottom surface of the sealant template of the present invention. Figure 4 is a schematic cross-sectional view of one of the module blocks and its corresponding C0B chip module. FIG. 5 is a schematic flow chart of the sealing method of the wafer module of the present invention. 6A to 6F are schematic cross-sectional views showing the stages of the sealing process of the wafer module of the present invention. 7A and 7B are schematic views showing another embodiment of the encapsulation stencil of the wafer module of the present invention. [Major component symbol description] 10_ wafer 11-substrate 12 - metal line 13 - template 14 - via 15 - encapsulant 16 - electronic component 2-C0B substrate 15 1364105 20-COB wafer module 201 - wafer ' - 202-electronic component'. 203-substrate 204-electronic component 3-sealing template 30-top surface 31_ bottom surface 32- template block 320-through hole 321, 322-trench 323-protrusion structure 33-hollow convex Cover 4 - Chip Module Sealing Method Call 40~44 - Step 90 - Sealing Material 91 - Scraper 910 - Opening