TWI358893B - Quarter-rate clock recovery circuit and clock reco - Google Patents

Description

1358893 17621pif.doc IX. Invention Description: . Group Mountain:: The case is claimed to be the priority seat of the Korean Patent Application No. 2_-61262 of the Korean Intellectual Property on August 4, 2004. The contents disclosed in the patent application are fully incorporated in the present specification. °Hai [Technical Field of the Invention] Shuming is a kind of clock recovery circuit, and special kind of quarter-rate clock recovery circuit and using this j material recovery method. j 崎脉贡 • [Prior Art] In general, the parallel circuit is more difficult to design than the serial power (-it). Therefore, in order to save the cost of wiring and interconnection and/or to avoid noise (for example, cross-talk noise of (4) circuits, in parallel, rather than in parallel, two remote devices Inter-transmission digital data has become the latest trend in serial data transmission, where data is transmitted at high speed by, for example, single optical fiber φ (optlcal flber), coaxial or twisted-pair cable. Multiple lines simultaneously transmit several data streams. To reduce cost, the receiver can use the clock recovery circuit (CRC) to reply to one bit stream of the received high-speed digital data. Pulse, instead of transmitting the clock to the remote receiver synchronized with the serial high-speed digital data. The traditional clock recovery circuit (Crc) can use a phase locked loop (pll) or delay locked loop 6 1358893 17621pif.doc (delay locked loop » DLL) The block diagram in Figure 1 shows the use of a phase-locked loop (p traditional clock recovery circuit. The slave device (multiplexe〇12G) The receive-reference frequency clock (1) is used as an input. The reference frequency clock 11G can be generated by a crystal oscillator which can generate a relatively frequency clock to provide to the multiplexer 120. 〇The reference frequency clock 11Q can generate a high frequency clock through the __ feedback loop. The feedback loop can include a frequency phase (four) device (Calta deteCt〇r) Π0, loop filter 140, a voltage Controlled oscillation = (VCO) 150 and / or a frequency divider 160. When the high frequency clock reaches the frequency, the serial input data 100 instead of the reference frequency clock No can be input to the phase-locked loop (PLL) by the multiplexer 12〇. 时 The clock 180 synchronized with the serial input data 100 can be input and output from the vc〇150. The clock can be input with the serial data. 1〇〇 is commonly applied to the trigger (handsome flop) 170' and a clock data 19〇 can be output from the flip-flop 17〇. In a nutshell, 'If a high-speed serial input data phase is input to the phase-locked loop (PLL) towel And the high speed serial input data has jitter Phenomenon (jitter) 'The PLL must be adapted to provide a clock synchronized with the high-speed serial input data in a short time. The performance of the beta clock recovery circuit depends on the performance of the phase-locked loop (PLL). Higher performance PLLs can be difficult because this can require a large amount of power loss and/or a large die area, thus increasing noise.曰', to solve the above problems can use phase interpolation. The phase insertion technique is a clock generation method in which the phase is between the first and first phases of the two input clocks. For example, a clock having a phase of 〇 to 9 可 degrees may be generated based on a first clock having a twist phase and a second clock having a phase of 9 degrees. • In particular, the half-rate clock recovery circuit that uses four clocks to perform phase insertion is a traditional clock recovery circuit. The four clock recovery circuits may include a reference clock having a half frequency of the input data and three clocks having a phase difference of 90 degrees, 180 degrees, and 270 degrees with respect to the reference clock, respectively. The half rate clock recovery circuit can solve one or more of the problems in circuit design. It increases its operating speed by reducing its operating frequency. Traditionally, there are at least two types of half-rate clock recovery circuits, the φth half-rate pulse recovery circuit uses at least two phase-locked loops (PLLs), and the second half-rate clock recovery circuit uses a single lock. Phase loop (PLL·), which produces four half rate clocks I, Q, Ib, and Qb with a 90 degree phase difference. The traditional half rate clock recovery circuit for private data bandwidth can use a multi-channel structure instead of a signal channel structure. The multi-rate structured half rate clock recovery circuit may have a parallel arrangement of transmit/receive channels 4' such as 4-way, 8-way, 16-way parallel channels. 8 893 893 17621pif.doc A half-rate clock recovery circuit using at least two phase-locked loops (PLLs) may require significant power loss and/or large die area. In comparison, a half-rate clock recovery circuit using a single phase-locked loop (PLL) can include a voltage controlled oscillator (VCO) that is capable of generating a high frequency corresponding to increasing the data transmission speed and increasing the number of channels to produce The four phases have a 90 degree phase difference clock to transmit these four clocks to each channel. The block diagram of Figure 2 illustrates a prior art or prior art publication of a clock recovery circuit for the period of 9 years U. The serial input data 201 and the reply clock 202 having the half rate of the serial input data 2〇1 can be supplied to the phase detector (phase deted〇210). The phase detector 210 can compare the two input signals. The phase difference between 2〇1 and 202, and outputting an up/down signal 215 according to the comparison result. The uplink/downlink signal 215 can be provided to the signal separator 220, and the signal φ separator 220 can be The low-rate uplink/downlink signal 225 is output, and the signal can be used in a digital-to-analog converter (DAC) control logic 230. The DAC control logic 230 can be based on the uplink/downlink signal output by the signal separator 220. The digital control code 235 is output 225 to perform phase insertion of the reply clock 202. The digital control code 235 can be provided to the phase insertion unit 250 via a plurality of digital to analog converters (DACs). 9 17621pif.doc Multiple DACs 240 A non-linear DAC is included, which has a non-linear conversion characteristic 'compensable for nonlinear characteristics of the digital control code 235 when the digital control code 235 output by the DAC control logic 23G does not vary linearly The phase insertion unit 250 can perform the phase insertion according to the weight of the output of the DAC 240 (the weight \ control signal 245 is applied to the four clocks 265 outputted by the clock generator 26〇) and can output the output clock to follow the sequence. The phase of the input data 201. The output clock 2 〇 2 output by the phase insertion unit 250 can be fed back to the phase detector 210. The half rate clock recovery circuit can perform phase on the clock having the half frequency of the serial input data 201. And, for example, when the rate of the serial input data 201 is about 85 Gbps, the phase insertion unit 250 pairs 帛-, 帛2, 3, and 4 with the half-frequency (4.25 GHz) of the serial input data. The clock execution phase insertion second clock has a phase difference of 9 degrees with respect to the phase of the first clock, the first clock has a phase difference of 18 degrees with respect to the phase of the first clock, and the fourth clock The phase difference with respect to the phase of the first clock has a phase difference of 270. The phase detector 210 detects the phase difference between the 8.5 Gbps serial input data 2〇1 and the first/second clock provided by the phase insertion unit 250. Although not shown in Figure 2, another situation Yes, the phase detector 210 can multiplex the serial input data stream 2〇1 into two data streams 270 having half the frequency of the serial input data unit 201 to have a phase relative to the first % pulse. The second clock of the 90 degree phase difference and the fourth clock having a phase difference of 270 degrees with respect to the phase of the first clock are used to reply to the data. 1358893 17621pif.doc But when the data rate (or data transmission rate) increases The traditional half-rate clock recovery circuit may have problems. There are at least two ways to generate four clocks with a half-frequency (4.25 GHz) of serial input data 2 〇 1 and a phase difference of 90 degrees from each other to provide the four clocks to each channel, as follows Said. It should be noted that a ring oscillator (ring 〇scillat〇r) cannot be used to generate frequencies between 3 GHz and 4 GHz. In the first method, an 8.5 GHz local voltage controlled oscillator (VCO) can be implemented when the data transfer rate is 8.5 GHz. This 8.5 GHz seismic frequency can be divided into two halves, four clocks having a frequency of 4.25 GHz and having a phase difference of 9 相互 between each other, for example, using a flip-flop. y In the second method, when the data transmission rate is 8.5 GHz, four clocks having a frequency of 4.25 GHz and having a phase difference of 9 相互 are used, for example, a 4.25 GHz local voltage controlled oscillator (VC0) and a Produced by a poly-phase filter. In both methods, four φ having a phase difference of 9 degrees from each other are transmitted to each channel. However, it is more difficult to perform a phase-locked loop (pLL) operating at a higher frequency corresponding to the required data transmission speed and/or having the desired jitter characteristics. Moreover, transmitting four clocks to each channel may result in significant power loss, line mismatch, and/or tie-in effects, as power loss, line mismatch, and/or loss effects may increase. The ratio of frequencies. Thus, if you do not use clock buffer n (clockbuffer), you may limit the transmission distance of 1762Ipif.doc. The increase in the consumption of the stimulator will result in a wafer area and/or power loss that is large, and a power supply must be arranged in the plan view of the larger green sheet. Two: two considerations 发明 [Summary] ϋ Contact and ground voltage contacts. In real_中的—the clock recovery circuit includes: a clock generation benefit, which is suitable for generating the data speed of the input data of the first and third azoles; the second=pulse and Ϊ^; the second and third The fourth clock executes the phase ί: == fifth, sixth, seventh of the frequency, the eighth time 45^90^135: the fifth bj bit detection state 'its suitable for output corresponding to the input data The signal of the phase difference between the 22nd and the 8th clock; and the signal of the heart control == detector output, and generate the control clock, -. /, 迥 to produce the first, second, third And the fourth pulse and four, the data rate of the input data has a quarter frequency of 90 and the phase of the fourth clock relative to the first clock is respectively transferred to the day_1 difference; at least - A clock recovery circuit, which is suitable for receiving the first, second, third and fourth 12 1358893 17621 pif.doc clocks, and is adapted to reduce the data rate of the input data by using a reply clock signal to provide more De-multiplexing data to multiple channels; and a controller that inserts a phase based on the signal output from the phase detector Line control. The clock recovery circuit includes a phase insertion unit having a first phase interpolator adapted to receive the first, second, third, and fourth clocks to generate a fifth clock, the fifth The phase of the clock and the longitudinal input data and having a quarter-frequency of the data rate of the input data; the second 'suitable for generating the sixth clock' having a phase difference of 5 degrees with respect to the phase of the fifth clock; a third phase interpolator adapted to generate a seventh pulse 'having a phase difference of 9G degrees with respect to a phase of the fifth clock. The four phase = input 'is adapted to generate an eighth clock relative to the fifth clock Avoid phase

2 135 degrees phase difference on Si. The clock recovery circuit further includes a phase 'which is adapted to receive the input data and the fifth and sixth day: pulse' to output a signal corresponding to her difference between the input data/time. I #七和弟八 includes this dew - a light _ method of the real _, this method - the second rate t of the data rate of the quarter - the frequency of the first relative to the first main - four clocks Second, third, and fourth time difference; phase of production and 270 degrees, fifth stage, r/r clock of sixth frequency ^ sixth, seventh, and second === 13 1358893 17621pif.doc The above-described and other objects, features and advantages of the present invention will be apparent from the following description of the preferred embodiments of the invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The detailed description of the embodiments of the present invention, the specific structural and functional details disclosed in the specification are disclosed. However, the present invention can also be: = 8.1 is limited to the embodiments listed in the present specification. His form of influence is implemented! To various improvements and to it, and in the second Ming 2_ by Fan Qi shown in the illustration slot invention and " odd detailed description. However, it should be understood that the present invention is out of scope. The entire description of the drawings "all modifications, equivalent forms and other shapes of the same type H designate the same elements. f ΐίϋ _ 'Although the first and second terms are used in this specification ^ are these components It should not be limited to the use of the condition of the range τ. Ma's in the invention may also be referred to as the second element, and the second element is a term used in the book. "and/or, including any and all surnames of the relevant enumerated items. Understand that when referring to a - element, this cloud is π 士 从 , ± 仪 镬 镬 镬 镬 镬 镬 ± ± ± ± ± ± ± 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 (interveningelement). Conversely, when it is mentioned that the element is "directly connected," or "directly coupled, to another element, there is no insertion element. Other words used to describe the relationship between the elements should also be Interpret in the same way (ie, "between," "directly between": contiguous,,, etc.). The terminology used in the 1st state of the United States and the text of this book is only for the purpose of describing a particular embodiment, and 2 is limited to the present invention. The singularity of the use of the singularity of the singularity of the singularity of the book, the singularity of the book, the singularity of the book, the singularity of the singularity of the book 3. Including "and/or" having "the" is intended to mean the presence of the features, steps, operations, components, and/or components, but does not exclude the presence or the , operations, components, components, and/or groups thereof. Unless otherwise stated, all terms (including, technical and scientific terms) used in the specification are the same as those of those skilled in the art. It can be further understood that 'as defined by the $ language used in the dictionary ^, the meaning of the term should be consistent with the meaning of the context of the related technology #, and should not be too idealized or too formal, unless It is clearly stated in the manual. In the case of some other implementation methods, the recorded Wei/Action can be entered in the reverse order of the recording order in the stream (4) = for example, 'continuous display (four) two blocks can actually be executed almost simultaneously, The blocks may sometimes be executed in the reverse order, depending on the function/15 1358893 17621pif.doc, and the block diagram in 3 depicts a quarter-rate clock recovery circuit in accordance with the present invention. (d) The pulse generator, for example, generates four clocks having a quarter frequency of the data rate of the received data 301. The flute can include: a first time clock 365a having a twist phase; a flute ri ^ 365b' having a phase of 90 degrees with respect to the phase of the first clock; ^ & 365C, which is relative to the first - the phase of the clock has 180 degrees phase 〇 = vertical and fourth clock 365d, which has a phase of 27 〇 complete = material W with respect to the phase of the first clock, and these four clocks can have a body When the data rate is low, the daily pulse generator 3 causes a delay locked loop (DLL) including the oscillator. Another - the rate is w, Β ± ΗΛ. In another case, when receiving data (vom 36G can be used - local pressure controlled oscillator LVCO) and a trigger.四个 Four clocks 365a 5, 丨 35〇. This phase insertion can be provided to the phase insertion unit to perform phase mapping, which can be divided by the four clocks 365a to 365d - fm, 'to output the four 302a μ frequencies having the data rate of the received data 301 and synchronized The fifth clock of the received data 3G1 == the phase of the fifth clock shift a has a phase difference of 45 degrees; the seventh phase of the difference of the second clock 302; the phase of the 4 fa has a phase of 9 degrees c, and relative to the The phase of the fifth clock 3〇2a has 16 1358893 17621pif.doc The eighth clock with a phase difference of 135 degrees is 3〇2d. The phase inserters 3M, 3S2, .353, and 354 included in the phase inserting unit 35A can generate four clocks having the four data of the received data 301, and the four times. 45 degree phase between veins

After the control signal of the phase of the fifth clock 3〇2a is determined, the signal signals of the eight clocks, the seventh clocks 3〇2c, and the eighth clocks 302d can be applied to the three clocks according to the four clocks. 〇2d is determined by the basis of 4 = position difference. Thus, the four phase inserter detents, 352 353 and 354 can be easily controlled by generating control in accordance with the typical method described above. The phase insertion control benefit 320 determines the control method of the phase inserters 351 to 354 included in the phase insertion unit 35A. 〇

The fifth clock 302a to the eighth clock 302^ output by the phase insertion unit 350 can be supplied to the phase detector 31(), and the phase controller applies the phase of receiving the poor material 301 and the four clocks to the middle. Each phase of the comparison is compared: and the data rate of the reception 301 is reduced by performing ^ (e.g., η is 4) for the received data 3〇1 to output the n reply data streams 37〇. 〇

In another embodiment, η may be twenty or forty, so that the input data can be converted according to the township JL to twenty or forty data streams, and the detector 310 can compare the received data. The phase and phase of 3〇1 are inserted into each of the four phases 302a to 302d of the single-turn 350 output, 17 1358893 J7621pif.doc, and it is determined that each of the four clocks applied to the side is super rainy to receive. The phase of the data is still behind the phase of the received data. Although each phase in the application of the clock is ahead of the reception, the phased device 31G can output the phase of each of the phases in the negative downlink signal 302ai"02d receiving the lean 3〇1 phase. The tester 31 can output a valid uplink signal. In the other embodiment, the term "uplink signal" is compared with the "downlink signal," and the phase can be performed on the single circuit block shown in FIG.

Si : Off function. Alternatively, phase detection and multiplex separation can be performed on discrete circuit blocks. The phase insertion controller 320 can perform operations in different configurations, and the disk phase detector 310 and the phase insertion unit 35G together form a feedback circuit. The block diagram of the input control = ^ indicates that the phase is inserted in another embodiment according to an embodiment of the present invention. Compared with the digital control method shown in FIG. 4, the target = controller 32 can use the - plane ratio. Control methods to perform operations at high operating speeds. For example, the phase insertion controller can perform operations using a charge pump. Referring to Figure 4, the phase insertion controller 32A can include a signal, a digital to analog converter (DAC) (4) logic 42, and a digital to analog converter (DAC) 430. The up signal and the down signal output by the phase flipper 310 can be sent to the signal splitter 410. Ϊ358893 1762lpif.(joc This signal splitter .410 can reduce the frequency of the uplink/downlink signal provided by the phase detector 31. For example, when the frequency is about 2.125GHz, the uplink/downlink is poorly shaken to the signal. In the splitter 410, the signal splitter 41 can convert the downlink signal into a signal having a lower frequency of about 425 MHz. In order to convert the rate of the uplink/downlink signal output by the phase detector 310 into a DAC control The rate of logic 420 can be programmed to reduce the frequency of the upstream/downlink signals, wherein the DAC control logic 420 is operated by complementary metal oxide semiconductor (CMOS) logic. DAC control logic 420 and The plurality of DACs 430 can control the phase insertion unit 35 using the uplink/downlink signals output by the signal separator 410. The DAC control logic 420 can output the control code 425 to a plurality of DAs (: 43 。. This control code 425 can be The DACs 43 are converted into analog control signals and can be used to control the four phase interpolators 351 to 354 included in the phase insertion unit 35A.

φ In an embodiment of the invention, a plurality of DACs may include eight DACs (DAC1 to DAC8). That is, DAC1 through DAC4 can output control signals to control phase interpolators 351, 353 which generate a fifth clock 302a and a seventh clock 302c, respectively. The DACs 5 through DAC 8 can output control signals to control the phase inserters 352, 354 which generate the sixth clock 3〇2b and the eighth clock 302d, respectively. In order to reduce the number of phase interpolators, the DAC control logic 42 can obtain 19 1358893 17621 pif.doc by generating an offset (Qffset) according to the control code for generating the fifth clock to generate the sixth clock to the eighth clock. Control code. The clock control code can use the control code that generates the fifth clock: The DAC control logic 42 can include a k-bit bidirectional (1) coffee shift shift register (Shiftregister) can vary according to the resolution power) . s For example, a -32-bit shift register can be decomposed into 32 partial (step) pulse phases by a quadrant corresponding to the 9-degree phase. Accordingly, the 32-bit shift register can control the clock phase by decomposing the 36 〇 ^ phase into 128 steps. The shifting buffer included in the DAC control logic 420 t can be used to perform the shifting operation of the up/down signal provided by the number separator 410: ° If the control (4) series includes a 32-bit shift scratch volume, Then in the initialization phase '& 32-bit shift staging to find "OOOOOOOOh". "Resist" "When the 32-bit shift register is connected to the _ minute_(four) = effect" signal, the shift register can be shifted to the right, and the most significant bit , MSB) is set to "Γ,. According to the 32-bit shift register, it can receive the signal from the signal separator 4ι〇, "on, the signal, when the bit of the shift register is set to ... η11 '' this shift is temporarily The memory can reverse the transfer bit direction and start to the left private bit, and the least significant bit (10) is set to “〇”. 4 “The j-bit shift register receives the signal from the signal separator 410. When the $down "signal" signal, the shift register can be shifted to the left, and the least significant 1358893 17621pif.doc bit (LSB) is set to "〇,,. According to the 32-bit shift register, a plurality of valid "downlink" signals from the signal separator 4i can be received. When the bit of the shift register is set to "000...000", the shift The scratchpad can reverse the bit direction and start shifting to the right. The most significant bit (MSB) is set to "1." The 32-bit control code can use the 32-bit shift register as a hill. The ball-like sample is generated according to the uplink/downlink signal performing a two-way shift operation, and

The 32-bit control code is used to generate a fifth clock based on the first to fourth clocks 365. The table in Figure 5A illustrates the operation of controlling the phase storage of Figure 4_ in accordance with a digital to analog to four (DAC) controlled touch in accordance with an embodiment of the present invention. In the table shown in Figure 5A, the first column indicates "upstream, signal, and the first column indicates "downstream" signal.

t^DSEL denotes a register value which is selected from the first clock to the fourth clock of the phase inserter 351 of the fifth clock when the two phases have a phase difference of 90 degrees from each other. pulse. The DSEL temporary cry can consist of ::: meta, and the fox register can be included in the DAc control logic control logic 420 can be determined using the DSEL register and the 32 bit shift: register. Corresponds to the -DAc i The high-order cell of the control register to the fourth Dac4 can be used to select the second clock with the degree phase 365b or the fourth clock with the phase of the phase 21 1358893 17621pif.doc 365d 〇 For example, when DSEL When the high bit of the scratchpad is "〇", the second clock 365b is selected. When the high bit of the DSEL register is "i,", the fourth clock 365d is selected. The lower bits of the DSEL register (1 〇) can be used to select the first-clock 365a with a phase of 〇 or the third clock 365c with a phase of (10) degrees. For example, when the lower bit of the DSEL register is ‘‘,, when the first clock 365a is selected, and the lower bit of the DSEL register is “1”, the third clock 365c is selected. Nothing. : When does the shift direction of the private temporary storage $ change in response to the upstream line afl? The tiger DSEL temporary value can be changed to select two clocks in the first to 365 to generate the fifth clock. That is, when the phase of the f D two clocks changes from one quadrant to another, the register value can be changed to indicate a new quadrant. The fourth column in iA represents the state of the shift register, and the fifth to ί four DACs (ie DAC DAC2, er 3 -, _ ^ control code to output separately - weight control signal to the first brother, Brother 2 and the fourth clock 365.

As shown in the table in Figure 5A, the four D generations are generated and the DSEL wheel values are set to set the five clocks. 3. The position of the target is the seventh phase when there is a phase difference with respect to the /, and the phase difference. Pulse 302c. The phase inserter 353 which produces the seventh clock shame at 22 1358893 1762Jpjf.doc can be designed to be ί, and the pulse has a phase of 9 degrees with respect to the clock pulsed by the phase insertion state 351 which produces the fifth clock 302a. difference. In the example, four phase interpolations 54 having phase structures can be executed. Moreover, 16 DACs can be used instead of 8 DACs. = 'relative to the fifth clock phase == (d) can be obtained by the phase 2 Ϊ control code corresponding to the 45 degree relay 3〇2c; relative to the seventh clock should be 45 degrees The eighth clock_ can be obtained by using the pair of codes to generate the control analogy of the seventh time; instead of drawing the digital control according to the present invention to the control logic for the control The seventh = offset can be used to have a 45 degree phase difference based on the generation of the fifth clock and the phase _ phase Γ Γ eight clock phase. The phase of the coffee and the seven clocks 302c = 'When the phase relative to the first - clock ship = the clock 3 〇 2a is generated, the sixth clock _ can be: two = the phase of the pulse 365a has 45 sounds, the first The time-bit 16 bits (or steps), the zero-bit and the fifth-time I: 23 1762ipif.doc and the seventh clock 302c shown in FIG. 5A can be divided into 32 parts. Corresponding to the 9G degree phase knife (or step) 0 means that when the fifth clock phase has a phase difference with respect to the phase of the first clock 365a, -FFFFFFFFh- ΠΔ〇 The control code of η DAC1 whose control code can be 2 can be "__00h". The DAC3 and the 4th generation of the prison 4 are "___,,. Since the sixth clock 302b is applied to the fifth phase, the phase difference is 45 degrees, so the sixth antimony is produced. 3G2b DAC5 control code

It can be "_0 chath", * The control code of DAC6 can be "OOOOFFFFh" so that it has a phase difference of 45 degrees with respect to the phase of the first clock. The control codes of DAC7 and DAC8 are "face-to-face". The control code generated by DAC control logic 420 can be converted to analog control signals via a plurality of dac 430' and can be provided to phase insertion unit 350. As noted above, the plurality of DACs 420 can include a non-linear DAC having non-linear switching characteristics. The block diagram of Figure 6 illustrates the connection between a phase insertion unit and a plurality of digital to analog converter DACs in accordance with an embodiment of the present invention. Phase insertion unit 350 can include four phase interposers 351, 352, 353, and 354. Multiple DACs may include eight DACs (DAC1 to DAC4 and DAC5 to DAC8) and receive control codes 520a, 530a, 540a, 550a, 520b, 530b, 540b, and 550b from DAC control logic 420 to output eight analog control signals 720a, 730a, 740a, 750a, 720b, 730b, 740b, and 750b are incorporated into phase insertion unit 350. 24 1358893 17621pif.doc The first phase inserter 351 of the phase insertion unit 350 can receive the four clocks 365a to 365d provided by the clock generator 360 and the control signals 72A, 730a, 740a and 750a output by the DAC1 to the DAC4. The second phase interpolator 352 of the phase insertion unit 350 can receive the four clocks 365a through 365d provided by the clock generator 360 and the control signals 720b, 730b, 740b, and 750b output by the DACs 5 through DAC8. The third phase inserter 353 of the phase insertion unit 350 can receive the four clocks 365a to 365d provided by the clock generator 360 and the control signals 72A, 73A, 74A and 750a output by the DAC1 to DAC4. The fourth phase inserter 354 of the phase insertion unit 350 can receive the four clocks 365a to 365d provided by the clock generation 360 and the control signals 72〇b, 73〇b, 74%, and 75〇t output by the DAC5 to the DAC8. . The circuit diagram in Figure 7 illustrates a phase interpolator included in a phase insertion unit in accordance with an embodiment of the present invention. Phase insertion unit 350 can include four phase interposers 351, 352, 353, and 354.

The control code output by the φ DAC control logic 420 can be converted to analog control signals by a plurality of DACs 430, and such ratio control signals can be supplied to the phase insertion unit 350. The first phase inserter 351 can generate a fifth clock 3〇2a that tracks the phase of the input negative material 301. The second phase inserter 352 can generate a sixth clock 302b having a phase difference with respect to the phase of the fifth clock 3〇2a, and the second phase inserter 353 can generate a seventh clock 3〇2c, which The phase with respect to the fifth clock 302a has a phase difference of 90 degrees. The quad phase interpolator 25 1358893 17621pif.doc 354 can generate an eighth clock 3G2d having a phase difference of 135 degrees with respect to the phase of the fifth clock shift & As described above, since the control signals for generating the fifth clock and the seventh clock c are the same, the four DACs (DAC1 to DAC4) outputting the control signal for generating the fifth clock can be reused to 302c. For example, the phase inserter 35i that produces the fifth clock 3〇2a and the phase inserter 353 that generates the seventh clock 302c may have different structures such that the clocks generated by them have 9 degrees of mutual Phase difference. Similarly, since the control outputs of the sixth clock 3〇2b and the eighth clock 3 generate the four i==dac8 of the control signals of the sixth clock 3〇2b, the mobile coffee can be used to generate the “clock shift d”. The phase interpolator 354 of the phase inserter 352 and the eighth pulse 302d of the New Zealand clock may have a phase difference of 90 相互 between the different pulses. The phase of the seat is inserted into the single 7C 350 output. The fifth clock 3〇2a to the eighth clock 3〇2d may be supplied to the phase detector 31() to form a feedback circuit. The block diagram in FIG. 8 illustrates the invention of the invention- In the high-speed data receiver of the %-pulse recovery circuit of the embodiment, the material receiving memory 800 of the clock recovery circuit of the embodiment of the present invention may include a plurality of clock recovery circuits. At this time, the pulse recovery power $n 'eight 8 〇 ¥ 之 的 的 的 串 串 串 资料 发生器 发生器 820 820 φ φ φ φ φ φ φ φ φ φ φ φ φ φ φ φ .doc has a phase difference of 90 degrees with each other and has a quarter frequency of the data rate of the received high speed serial. ^ Clock The complex circuits MOq through 81〇_n can typically be coupled to the clock generator 820 and can receive four clocks 830 that are output at a time when the pulse occurs. The plurality of clock recovery circuits 81G.1 through 81G_n can The four recovery clocks with the phase difference between the shots and the eyes separate the high-speed serial data stream 801 into four data streams 840-1 to 84〇-n.

These four reply clocks can be generated by the clock recovery circuits 810-1 to 8l 〇-n, which generate four clocks of the output of $82 。. The 84〇/= pulse recovery circuits 81〇_1 to 81〇-n can output the multiplexed data stream U 4〇-n into an internal circuit 85A. Xigong = internal circuit 850 can divide the multiplexed data stream 840-1 to 84 〇 _n = the tool is separated into a frequency lower than the frequency of the data stream 840-1 to 840-n. Complement the quarter-rate clock recovery circuit, this two: 2! clock recovery circuit can use four phase inserters. The four rates and phases can be generated according to four 1/4 clocks with the data rate of the received data and the phase difference (four) of the 9G degrees. The four 1/4 (four) receiving (four) materials have the received data. The data rate is 'and has a phase difference of 45 degrees from each other. The number of clocks with a phase difference of 45 degrees between each other is the least used (called two I, the device is generated), so the design cost of the phase-locked loop, such as the phase-locked loop, can be reduced. For example, with half-turn rate When the pulse recovery circuit is compared, the operating frequency of the clock generator (eg, vco) can be reduced by half, and/or the clock source with the expected jitter characteristics may be easier to design. The mismatch between lines, and/or the coupling effect can be reduced by reducing the operating frequency of the clock generator, thereby producing a high-quality clock.

Moreover, the use of a multi-channel structure of the quarter rate clock recovery circuit, insertion between the channels and providing clocks to the buffers of each channel is facilitated, and/or the power loss of the buffer can be reduced because of the buffer The number is reduced by y. In addition, the total wafer area can also be reduced. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and it is intended that the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS The block diagram in Fig. 1 illustrates a clock recovery circuit using a phase-locked loop (PL1), prior art or prior art publication dated December 14, 1999. The block diagram in 2 shows a prior art or prior art publication, a half rate clock recovery circuit on December 14, 1999. The block diagram of Figure 3 illustrates a four-one clock recovery circuit in accordance with an embodiment of the present invention. - Phase Interpolation of Embodiments The block diagram of Figure 4 illustrates the controller in accordance with the present invention. 28 1358893 17621pif.doc The tables in Figures 5A and 5B illustrate the operation of the digital insertion to analog converter (DAC) control logic to control the phase insertion unit of Figure 4 in accordance with an embodiment of the present invention. The block diagram of Figure 6 illustrates the connection between a phase insertion unit and a plurality of digit to analog conversion n DACs in accordance with an embodiment of the present invention. The circuit diagram in Figure 7 illustrates a phase interpolator included in a phase insertion unit in accordance with an embodiment of the present invention. The block diagram of Figure 8 illustrates a high speed data receiver using a clock recovery circuit in accordance with an embodiment of the present invention. [Main component symbol description] 100, 201: serial input data 110: reference frequency clock 120: multiplexer 130: frequency phase debt detector 140: loop filter 150: voltage controlled oscillator (vc〇) 160: Divider Xin 170: Trigger 180, 190: Clock 202: Reply Clock 210: Phase Detector 215. Up/down Signal 220: Signal Splitter 225: Low Rate Up/Down Signal 29 1358893 17621pif.doc 230 : Digital to Analog Converter (DAC) Control Logic 235: Digital Control Code 240: Digital to Analog Converter (DAC) 245: Weighted Control Signal 250: Phase Insertion Unit 260: Clock Generator 270: Data Stream 301: Receive Data 310: phase detector 320: phase insertion controller 350: phase insertion units 351, 352, 353, and 354: phase interpolator 360: clock generators 265, 365, 365a, 365b, 365c, 365d, 302, 302a, 302b, 302c, 302d: clock 370: reply data stream UP, DOWN, 315, 345: signal 410: signal splitter 420: digital to analog converter (DAC) control logic 430: digital to analog converter (DAC) 415 : Signal 425: Control Codes 520a, 530a, 54 0a, 550a, 520b, 530b, 540b, 550b: control code 30 1358893 17621pif.doc 720a, 730a, 740a, 750a, 720b, 730b, 740b, 750b: analog control signal 800: high speed data receiver 8 01 . tfj speed string Column lean stream 810-1, ..., 810-n: clock recovery circuit 820: clock generator 830: clocks 840-1, ..., 840-n: data stream 850: internal circuit

31

Claims (1)

1358893 17621pif.doc For the Chinese patent scope of No. 94126168, there is no slash correction. This revision date: 1〇〇1〇月η日日10, application for patent garden: 1. A clock recovery circuit, including: a clock generator, Suitable for generating first, second, third and fourth clocks, which have a quarter frequency of the data rate of the input data, and the second, second and fourth clocks are connected to the first clock The phase has a phase difference of 90 and 270 degrees, respectively; a phase insertion unit adapted to perform phase insertion on the first, second, third, and fourth clocks to generate fifth, sixth, seventh, and eighth, respectively The clock, which has a quarter-frequency rate of the input material>, wherein the fifth clock tracks the phase of the input data, and the sixth, seventh, and eighth clocks are relative to the fifth The clock has a phase difference of 45, 90 and 丨35 degrees, respectively; a phase detector adapted to output a signal corresponding to the phase difference between the input data and the fifth, /, seventh and eighth clocks; And a controller adapted to receive an output signal from the phase detector, And generating a control signal to control the phase insertion unit, wherein the phase insertion unit comprises: a first phase inserter adapted to generate a fifth time according to the control signal and the first, second, third and fourth clocks a phase inserter adapted to generate a sixth clock based on the control signal and the first, second, third, and fourth clocks; the first two-bit position: the inbound state is adapted to be based on the control The number and the first, third, and fourth clocks generate a seventh clock; and the fourth phase inserter, the fourth, fourth, and fourth clocks generate an eighth clock. κ control like brother 2 32 1358893 17621pif.doc for the 94126168 Chinese special touch without a plan, although the original amendment date: 1GG year 1G month 13 2. As described in the patent scope of the first item of the clock recovery circuit, which The clock generator includes a ring voltage controlled oscillator. 3. The clock recovery circuit of claim 1, wherein the clock generation benefit comprises a local voltage controlled oscillator (VCO) and at least one polyphase filter. 4. The clock recovery circuit of claim 1, wherein the phase detector is adapted to receive input data and fifth, sixth, seventh and eighth clocks and according to the input data and 5. The phase difference between the sixth, seventh and eighth clocks outputs an up signal and a line signal. 5. The clock recovery circuit of claim 1, wherein the phase detector output is valid when the phase of the input data lags behind the phases of the fifth, sixth, seventh, and eighth clocks. The downlink signal and an invalid uplink signal; when the phase of the input data leads the phase of the fifth, sixth, seventh and eighth clocks, the phase detector outputs a valid uplink signal and an invalid downlink signal. 6. The clock recovery circuit of claim 1, wherein the phase detector uses the input data and the fifth, sixth, seventh and eighth clocks to reduce the data rate of the input data to Four data streams having a quarter frequency of the data rate of the input data. 7. The clock recovery circuit of claim 1, wherein the controller comprises: 'digital-to-analog converter (DAC) control logic adapted to generate a plurality of control codes to Responding to the uplink signal and the downlink signal; and 33 1358893 17621pifdoc Amendment date: October 13, 100 is the Chinese patent range No. 94126168. There is no slash correction. The at least-digit to analog converter (DAC) is suitable for generating according to the control code. Control signal. 8. The clock recovery circuit of claim 7, wherein the controller further comprises a signal separator, wherein the signal separator is adapted to divide the first frequency of the line signal and the downlink signal to be lower than the first frequency. a second frequency of a frequency and adapted to provide an output signal of the signal splitter to the DAC logic. 9. The clock recovery circuit of claim 8, wherein the DAC control logic is adapted to respond to operation of the second frequency. ??? 10. The clock recovery circuit of claim 7, wherein the control signal of the control phase insertion unit comprises: a first control signal group adapted to control the first phase inserter; a second control a signal group adapted to control the second phase inserter; a third control signal group adapted to control the third phase inserter; and a fourth control signal group adapted to control the fourth phase inserter. The clock recovery circuit according to claim 10, wherein the second control signal group generates the second control signal group according to the generation of the sixth clock U signal and generates a second control signal group according to the generation The first control signal group of the seven clocks is generated; and wherein the fourth control signal group is generated according to the first control signal group that generates the eighth clock. 12. The clock recovery circuit of claim 7, wherein the control codes comprise: a first control signal group adapted to control the first phase inserter and the 34 1358893 17621pif.doc revision date : The first phase inserter without a slash correction; and a second control signal group adapted to control the insertion of the second phase into the fourth phase inserter. I3. The application for the multiplex circuit of claim 12, wherein the first control signal is generated based on a first control signal group that generates a sixth clock minus eight clocks. H.—A high-speed data receiver, comprising: a student advisory' adapted to generate the first, second, third, and fourth clocks, having a quarter-frequency of the data rate of the input data, and a second second And the four clocks have a phase difference of 90, 180, and 270 degrees with respect to the phase of the first-clock; and the MS one, the return circuit's face is connected to the clock generator, and is suitable for the suburbs: The third and fourth clocks, ii are adapted to use the data rate of the reply clock == small input to provide a multiplexed data channel, wherein at least one clock recovery circuit comprises: a phase insertion unit having: a a first phase inserter adapted to receive the first, second, third and fourth clocks to generate a fifth clock, the fifth clock followed by the phase of the input data and having the data of the input data a quarter frequency of the rate; a second phase interpolator adapted to generate a sixth clock having a phase difference of 45 degrees with respect to the phase of the fifth clock; 35 1358893 17621pif.doc Date of revision: 1 On October 13 of the following year, it was the Chinese special for No. 94126168. The range has no scribe line correction. The third phase interpolator is adapted to generate a seventh clock having a phase difference of 90 degrees with respect to the phase of the fifth clock; a fourth phase interpolator suitable for generating The eighth clock, the eighth clock has a phase difference of substantially 135 degrees with respect to the phase of the fifth clock; a phase detector adapted to receive input data and the fifth, the third, the third, and the eighth a clock for outputting a signal corresponding to a phase difference between the input data and the fifth, eighth, seventh, and eighth clocks; and - controlling H' to perform the phase insertion unit according to a signal output from the phase side device Controlling, wherein, the phase interpolator is adapted to generate the fifth clock according to the control signal and the third and fourth clocks; and the second phase is decoupled according to the control signal and ―, second, third, and fourth; the third phase inserter is adapted to generate the seventh clock according to the control mm: the first, third, and fourth clocks; 11 'is suitable for generating the eighth clock based on the control signal and the -, - and four clocks15. A method for clock recovery, comprising: capital, second, third, and fourth clocks, which have input data for the first, third, and fourth clock phases, and There are phase differences of 90, 180 and 270 degrees respectively; the seventh and the "clock, which has the quadruple of the input data, the frequency, the fifth af pulse and the miscellaneous data 36 1358893 17621pif.doc ... Date: October 13, 100 is the Chinese patent range of No. 94126168 without the slash correction phase, and the sixth, seventh and eighth clocks have 45, 90 and 135 degrees respectively with respect to the phase of the fifth clock. a phase difference; generating a control signal for generating fifth, sixth, seventh, and eighth clocks; and performing phase insertion on the first, first, second, and fourth clocks to generate fifth, sixth, The seventh and eighth clocks, wherein the control signals include: a first control signal for controlling a first phase insertion for generating a fifth clock; and a second control signal for controlling a sixth clock. Second phase insertion; a second control signal, used Controlling the third phase insertion of the seventh clock; and a fourth control signal 'for controlling the fourth phase insertion of the eighth clock, and wherein the second control signal is generated according to the first control signal, thereby generating The sixth clock 'the sixth chowder in the first-control dragon execution phase, the phase of the fifth clock generated by the insertion has a phase delay of 45 degrees; the second control signal is generated according to the first control signal, = The first pulse is generated with a phase delay of 9 degrees relative to the first control signal insertion target; and the fourth control: the root f first control signal is generated, thereby generating the eighth time Pulse, the phase of the fifth day of the day when the phase f is phased with respect to the first control signal has a phase delay of lss degrees. The generation of the brother five 37 1358893 17621pif.doc is the Chinese patent scope of No. 94126168 The original date of the amendment is: October 13, 100. 16. The clock recovery method as described in claim 15 of the patent application, wherein the signal includes an uplink signal and a downlink signal. The clock recovery method according to item 16 of the scope, wherein the phase of the input data lags behind the phase of the fifth, sixth, seventh, and eighth clocks, and the signal is valid. The tiger is invalid; when the phase of the rounded data is ahead of the phase of the fifth, sixth, seventh and eighth clocks, the uplink signal is valid and the downlink signal is invalid.