1345195 九、發明說明： 尤其是指一種利用時脈訊號來消除各級暫 【發明所屬之技術領域】 本發明涉及一種控制電路， 存器中殘留電荷之控制電略。 【先前技術】 功能先進的顯示器漸成為現入、治故 _ 7咱費電子產品的重要特色，其中液晶顯 不斋已經魏成為紐f 勒電話、個人數位助理(PDA)、數位相 機、電腦螢幕或筆記型電腦螢幕所虚 泛應用具有高解析度彩色螢幕的顯示 移位暫存器（―娜示面板之驅動謝之-重要壯 構’其用以驅動液晶顯示面板中各級顯示電路，因此移位暫存器之電路設 計對液晶顯示面板之效能具有決定性之影響。 清參閱第1圖’第1圖係先前技術之液晶顯示器中單級移位暫存器1〇 • 之姐結細。棘姉存11 1G锋包含-減區塊（pUll_upseetion)12、 一拉低區塊（pull-down section) 14、一拉低驅動區塊（pull_d_ section) 16 與一拉局驅動區塊（pull-up driving section) 18。該拉高區塊 12 具有一電晶體NT11 ’用以接收一時脈訊號CK與輸出一輸出訊號gout。 該電晶體NT11之閘極電性連接至一節點N3，且該節點N3電性連接至另 —電晶體NT18。電晶體NT18之閘極用以接收一清除訊號CLR^請同時參 閱第2圖，其為第1圖中各節點之訊號時序圖。當該清除訊號CLR為高電 位時，電晶體NT18會被打開而將節點N3所殘留之電荷藉由低電位Vss釋 5 1345195 玫掉⑽，祕先前技術之移㈣存器係在無晝軌雜人的時間内（即 Ma^ time ’每頓畫面輸入的間隔時間）啟動清除峨⑽轉放節點 N3所殘留之電# ’如第2圖穌’清除訊號贴是在驗_級輸出訊號 咖τ㈣與起始訊號STV之間啟動。這樣—來，就必須以外部電源額外 提供該/遗峨CLR ’而且>雜訊號CLR的啟動時社過接近最後一級 輸出訊號G〇UT(La_，也會導致最後-級的電路效能不佳。 • 因此，必須提*一種可利用内部時脈訊號來消除各級中殘留電荷之移 位暫存器’域時脈訊號係在畫面訊號輸入的時間内運作，以克服先前技 術之缺陷。 【發明内容】 本發明之主要目的在於提供-翻⑽辦動I絲雜各級暫存器 中殘留電荷且不影響各級電路效能之控制電路。 ^ 依據本發明之上述目的，本發明提供一種控制電路，其包含複數級暫 存益，每-級暫存器用以分別輸出一輸出訊號，該輸出訊號並做為下一級 動訊號母一級暫存器設有一電晶體用以接收一清除訊號，當清除訊 號為尚電位時’則可藉由該電晶體釋放該級暫存器之殘留電荷。 母一級暫存器可利用相隔一預設數量之暫存器之輸出訊號來做為該級 子盗之清除訊號’該清除訊號只要不與該級輸出訊號或其前一級輸出訊 號同步即可。該級暫存器要輸出該級輸出訊號前，可先釋放該級暫存器之 聋留電荷’使該級暫存器在輸出該級輸出訊號時的電荷耦合效應可降到最 6 1345195 低’因此即可维持各級暫存器輸出訊號的品質。 本發明之控制電路利用内部時脈訊號來控制各級暫存器中之電晶體， 以消除各級暫存器之殘留電荷，且該時脈訊號係在畫面訊號輸人的時間内 運作’故無需之外部電源。本發明之控舰路可有效崎低移位暫存 器中之電荷耦合效應，並可提升暫存器電路的效能與增加其使用壽命。 【實施方式】 請參閱第3圖，第3圖係本發明控制電路之一實施例之結構示意圖。 控制電路30包含複數級暫存器，該複數級暫存器係以串聯方式連接。每— 級暫存器用以分別輸出-輸出訊號，該輸出訊號並做為下—級之驅動訊 號’例如：第1級暫存器302接收起始訊號ST，並輸出一輸出訊號〇mTUTJ 做為第2級暫存器304之驅動訊號；第2級暫存器304接收第1級暫存器 302所輸出之輸出訊號，並輸出一輸出訊號2做為第 3級暫存S 3〇6之驅動訊號’依此類推。各級暫存器同時接收由—時脈訊號 產生器320所產生之一第一時脈訊號⑶與一第二時脈訊Εχ(：κ，藉以控 制各級暫存器訊號輸出之運作。第一時脈訊號ck與一第二時脈訊號xck 互為反相。 在第3圖中，控制電路30所例示之清除訊號CLR係由時脈訊號產生 器320所產生並與起始訊號ST同步。當清除訊號CLR啟動時（即呈高電 位時）’除了第1級暫存器302外’其他各級暫存器之殘留電荷皆會被釋放， 因此可降低各級暫存器在輸出其各別之輸出訊號的電荷耦合效應 (Coupling)。由於此實施例所例示之清除訊號CLR係與起始訊號ST同步， 7 故第1級暫存器如並不接收該清除訊鏡clr，以免影響其輸出訊號 OUTP T_i U常輸出。歸除喊CLR亦可改為與其他任何—級之輸出 訊號同步i編訊號與清除訊號CLR同步之該級偷财接收該清 除訊说CLR ’以維持該級暫存器輸出訊號之正常運作。 請參閱第4圖，第4圖係本發明控制電路之另-實施例之結構示意圓。 控制電路40之各級_上述_路3Q她，而不同之處在於：每一 級暫存益接收各別之清除訊號，且每一級暫存器所接收之清除訊號係為前 兩級暫存__。例如·•第3級働所触之清除訊號咖」 為第及暫存4〇2之輸出訊號咖則^，依此類推，第魏暫存器410 之/月除訊號CLR_N則為第N·2級暫存器之輸出訊號〇υτρυτ—n士 在第4圖中’由於每一級暫存器皆有各別之清除訊號，故每一級暫存 裔皆可在其各別之清除訊號啟動時，釋放掉其内部之殘留電荷。由於在每 •’暫存盜要輸出該級輸出訊號前，前一級暫存器之電荷福合效應最為嚴 重’故利用前峨暫存器之輸出訊縣做為該級暫存器之清除訊號，目的 祕預絲舰暫辆雜麟崎㈣财，絲放驗暫存器之殘留 ?使該、·及暫存器在輪出該級輸出訊號時的電練合效應可降到最低， =此即可維持各級暫存器輪出訊號的品質。每一級暫存器之清除訊號亦可 麵相隔其他數量之暫存器所輸出之輸出訊號，只要不與該級輸出訊號或 其前—級輪出訊號同步即可。 喷參閱第5圖’第5圖係本發明控制電路之單級暫存器之電路結構圖。 °°暫存器50包含-第一時脈訊號拉低電路η、一第二時脈訊號拉低電路 1345195 、一第N+1級輸出訊號拉低電路56與電晶體T卜丁2、T3。電晶體T1 接收驅動訊號叫並用以控制電晶體T2之開啟來翻輸出訊號〇υτ_Ν β 電曰曰體Τ3接收清除訊號CLR，當清除訊號clr為高電位時，電晶體们 被打開’使電晶體T2之閘極電位被拉至低電位％，藉此可釋放電晶體τ2 之殘留電荷。而第N+1級輸出訊號拉低電路56則在第_級輸出訊號為 高電位時’同樣可將電晶體T2之閘極電位被拉至低電位％以釋放電晶體 Ή之殘留電荷。因此，在顯示每一晝面的時間内，每一級暫存器可釋放電1345195 IX. Description of the invention: In particular, it refers to the use of a clock signal to eliminate various stages. [Technical Field] The present invention relates to a control circuit for controlling the residual charge in a memory. [Prior Art] The advanced display has gradually become an important feature of the current electronic products. Among them, the LCD has not become fast, it has become a Newphone, personal digital assistant (PDA), digital camera, computer screen. Or a notebook computer screen with a high-resolution color screen display shift register ("Na's panel driver thank you - important sturdy" is used to drive the display circuits in the LCD panel, so The circuit design of the shift register has a decisive influence on the performance of the liquid crystal display panel. Refer to Fig. 1 'Fig. 1 for the single-stage shift register of the prior art liquid crystal display.姊 姊 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 Up driving section) 18. The pull-up block 12 has a transistor NT11' for receiving a clock signal CK and an output-output signal gout. The gate of the transistor NT11 is electrically connected to a node N3, and the node N3 electrical Connect to the other transistor NT18. The gate of the transistor NT18 is used to receive a clear signal CLR^ Please also refer to Figure 2, which is the signal timing diagram of each node in Figure 1. When the clear signal CLR is high When the transistor NT18 is turned on, the charge remaining in the node N3 is released by the low potential Vss (1), and the prior art shift (4) is stored in the time of the trackless miscellaneous (ie, Ma^). Time 'interval of input per screen') Clear 峨 (10) Recharge the remaining power of node N3 # ' As shown in Fig. 2, the clear signal is activated between the _ level output signal τ (4) and the start signal STV. In this way, it is necessary to provide the /testamentary CLR with an external power supply and the start-up time of the noise signal CLR is close to the last-level output signal G〇UT (La_, which also causes the final-level circuit performance not to be Preferably, it is necessary to provide a shift register that can use the internal clock signal to eliminate residual charge in each stage. The domain clock signal operates during the input of the picture signal to overcome the defects of the prior art. SUMMARY OF THE INVENTION The present invention The main purpose is to provide a control circuit for turning over (10) the residual charge in the I-cell registers and not affecting the circuit performance of each stage. ^ According to the above object of the present invention, the present invention provides a control circuit including a plurality of stages For each temporary storage, each output buffer is used to output an output signal, and the output signal is used as a lower level signal. The first stage register has a transistor for receiving a clear signal, and when the clear signal is still potential. 'The residual charge of the stage register can be released by the transistor. The parent level register can use the output signal of a predetermined number of registers to be the clear signal of the level of the thief' The signal is not synchronized with the output signal of the stage or its output signal of the previous stage. Before the stage register outputs the output signal of the stage, the reserved charge of the stage register can be released first, so that the charge coupling effect of the stage register when outputting the output signal of the stage can be reduced to a maximum of 6 1345195. 'Therefore, the quality of the output signals of the registers at each level can be maintained. The control circuit of the present invention uses internal clock signals to control the transistors in the registers at each level to eliminate the residual charge of the registers at each level, and the clock signal operates during the time when the picture signal is input. No external power supply is required. The control ship of the invention can effectively lower the charge coupling effect in the shift register and improve the performance of the register circuit and increase its service life. [Embodiment] Please refer to FIG. 3, which is a schematic structural view of an embodiment of a control circuit of the present invention. Control circuit 30 includes a plurality of stages of registers that are connected in series. Each level register is used to separately output an output signal, and the output signal is used as a lower level drive signal. For example, the first stage register 302 receives the start signal ST and outputs an output signal 〇mTUTJ as The driving signal of the second level register 304; the second level register 304 receives the output signal output by the first level register 302, and outputs an output signal 2 as the third level temporary storage S 3〇6 Drive signal 'and so on. The buffers of each level simultaneously receive a first clock signal (3) generated by the clock signal generator 320 and a second clock signal (: κ, thereby controlling the operation of the signal output of each level of the register. The first clock signal ck and the second clock signal xck are mutually inverted. In FIG. 3, the clear signal CLR exemplified by the control circuit 30 is generated by the clock signal generator 320 and synchronized with the start signal ST. When the clear signal CLR is started (that is, when it is high), the residual charge of the other levels of the scratchpad will be released except for the first stage register 302, so that the registers at each level can be reduced. The charge coupling effect (Coupling) of the respective output signals. Since the clear signal CLR exemplified in this embodiment is synchronized with the start signal ST, 7 the first stage register does not receive the clear mirror clr, so as to avoid Affects the output signal OUTP T_i U often output. The reverting CLR can also be changed to synchronize with any other-level output signal i-synchronization signal and clear signal CLR synchronization of the level of stealing money to receive the clear message CLR 'to maintain the The stage register output signal works normally. See Figure 4, Figure 4 is a schematic diagram of another embodiment of the control circuit of the present invention. The stages of the control circuit 40 are the same as the above-mentioned _路3Q, but the difference is that each level of temporary storage benefits each. The signal is cleared, and the clear signal received by each level of the scratchpad is the first two levels of temporary storage __. For example, • the level 3 働 清除 清除 清除 清除 为 为 为 为 为 为 为 为 第 第 第 第 第 第 第Then ^, and so on, the first register signal CLR_N of the first register 410 is the output signal of the Nth and 2nd stage registers 〇υτρυτ-n in the fourth picture 'Because each level of the register is There are separate clearing signals, so each level of temporary storage can release its internal residual charge when its respective clearing signal is activated. Because before each temporary storage of the output signal is output, The charge-forcing effect of the first-stage register is the most serious. Therefore, the output of the front-end register is used as the clear signal of the stage register, and the purpose of the pre-wire ship is temporarily mixed with the four-story (four), the silk test. Residue of the scratchpad? The electro-mechanical effect of the register and the register can be reduced to the most when the output signal of the stage is turned off. , = This can maintain the quality of the polling signals of each level of the register. The clearing signal of each level of the register can also be outputted by other numbers of registers, as long as it does not output signals with this level or The front-stage round-out signal can be synchronized. Refer to Figure 5, Figure 5, which is a circuit diagram of the single-stage register of the control circuit of the present invention. The °° register 50 includes - the first clock signal is pulled low. The circuit η, a second clock signal pull-down circuit 1345195, an N+1th-order output signal pull-down circuit 56 and the transistor T, 2, T3. The transistor T1 receives the drive signal and is used to control the transistor T2. Turning on and outputting the signal 〇υτ_Ν β The electric body Τ3 receives the clear signal CLR. When the clear signal clr is high, the transistors are turned on, 'the gate potential of the transistor T2 is pulled to the low potential %, thereby The residual charge of the transistor τ2 can be released. The N+1th output signal pull-down circuit 56 can also pull the gate potential of the transistor T2 to a low potential % to release the residual charge of the transistor when the _ stage output signal is high. Therefore, each stage register can release electricity during the time that each face is displayed.
晶體T2之殘靠荷兩次，如此可降低整體移位暫存器之偏壓效應（伽⑷， 並可提高暫存器電路的效能與增加其使用壽命。 §單級暫存器50之電路結構應用於第3圖所示之控制電路時，則 其輸出訊號贿除訊號CLR时之該㈣存n不接收該絲訊號CLR，故 該級暫存器不需設置電晶體T3。 請參閱第6圖，其為應用單級暫存器50各節點之訊號時序圖。清除訊 號CLR可選擇與起始訊號ST或第Ν·2級、第N_3級等暫存器之輸出訊號 同步，使節點Q之殘留電荷可適時地被釋放，以改善電荷耦合效應。 相較於先前技術，本發明之控制電路利用内部時脈訊號來控制各級暫 存器中之電晶體’以消除各級暫存器之殘留電荷，且該時脈訊號係在晝面 訊號輸入的時間内運作，故無需額外之外部電源。本發明之控制電路可有 效地降低移位暫存器中之電荷耦合效應，並可提升暫存器電路的效能與增 加其使用壽命。 以上所述者僅爲本發明之較佳實施方式，舉凡熟習本案技術之人士援 9 本發明之精神所作之等效修飾或變化，皆涵蓋於 . T印專利範圍内。The residual of the crystal T2 is twice, which can reduce the bias effect of the overall shift register (gamma (4), and can improve the performance of the register circuit and increase its service life. § The circuit of the single-stage register 50 When the structure is applied to the control circuit shown in FIG. 3, the output signal bribes the signal CLR when the (4) memory n does not receive the silk signal CLR, so the stage register does not need to set the transistor T3. 6 is a signal timing diagram of each node of the single-stage register 50. The clear signal CLR can be selected to synchronize with the output signals of the start signal ST or the second level, the N_3 level, and the like, so that the node The residual charge of Q can be released in time to improve the charge coupling effect. Compared with the prior art, the control circuit of the present invention uses the internal clock signal to control the transistor in each stage register to eliminate the temporary storage at each level. Residual charge of the device, and the clock signal operates during the input time of the kneading signal, so no additional external power supply is needed. The control circuit of the invention can effectively reduce the charge coupling effect in the shift register, and Improve the performance of the scratchpad circuit Plus its life. The above embodiments are merely preferred embodiment of the present invention, those skilled in the case covered the technical spirit of the assistance made by the equivalent of the ninth aspect or modified variations, all encompassed. The patentable scope of the printed T.
f圖式簡單說明J 第1圖為先前技術之單級移位暫存器之電路結構圖。 . 第2圖為第1圖中該移位暫存器各節點之訊號時序圖。 第3圖為本發明控制電路之一實施例之結構示意圖。 第4圖為本發明控制電路之另—實施例之結構示意圖。 φ 第5圖為本發明控制電路之單級電路結構圖。 第6圖為第5圖中各節點之訊號時序圖。 【主要元件符號說明】 30'40 控制電路. 302-310、402-410 各級暫存器 320、420 時脈訊號產生器 50 單級移位暫存器 52 第一時脈訊號拉低電路 54 第二時脈訊號拉低電路 56 第N+1級輪出訊號拉低電路 T1-T3 電晶體 CK 第一時脈訊號 XCK 第二時脈訊號 CLR 清除訊號 10 1345195F Schematic Description J Figure 1 is a circuit diagram of a prior art single-stage shift register. Figure 2 is a timing diagram of the signals of each node of the shift register in Figure 1. FIG. 3 is a schematic structural view of an embodiment of a control circuit of the present invention. Figure 4 is a block diagram showing another embodiment of the control circuit of the present invention. φ Fig. 5 is a single-stage circuit structure diagram of the control circuit of the present invention. Figure 6 is a signal timing diagram of each node in Figure 5. [Main component symbol description] 30'40 control circuit. 302-310, 402-410 Level registers 320, 420 Clock signal generator 50 Single-stage shift register 52 First clock signal pull-down circuit 54 Second clock signal pull-down circuit 56 N+1-stage turn-off signal pull-down circuit T1-T3 transistor CK first clock signal XCK second clock signal CLR clear signal 10 1345195
OUTPUT_N ST 各級輸出訊號驅動訊號 起始訊號OUTPUT_N ST level output signal drive signal start signal