TWI237879B - Circuit carrier and bonding pad thereof - Google Patents
Circuit carrier and bonding pad thereof Download PDFInfo
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- TWI237879B TWI237879B TW093109847A TW93109847A TWI237879B TW I237879 B TWI237879 B TW I237879B TW 093109847 A TW093109847 A TW 093109847A TW 93109847 A TW93109847 A TW 93109847A TW I237879 B TWI237879 B TW I237879B
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- bonding pad
- layer
- substrate
- circuit carrier
- solder
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
1237879 五、發明說明（1) 發明所屬之技術領域 本發明是有關於一種線路載板’且特別是有關於一 種線路載板，其表面所配置之接合墊具有一阻障層 (barrier layer)，其可提高接合墊之電移阻抗 (electromigration resistance) ° 先前技術 覆晶接合技術(flip chip interconnect technology )係為一種將晶片（die)連接到承載器 (carrier )的封裝技術，其主要係將晶片之多個銲塾 (pad)，利用面陣列（a r e a a r r a y )的排列方式，配置 於晶片之主動表面（active surface)上，並在各個鐸 塾上分別依序形成球底金屬層（Under Bump Metallurgy, UBM)及凸塊（bump)，其例如為銲料凸塊 (solder bump)，接著將晶片翻面（fiip)之後，再利 用這些凸塊來將晶片之主動表面上的這些銲墊分別電性 及結構性地連接至一承載器（例如基板（s u b s t r a t e )或 印刷電路板（printed circuit board, PCB))之表面 的多個接點。值得注意的是，由於覆晶接合技術可適用 於高接腳數（high pin count)之晶片封裝結構，並具 有縮小封裝面積及縮短訊號傳輸路徑等優點，使得覆晶 接合技術已廣泛地應用在晶片封裝結構，且特別是具有 高腳位之晶片封裝結構。 請參考第1圖’其繪示為習知之一種線路載板的剖面 示意圖。線路載板1 〇 〇包含一基板11 〇、多個接合塾1237879 V. Description of the invention (1) The technical field to which the invention belongs The present invention relates to a circuit carrier board, and in particular to a circuit carrier board. The bonding pads disposed on the surface thereof have a barrier layer. It can increase the electromigration resistance of the bonding pad. The previous technology flip chip interconnect technology is a packaging technology that connects a die to a carrier. The plurality of pads are arranged on the active surface of the wafer using an area array arrangement, and an under-bump metallurgy layer is sequentially formed on each of the tombs. UBM) and bumps, which are, for example, solder bumps, and then after the wafer is turned over (fiip), these bumps are used to electrically and separately pads on the active surface of the wafer. A plurality of contacts structurally connected to a surface of a carrier (such as a substrate or a printed circuit board (PCB)). It is worth noting that because the flip-chip bonding technology can be applied to high-pin count chip packaging structures, and has the advantages of reducing the package area and shortening the signal transmission path, the flip-chip bonding technology has been widely used in Chip package structure, and especially a chip package structure with a high pin position. Please refer to FIG. 1 ', which is a schematic cross-sectional view of a conventional circuit board. The circuit carrier board 100 includes a substrate 11 and multiple joints.
12642TWF.PTD 第6頁 1237879 五、發明說明（2) (bonding pad) 120 (圖僅繪示其一）、一銲罩層 (solder mask layer) 130 及一保護層140，其中基板 1 1 0包含多個導線層、多個絕緣層及多個導電孔 (conductive via )(圖均未繪示），而每一絕緣層係 配置於相鄰兩導線層之間，且每一導電孔係穿過絕緣層 而與至少兩導線層相互連接。此外，這些接合墊丨2 〇係配 置於基板1 1 0之表面1 1 2上’用以分別連接多個銲料塊/ (solder bump ) 1〇 (圖僅繪示其一），例如為覆晶接合 用之凸塊（flip chip bump)，其中接合墊120係可由基 板1 1 0之最外層的導線層所構成。此外，由於基板11 〇之 導線層的材質通常為銅，所以接合墊120之材質亦為銅。 f外’ 1料塊10則是作為基板110與晶片20相連接之接 .、、，=^料塊1 0之材質例如為含鉛銲料或無鉛銲料。 面112且樣輝參圖，銲罩層130係覆蓋於基板110的表 )，開口 具有多個開口 132(圖僅綠示其一 層130可限弟Ϊ = f暴露出局部的接合墊120，其中銲罩 料塊1 0於迴録Γ吁料塊10之底部的流動，以避免相鄰兩銲 合墊1 2 0之間的^ e f 1 〇 W )時彼此熔接，而造成相鄰兩接 面發生氧化，、s ^路。為了防止鋼材質之接合墊120的表 置一保護層I4fi，⑦甘曰在接合塾“Ο之局部暴露的表面上配 值得注意的η ，/、例如為一鎳/金層（N丨/ A u 1 a y e r )。 質之接合塾〗 田使用保護層1 4 0而無法有效地避免銅材 1 4 0之後，在徂$表面發生氧化時’亦可在形成保護層 ”護層140之表面更額外地覆蓋一有機表面12642TWF.PTD Page 6 1237879 V. Description of the invention (2) (bonding pad) 120 (only one is shown in the figure), a solder mask layer 130 and a protective layer 140, wherein the substrate 1 1 0 includes Multiple conductive layers, multiple insulating layers, and multiple conductive vias (none of which are shown), and each insulating layer is disposed between two adjacent conductive layers, and each conductive via passes through The insulating layer is connected to at least two lead layers. In addition, these bonding pads 丨 2 〇 are arranged on the surface 1 1 2 of the substrate 1 10 ′ to connect a plurality of solder bumps / (solder bump) 1 〇 (only one is shown in the figure), for example, flip chip A flip chip bump for bonding, wherein the bonding pad 120 may be composed of the outermost conductive layer of the substrate 110. In addition, since the material of the lead layer of the substrate 110 is usually copper, the material of the bonding pad 120 is also copper. The outer block 10 is used as a connection between the substrate 110 and the wafer 20. The material of the block 10 is, for example, lead-containing solder or lead-free solder. The surface 112 is shown in the drawing, the solder mask layer 130 covers the surface of the substrate 110), and the opening has a plurality of openings 132 (only the green layer 130 is shown in the figure). F = the partial bonding pad 120 is exposed, where The flow of the welding mask material block 10 on the bottom of the recording material 10 is avoided to avoid welding between adjacent welding pads ^ ef 1 〇W between the two welding pads 1 2 0, resulting in adjacent two joints. Oxidation occurred. In order to prevent the surface of the bonding pad 120 made of steel from being provided with a protective layer I4fi, Gan Gan said that it is worth noting η on the partially exposed surface of the bonding pad, such as a nickel / gold layer (N 丨 / A u 1 ayer). After using the protective layer 1 4 0, the copper cannot be effectively avoided after the copper 1 140, when the surface oxidation occurs, the surface of the protective layer 140 can also be changed. Additionally covering an organic surface
1237879 五、發明說明（3)1237879 V. Description of the invention (3)
保護層（Organic Solderability Preservatives， 〇SP )或是一銲料層（圖均未示），用以更有效地將接合塾 1 2 0之表面隔絕於外界之空氣，進而降低接合墊丨2 〇之表 面發生氧化的機率，同時額外增加之銲料層亦有助於鲜 料塊1 0及接合墊2 2 0之間的接合作業。 ' f 請同樣參考第1圖’銲料塊1 0之材質無論是含錯銲料 或是無鉛銲料，銲料塊1 0之成分均會包括踢。在銲料塊 1 〇長期處於高溫及高電流密度的情況下，銲料塊丨〇之内 部的電子遷移（electromigration)將趨於明顯， 導致銲料塊1〇之錫極易與接合墊12〇之銅姓入 化合物 nnter-Metallic corapound， 及接合墊12〇之間。，得注意的*，由二 化合物的結構相當脆弱，導致銲、、銅之"金屬 的接…大幅地降低，接合塾120之間 10及接合墊120時，很容易於銲Ί 月作用於鋒料塊 發生斷裂，因而導致銲料塊丨'〇鱼 0 ^接合墊120之間 接不良甚至中斷。 /、接σ塾1 2 0之間的電性連 發明内玄 因此，本發明之目的就是 具有多個分別連接一銲料塊之:=供—種線路載板，其 有較高之電移阻抗，以減緩接合:^ ’曰且這些接合墊具 化合物的生成速率。 塾及銲料塊之間介金屬 此外，本發明之再一目 3 於連接-銲料塊，並具有較-種接合墊，其適 〜秒阻抗，以減緩接合 1237879 五、發明說明（4) 墊與銲料塊之間介金屬化合物的生成速率。 為達本發明之上述目的，本發明提出一種線路載 板，其適於連接一銲料塊，此線路載板包含一基板與至 少一接合墊，其中接合墊係配置在基板之一表面，用以 連接銲料塊，而接合墊具有一第一銅層、一J且障層及一 第二銅層，其依序堆疊於基板之表面，且阻障層係用以 增加接合墊之電移阻抗。 依照本發明的較佳實施例所述之線路載板，其中銲 料塊之組成成分包含錫，而阻障層之材質係為鈦、鈦鎢 合金、絡或絡銅合金等。 依照本發明的較佳實施例所述之線路載板，更包含 一銲罩層，其覆蓋基板之表面，且銲罩層具有至少一開 口以完全暴露出接合墊，或者是暴露出局部的接合墊。 為達本發明之上述目的，本發明又提出一種接合 墊，其適於配置在一線路載板之一基板的表面，用以連 接一鮮料塊，其中接合塾包含一第一銅層、一阻障層及 一第二銅層，其中第一銅層係配置於基板表面，而阻障 層係配置於第一銅層上，用以增加接合墊之電移阻抗， 且第二銅層係配置於阻障層上，用以連接銲料塊。 依照本發明的較佳實施例所述之接合墊，其中銲料 塊之組成成分包含錫，而阻障層之材質係為鈦、鈦鎢合 金、鉻或鉻銅合金。 基於上述，本發明之線路載板乃是在其接合墊具有 一阻障層，故可增加接合墊之電移阻抗，以減緩在接合A protective layer (Organic Solderability Preservatives, 0SP) or a solder layer (not shown) is used to more effectively isolate the surface of the bonding pad 1 2 0 from the outside air, thereby reducing the surface of the bonding pad 2 2 0 The probability of oxidation and the additional solder layer also helps the bonding operation between the fresh block 10 and the bonding pad 2 2 0. 'f Please also refer to Figure 1 ’The material of solder bump 10, whether it is the wrong solder or lead-free solder, the solder bump 10 will include kicks. Under the condition that the solder bump 10 is at a high temperature and high current density for a long time, the internal electron migration of the solder bump 10 will tend to be obvious, resulting in the solder tin 10 soldering easily with the copper surname 12 of the bonding pad. Into the compound nnter-Metallic corapound, and the bonding pad 120. It should be noted that the structure of the two compounds is very fragile, which leads to a significant reduction in welding, copper, and metal quotations ... greatly reduced. When joining 10 between the joints 120 and the bonding pads 120, it is easy to act on the joints. The frontal block breaks, which results in poor or even interruption of the solder block. / 、 Electrical connection between σ 塾 1 2 0. The purpose of the present invention is therefore to have a plurality of: one for each type of circuit board, which has a high electrical resistance. In order to slow the bonding: ^ 'and said the formation rate of these bonding pad compounds. In addition, another metal of the present invention is connected to the solder block, and has a comparative type of bonding pad, which is suitable for ~ second impedance to slow down the bonding 1237879 V. Description of the invention (4) Pad and solder The rate of formation of intermetallic compounds between the blocks. In order to achieve the above object of the present invention, the present invention provides a circuit carrier board, which is suitable for connecting a solder bump. The circuit carrier board includes a substrate and at least one bonding pad, wherein the bonding pad is disposed on a surface of the substrate and used for The solder bump is connected, and the bonding pad has a first copper layer, a J barrier layer, and a second copper layer, which are sequentially stacked on the surface of the substrate, and the barrier layer is used to increase the electrical resistance of the bonding pad. According to the circuit carrier board according to the preferred embodiment of the present invention, the composition of the solder block includes tin, and the material of the barrier layer is titanium, titanium tungsten alloy, copper or copper alloy. According to a preferred embodiment of the present invention, the circuit carrier board further includes a solder mask layer covering the surface of the substrate, and the solder mask layer has at least one opening to fully expose the bonding pads, or to expose local bonding. pad. In order to achieve the above object of the present invention, the present invention further provides a bonding pad, which is suitable for being disposed on a surface of a substrate of a circuit carrier board for connecting a fresh block, wherein the bonding pad includes a first copper layer, a A barrier layer and a second copper layer, wherein the first copper layer is disposed on the surface of the substrate, and the barrier layer is disposed on the first copper layer to increase the electrical resistance of the bonding pad, and the second copper layer is It is arranged on the barrier layer for connecting the solder bump. According to the bonding pad according to the preferred embodiment of the present invention, the composition of the solder bump includes tin, and the material of the barrier layer is titanium, titanium tungsten alloy, chromium or chromium-copper alloy. Based on the above, the circuit carrier board of the present invention has a barrier layer on its bonding pad, so the electrical resistance of the bonding pad can be increased to slow down the bonding
12642TWF.PTD 第9頁 123787912642TWF.PTD Page 9 1237879
五、發明說明（5) 2!ί ί i ϊ i ί ί化合物的生成速率，進而長時間 芦付師枓塊與接合墊之間的接合強度。 為讓本發明之上述目的、牿微釦 懂，下文特舉一較佳實施例，並配人”，月b更明顯易 說明如了：貫例並配合所附圖 <，作詳細 線路LiL第2A圖：其繪示為本發明較佳實施例之-種 合墊i2:i圖僅繪示其-）、-銲保 ^= 24 0，其中基板210係包含多數個導線層、多數個絕 ί = 電孔（圖均未示）’而每-絕緣層係配 ί Ϊ : 層之間’且每一導電孔係穿過絕緣層而 ;A 層相互連接。此外’這些接合墊2 2 0係配置 Γίϊ曰 面212上，用以連接多個銲料塊10，其例 如為覆_曰曰接合用之凸塊，其中接合墊220具有一第一銅層 210之：2Λ224及一第二銅層2 26 ’其依序堆疊於基板 21〇之表面212上，其中阻障層224的厚度係以約略介於ι # m (微米）至3 “ m (微米）之間為較佳，且第一銅層 係1 =基板210之最外層的導線層所構成，由於基板 、之¥線層的材質通常為銅，所以第一銅層222之材質 亦為銅。另外’銲料塊1 0則是作為基板2 1 0與晶片2 0相連 接之接點，而銲料塊丨〇之材質例如為含鉛銲料或無鉛 料。 鮮罩層2 3 0係覆蓋於基板210的表面212，且銲罩層V. Description of the invention (5) 2! Ί i ϊ i ί The rate of formation of the compound, and thus the bonding strength between the Lu Fushi block and the bonding pad for a long time. In order to make the above-mentioned object of the present invention clear and easy to understand, a preferred embodiment is given below, and it is provided with a person ", month b is more easily and easily explained as follows: with examples and in conjunction with the accompanying drawings <, a detailed circuit LiL Figure 2A: This is a preferred embodiment of the present invention-a kind of mat i2: i diagram only shows its-),-solder protection ^ = 24 0, where the substrate 210 includes a plurality of wire layers, a plurality of绝 ί = electrical holes (not shown in the figure) 'and each-insulating layer is equipped with ί: between layers' and each conductive hole is passed through the insulating layer; layer A is connected to each other. In addition, these bonding pads 2 2 0 is configured on the surface 212 to connect a plurality of solder bumps 10, which are, for example, bumps for bonding, wherein the bonding pad 220 has a first copper layer 210: 2Λ224 and a second copper The layer 2 26 ′ is sequentially stacked on the surface 212 of the substrate 21. The thickness of the barrier layer 224 is preferably between approximately 1 μm (micron) and 3 ”m (micron). A copper layer is composed of the outermost conductive layer of the substrate 210. Since the material of the substrate and the wire layer is usually copper, the material of the first copper layer 222 is also Copper. In addition, the solder bump 10 is used as a connection point between the substrate 2 10 and the wafer 20, and the material of the solder bump 10 is, for example, lead-containing solder or lead-free solder. The fresh cover layer 2 3 0 covers the surface 212 of the substrate 210, and the solder cover layer
1237879 五、發明說明（6) 2j 〇具有多數個開口 2 3 2 (圖僅繪示其一），開口 2 3 2係暴 路出局部的接合墊2 2 0，亦就是說，在第2A圖中，接合塾 2 2 0人為一鋒罩定義（Solder Mask Define, SMD)類型之 $ ^塾2 2 0 ’其中銲罩層2 3 〇係可限制住銲料塊丨〇之底部 、:L以避免相鄰兩銲料塊丨〇之間彼此連接而造 鄰兩接合墊2 2 0之間的短路。 化，彳ΐ :防止接合墊2 2 〇之第二銅層2 2 6的表面發生氧 出之ί ί層24〇係配置於接合墊2 2 0之第二銅層226的暴露 ί t ^田而保護層24〇例如為一錄/金層。值得注意的 Ξ銅；2匕保，層匕0?無法有效地避免接合㈣〇之第 後，在保罐面毛生乳化時’亦可在形成保護層2 4 〇之 (〇sp }、或者曰，額外地覆蓋一有機表面保護層 接合塾2 2 〇隔二於二界丄而，均未示），用以更有效地將 二銅層226ή6、ί外界ί工乳，進而降低接合墊22〇之第 層亦有助於、銲料面二生氧化人的機率，同時額外增加之銲料 由於塊及接合墊22〇之間的接合作業。 性，所“；合金）具有較佳之焊接特 鉛銲料或無鉛銲料，銲料為錫鉛合金，但不論是含 因此，在銲料塊10長期處於古t組成成3會包含i 0 下，銲料塊10之内部的電子溫及高電流密度的情況 銲料塊10之锡極易斑接移將趨於明顯，因而導致 生成介金屬化合物；銲；J 20之第-銅層222的銅結合 值得注意的是，為及接合墊2 2 0之間。 為了減緩銅及錫之介金屬化合物層1237879 V. Description of the invention (6) 2j 〇 has a plurality of openings 2 3 2 (only one of which is shown in the figure). The opening 2 3 2 is a local bonding pad 2 2 0, that is, in FIG. 2A In the joint, the joint 塾 2 2 0 artificial one mask type (Solder Mask Define, SMD) type $ ^ 塾 2 2 0 'Where the solder mask layer 2 3 〇 can limit the bottom of the solder block 丨 〇: L to avoid Adjacent two solder bumps are connected to each other to create a short circuit between two adjacent bonding pads 2 2 0. To prevent the occurrence of oxygen evolution on the surface of the second copper layer 2 2 6 of the bonding pad 2 2 0, the layer 24 0 is exposed to the second copper layer 226 of the bonding pad 2 2 0 The protective layer 240 is, for example, a recording / gold layer. It is worth noting that the copper is not protected; the two layers can not effectively avoid joining the second layer, and when the surface of the can is emulsified, the protective layer can also be formed (2sp) (0sp), or In other words, an organic surface protective layer is additionally covered (2 2 0 is separated from the second boundary) (both are not shown), to more effectively separate the second copper layer 226 and the outside milk, thereby reducing the bonding pad 22 The second layer of 〇 also contributes to the probability of secondary oxidation of the solder surface, and at the same time, the additional solder is due to the bonding operation between the block and the bonding pad 22o. (Alloy; alloy) has better soldering special lead solder or lead-free solder, the solder is a tin-lead alloy, but whether it contains it, the solder block 10 has been in the ancient t composition for a long period of time, and 3 will include i 0, the solder block 10 In the case of the internal electronic temperature and high current density, the tin spot of the solder bump 10 will tend to be obvious, which will cause the formation of intermetallic compounds; soldering; the copper bonding of the 20th-copper layer 222 of J 20 is worth noting that , And between the bonding pad 2 2 0. In order to slow down the intermetallic compound layer of copper and tin
!237879 五、發明說明（7) 生成於鮮料塊1 0及接合塾2 2 0之H aa 土 銲料塊10及接合墊22〇之間的的速率，以長期地維持 乃是拉ώ 3的接σ強度，故本較佳實施例 精由增加接合墊2 2 0之 ，」 先之第一铜展甘丄1丨早H2 4及第二銅層2 2 6於原 ^ 荆層222上，其中阻陸js99/fTi μ _ ^ 成方式可為雷供< id.、 日224及苐二銅層226之形 V工、(plating)笨， 係為鈦、鈦鹤合金、鉻或2鉻)錮專人八並且阻障層224之材質 之電移阻抗，廿收俏技1 *銅口至，用以提高接合墊2 2 〇 逮率一因tf塾22〇内之銅通過阻障層224的 ^成：^ ^ ^及鮮料塊心間介金屬化合物 密度的产π拉1b田銲料塊10長期處於高溫及高電流 緩錄及^人，这t具有阻障層224之接合墊2 20將可減 ίϊί:二ΐ金屬化合物的生成速率，故可長時間地保 付~抖塊10與接合墊2 2 0之間的接合強度。 凊同時參考第2 A、2 Β圖，其中第2 Β圖繪示為本發明 1佳實施例之另一種線路載板的剖面示意圖。相較於第 圖之線路載板201的銲罩定義（Solder Mask Define， MD)類型之接合墊22〇，第2]5圖之線路載板2〇2的銲罩層 ^0之開口232係暴露出全部的接合墊220，故第2B圖之接 a 塾 220 係為一非鮮罩定義（N〇n — s〇ider Mask Define， nsmd)類型之接合墊22〇。此外，第2B圖之接合墊22〇同 樣具有一第一銅層222、一阻障層224及一第二銅層22， 其依序配置於基板210之表面212。 任何熟知本發明之技藝者皆可知悉，本發明之線路 載板可以應用於晶片與封裝載板（package carrier)之 間的連接型態（例如覆晶接合型態），使得線路載板之! 237879 V. Description of the invention (7) The rate generated between the fresh material block 1 0 and the joint 塾 2 2 0 H aa earth solder block 10 and the joint pad 22 °, in order to maintain it for a long time, it is a free 3 Σ strength, so the preferred embodiment is to increase the bonding pad 2 2 0, "the first copper exhibition Gan 1 1 early H 2 4 and the second copper layer 2 2 6 on the original ^ Jing layer 222, The formation method of the land resistance js99 / fTi μ _ ^ can be a lightning supply < id., Japan 224, and the second copper layer 226 in the form of a V system, (plating), which is titanium, titanium crane alloy, chromium or 2 chromium ) 锢 Specialist and the electrical resistance of the material of the barrier layer 224, close the skill 1 * copper port to improve the bond pad 2 2 〇 because the copper within the tf 塾 22 〇 through the barrier layer 224成 成: ^ ^ ^ and the density of the fresh metal block intermetallic metal compound density π pull 1b field solder block 10 long-term high temperature and high current slow recording and ^ person, this t has a barrier layer 224 of the bonding pad 2 20 This will reduce the formation rate of the difluoride metal compound, so the bonding strength between the shaking block 10 and the bonding pad 2 2 0 can be guaranteed for a long time.凊 Referring to Figures 2A and 2B at the same time, Figure 2B is a schematic cross-sectional view of another circuit carrier board according to a preferred embodiment of the present invention. Compared with Solder Mask Define (MD) type bonding pad 22 of the circuit carrier board 201 in FIG. 2, the opening 232 of the solder mask layer ^ 0 of the circuit carrier board 202 in FIG. 5 is shown in FIG. 2. All the bonding pads 220 are exposed, so the connection 220a in FIG. 2B is a non-snider mask defined (nsmd) type bonding pad 22o. In addition, the bonding pad 22 of FIG. 2B also has a first copper layer 222, a barrier layer 224, and a second copper layer 22, which are sequentially disposed on the surface 212 of the substrate 210. Any person skilled in the art of the present invention can know that the circuit carrier board of the present invention can be applied to a connection type (such as a flip-chip bonding type) between a chip and a package carrier, so that the circuit carrier board can be
1237879 五、發明說明（8) 接合塾可作為凸塊塾（b u m p p a d )。此外，本發明之線 路載板亦可應用於封裝載板與電路板（circuit board) 之間的連接，例如球格陣列（B a 1 1 G r i d A r r a y， B G A ) 接合型態，使得線路載板之接合墊還可作為銲球塾 (b a 1 1 p a d )。另外，本發明之線路載板的接合墊更可 應用來連接一般表面黏著型（SMT )之電子元件的接點 (例如接腳或電極），故本發明之線路載板亦可應用於 一般之印刷電路板（PC B )。 綜上所述，由於本發明之線路載板的接合墊具有一 阻障層，其用以增加接合墊之電移阻抗，並降低接合墊 之第一銅層的銅之擴散經過_其阻障層的速率，因而減緩 銲料塊與接合墊之間之介金屬化合物的生成速率，並可 有效地減缓接合塾内之銅的消耗，進而長時間地維持銲 料塊與接合墊之間的接合強度。因此，當本發明之線路 載板的接合墊以表面黏著技術（SMT )來連接一電子元件 之接點時，線路載板之接合墊及電子元件之接點間的電 性及結構性連接（特別是電性連接）將可維持較長的時 雖然本發明已以一較佳實施例揭露如上，然其並非 用以限定本發明，任何熟習此技藝者，在不脫離本發明 之精神和範圍内，當可作些許之更動與潤飾，因此本發 明之保護範圍當視後附之申請專利範圍所界定者為準。1237879 V. Description of the invention (8) The joint 塾 can be used as a bump 塾 (b u m p p a d). In addition, the circuit carrier board of the present invention can also be applied to the connection between a package carrier board and a circuit board, such as a ball grid array (B a 1 1 Grid Aray, BGA) junction type, so that the circuit carrier The bonding pads of the board can also be used as ba 1 1 pads. In addition, the bonding pads of the circuit carrier board of the present invention can be further used to connect the contacts (such as pins or electrodes) of general surface mount (SMT) electronic components, so the circuit carrier board of the present invention can also be applied to general Printed circuit board (PC B). In summary, since the bonding pad of the circuit carrier board of the present invention has a barrier layer, it is used to increase the electrical resistance of the bonding pad and reduce the diffusion of copper through the first copper layer of the bonding pad_its barrier Layer, thus slowing down the generation rate of the intermetallic compound between the solder bump and the bonding pad, and can effectively slow down the consumption of copper in the bonding pads, thereby maintaining the bonding strength between the solder bump and the bonding pad for a long time. . Therefore, when the bonding pads of the circuit carrier board of the present invention are connected to the contacts of an electronic component using surface mount technology (SMT), the electrical and structural connections between the bonding pads of the circuit carrier board and the contacts of the electronic component ( In particular, the electrical connection) can be maintained for a long time. Although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art will not depart from the spirit and scope of the present invention. However, some changes and retouching can be made, so the scope of protection of the present invention shall be determined by the scope of the appended patent application.
12642TWF.PTD 第13頁 1237879 圖式簡單說明 第1圖繪示為習知之一種線路載板的剖面示意圖。 第2 A圖繪示為本發明較佳實施例之一種線路載板的 剖面示意圖。 第2 B圖繪示為本發明較佳實施例之另一種線路載板 的剖面示意圖， 【圖式標示說明】 10 ： 銲料塊 20 ： 晶片 100 線 路 載 板 110 基 板 112 表 面 120 接 合 墊 130 銲 罩 層 132 開 α 140 保 護 層 201， •202 :線路載板 210 基 板 212 表 面 220 接 合 墊 222 第 一 銅 層 224 阻 障 層 226 第 二 銅 層 230 焊 罩 層 232 開 Ρ12642TWF.PTD Page 13 1237879 Brief Description of Drawings Figure 1 shows a schematic cross-sectional view of a conventional circuit carrier board. FIG. 2A is a schematic cross-sectional view of a circuit carrier board according to a preferred embodiment of the present invention. FIG. 2B is a schematic cross-sectional view of another circuit carrier board according to a preferred embodiment of the present invention. [Schematic description] 10: solder bump 20: wafer 100 circuit carrier board 110 substrate 112 surface 120 bonding pad 130 solder cover Layer 132, α 140, protective layer 201, and 202: circuit substrate 210, substrate 212, surface 220, bonding pad 222, first copper layer 224, barrier layer 226, second copper layer 230, solder mask layer 232, and p
12642TWF.PTD 第14頁 12.37879 圖式簡單說明 2 4 0 :保護層 第15頁12642TWF.PTD Page 14 12.37879 Brief description of drawings 2 4 0: Protective layer Page 15
12642TWF.PTD12642TWF.PTD
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW093109847A TWI237879B (en) | 2004-04-09 | 2004-04-09 | Circuit carrier and bonding pad thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW093109847A TWI237879B (en) | 2004-04-09 | 2004-04-09 | Circuit carrier and bonding pad thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TWI237879B true TWI237879B (en) | 2005-08-11 |
| TW200534437A TW200534437A (en) | 2005-10-16 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW093109847A TWI237879B (en) | 2004-04-09 | 2004-04-09 | Circuit carrier and bonding pad thereof |
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| Country | Link |
|---|---|
| TW (1) | TWI237879B (en) |
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2004
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| TW200534437A (en) | 2005-10-16 |
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