TWI233187B - MOS device and fabrication method thereof - Google Patents

Abstract

A MOS device and fabrication method of the same. The MOS device of the invention includes a substrate. A gate electrode is disposed over the substrate. A pair of source/drain regions are respectively disposed in the substrate on both sides of the gate electrode. A stress-buffering lining is conformably disposed on both sides of the gate electrode and partially extends to the surface of the substrate and a stress layer is disposed over the gate electrode, the stress-buffering lining and the source/drain regions and contacts the stress-buffering lining to enhance stresses in a channel region in the substrate below the gate electrode.

Description

1233187

FIELD OF THE INVENTION The present invention relates to a metal oxide semiconductor (MOS) element and a method for manufacturing the same, and particularly relates to a method using local mechanical stress control (1 0ca 1 疋 mechanica and stress contr). 〇i, abbreviation] ^^) to increase the efficiency of the M⑽ element and its structure. + Prior technology In the current semiconductor devices, the entire silicon device (si bu 1 ^) is used as the substrate, and the purpose of high-speed operation and low volume is achieved by reducing the size of the device. However, the current reduction in device size is close to the physical == and the limit of cost. Therefore, it is necessary to develop other techniques different from the size reduction method to achieve high-speed operation and low power consumption. Therefore, some people have proposed the use of stress control in the channel area of the transistor To overcome the limit of device shrinkage. This method is to increase the mobility of electrons and holes by changing the lattice spacing of silicon by using stress. A common method is to use the Si-Ge layer (under tensile stress). Tensile-strained Si layer is used as the channel layer of the NMOS transistor, and compressive-tension germanium layer (⑽⑽compressive-strained Si_Ge layer) is used as the channel of the PM0S transistor. Floor. By using a tensile tension silicon layer and a compressive tension Si-Ge layer as the channel layer of the M0S transistor, it will increase the mobility of electrons and holes, and achieve high-speed operation and dual loss at the same time.

1233187 V. Description of the invention (2) --------- ~-

There are some problems with Sl /? NV, and this method, when the S layer (η through layer) and the Si-Ge layer (P channel layer) with compressive tension are formed at the same time as complementary to the oxygen semiconductor (c 〇mplementary metai 〇xide semiconductor; CM0S) device when the channel layer, the process will become very complicated, and it is very difficult to selectively form the NM0S channel layer and PM0S channel layer and ¥ Si formed by local temperature heat treatment In the -Ge layer, dislocation or segregation of Ge occurs, and the characteristics of the gate breakdown voltage are deteriorated.

In addition, recently, there have been studies that use a silicon nitride layer as a contact stop etching layer to generate stress to affect the transistor actuation current. This technique is called localized, stress control. By increasing the applied compressive stress, the mobility of the PM0S transistor can be improved; by reducing the applied compressive stress, the mobility of the NM0S transistor can be improved. 2. Although the method of using the silicon nitride layer to generate stress to improve the performance of the transistor is simpler than the method using the S 1 -Ge buffer layer, the improvement effect is limited. SUMMARY OF THE INVENTION In view of this, the present invention provides a structure and method which can further improve the efficiency of a transistor by using a technique of local mechanical stress control. ^ Therefore, the present invention provides a MOS device having a structure including a gate electrode X »on a substrate, and a source / drain in the substrate on both sides of the gate electrode. The stress buffer liner is compliantly arranged. On both sides of the gate electrode and part of it extends to the surface of the substrate ', and a stress layer is provided on the gate electrode, the stress buffer lining

1233187 V. Description of the invention (3) Layer and substrate under source / drain electrodes Among them, if the above-mentioned gate electrode and source NMOS transistor are used. If the upper and lower gate electrodes and body. In addition, in the present invention, the gate electrode is disposed in the substrate including the two sides of the electrode in the grooved isolation element, and the second stress layer is compliantly disposed on the gate, and the stress buffer layer is provided to the south pole. If the tensile stress mentioned above is covered, the second stress layer of the transistor formed by covering the drain electrode should be covered by the second stress layer. The crystal is a PMOS transistor. Firstly, the master in the substrate on both sides of the substrate also provided at least one first contact and contacted the upper electrode and two gate electrode liners. The second stress under the contact electrode should be PMOS power and the first The square gate 'is in contact with the stress buffer lining to increase the stress in the channel region of the gate. The stress layer has tensile stress. The transistor covered by the bottom / drain of the stress layer is a PM0s transistor and the stress layer described above has compressive stress. The transistor covered by the source / non-polar layer of the stress layer is pM〇s electric another MOS device, its structure includes an isolation element on the substrate, this shallow trench force layer 'positions the source / drain electrode on the gate isolation element, and extends the stress buffer liner side and partially to The substrate surface, the stress buffer layer, and the source / non-electrode layer are caused by the stress in the channel region in the first stress layer and the second substrate. The layer has tensile stress and the gate electrode and source / crystal and NMOS transistor under the first stress layer have a stress layer. If the above-mentioned first stress layer has a compression or stretching time, a method of manufacturing an MOS device composed of an electrode and a source / drain is as follows. The method is as follows. A lightly doped region. Then, compliantly

V. Description of the invention (4) Z forms a stress buffer layer on both sides and part of the closed electrode, and a stress buffer layer on both sides of the closed electrode: 2 The bottom surface is not gated on both sides of the gate electrode. ::: J: connection forms a source / drain region. The // H doped region and the heavily doped region cover the -stress layer and are in contact with the stress relaxation layer; the source; the / drain electrode overlies the -channel region = layer contact 'error in the underlying substrate to improve the interelectrode: The present invention also provides an open electrode formed by the active region of the active bottom in the other side s. The above active & is formed in the substrate}, and the isolation element contains a first =, A few G ports are formed from the active areas on the two sides of the substrate defined by the two, which extend from the open electrode portion to the base surface Φ = f on both sides of the closed electrode and the gap 4 on both sides of the closed electrode Unclosed =: Xuan layer on the second layer: The active region in the substrate forms a heavily doped region. The second gap: the second region and the heavily doped region form a source / drain region. After waiting for a while, the gap is removed, and the gate electrode 70% of the source / drain and source / drain is covered with a second stress: force ^ contact with the liner, with the above first stress The layer and the second force layer approximate the stress in a channel region in the underlying substrate. β a gate electrode In the above process, before removing the spacer, move the #object process to the surface of the source β electrode ^ 1233187

Compound. After the removal of the spacer, an automatic four-chemical process is performed to reduce the source / drain decay period. μ, X, 々 pain men r ... a metal silicide formed on the surface. Silicon oxide. 9 scoops are less than 50 angstroms, and the material can be the material of the above-mentioned stress layer. Rsi〇N ^ ^ ¡Keibei is SiN, silicon oxynitride

. * " Sergeant N) and silicon oxynitride (Si〇N) " ^ ^, manufacturing / including plasma enhanced chemical vapor deposition (PECVD

Twenty-two, high-speed ..., process chemical vapor deposition (rtcvd), atomic layered disordered deposition method (ALCVD), or low-pressure chemical vapor deposition (LpcvD) In the above-mentioned manufacturing method of the MOS device, it further includes Steps: = forming an inner dielectric layer on the stress layer or the second stress layer; using the stress layer or the first stress layer as an etch stop layer, etching a contact window opening in the inner layer dielectric layer; and removing the contact window opening A stress layer or a second stress layer. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below and described in detail with the accompanying drawings as follows: Embodiment According to the research results, for p-channel transistors, when the compressive stress or tensile stress in the channel region is increased, the hole carrier mobility is added. For N-channel transistors, when the channel is reduced The compressive stress in the region, that is, when the tensile stress in the channel region is increased, the migration of the electron carrier will be passed through ΪΒϋΠβΗΓ------------------ _ 0503-8980ClPTWF (Nl ); TSMC2002-0937; Shawn.ptd 10th minus 123318 7 V. Description of the invention (6) Xiuyi " The privacy rate increases the mobility of carriers in the channel region, so the present invention provides a structure of a MOS device and a manufacturing method thereof which can effectively increase the stress in the channel region. Structure The present invention provides a structure of a metal-oxide-semiconductor (MOS for short) device as shown in FIG. 1D. In this structure, the gate electrode is placed on the substrate 100 and the source / non-electrode is provided. S / D is provided in the substrate 100 on both sides of the gate electrode 104. The material of the gate electrode 104 may be polycrystalline silicon, metal, germanium, or polycrystalline silicon containing germanium. The gate electrode 1 〇 04 and the substrate 100 are provided with a gate dielectric layer I 0 2 ′, whose material may be silicon oxide. The stress buffer liner 1 1 〇 is compliantly arranged on the gate electrode 丨 〇 4 Both sides and part of the substrate extend to the surface of the substrate. The thickness of the stress buffering layer is controlled to less than 500 angstroms, and the material can be oxidized stone. Next, the stress layer 118 is provided on the gate electrode. 04. On the stress buffer liner 110 and the source / drain S / D, and the gate electrode 104 The stress buffer liner II is in contact, thereby increasing the stress in the channel region 1 j ^ in the substrate 100 under the gate electrode 104. Among them, the material of the stress layer 丨 8 is silicon nitride (s 丨 n), Vertical layer of oxynitride (SiON), or nitride oxynitride (^ ν) and oxynitride (y〇N). If this stress layer 118 has tensile stress, it covers the gate electrode below the stress layer 118 The transistor composed of 1 04 and source / drain S / D is a pM0s transistor and an NMOS transistor. The stress layer 118 on the right has a compressive stress and covers the layer below the stress layer 118.

1233187-Description of the invention (7) The transistor composed of the $ electrode 104 and the source / drain S / D is a pM0s transistor. In addition, 'a gold-lithium oxide layer 1 1 6 is provided between the stress layer 118 and the source / drain S / D, so as to reduce the sheet resistance of the source / drain S / D, which also shows appropriate The compressive stress can improve ... the performance of the transistor. Generally, a metal silicide layer 116 is formed between the stress layer 118 and the gate electrode 104. · ^ Externally, an ion implantation procedure (not shown) can also be used to implant, for example, argon (Ar) ions or oxygen (〇) ions into the stress layer 18, the operation timing is after the formation of the stress layer 1 18 ' After the ion implantation is completed, a tempering procedure between 3500c and 700c is performed to increase the compressive stress of the stress layer 18, thereby appropriately adjusting the overall stress in the channel region 114. Furthermore, the present invention also provides another Mos element structure, as shown in FIG. 2F. In this structure, the gate electrode 20 is provided on the substrate 20 () in the active area AA defined by two shallow trench isolation elements STI, and the source / drain S / D is provided on the gate. The substrate 200 on both sides of the electrode 21 is attached to the adjacent, shallow trench isolation element STI ′. In the shallow trench isolation element STI, a compliant first stress layer 205a is disposed. In addition, the material of the gate electrode 210 can be polycrystalline silicon, metal, silicon germanium, or polycrystalline silicon containing germanium, and a gate dielectric layer 208 is provided between the gate electrode 2 and the substrate 200, and the material Can be oxidized stone eve. The stress buffer layer 2 1 4 is compliantly arranged on both sides of the gate electrode 2 1 0. The sting extends to the surface of the base 2000. The thickness of the stress buffer lining layer 2 1 4 is controlled below 500 angstroms, and its material can be oxidized stone.

1233187 V. Description of the invention (8) Next, a second stress layer 224 is provided on the gate electrode 21, the stress buffer layer 214, and the source / drain s / D, and is connected to the gate electrode 21 and the stress buffer. The liner 2 1 4 contacts, and the scene of the first stress layer 204a provided in the shallow trench isolation element ST I and the second stress layer 224 provided on the surface of the gate electrode enhances the gate electrode. The stress in the channel region 220 in the substrate 200 below the 210 is. /, The material of the middle stress layer 205a and the second stress layer 224 can be nitrogen, Shi Xi (SiN), silicon oxynitride (Si0N), or a stack of silicon nitride (SiN) and oxynitride (SiON) Floor. If the second stress layer 224 has tensile stress and the first stress layer 205a has tensile stress, the gate electrode 2 1 0 and source // and electrode S covering the second stress layer 2 2 4 The transistor composed of / D is a ρ μ s transistor or crystal. If the second stress layer 224 has compressive stress and the first stress layer 205 & has tensile or compressive stress, the gate electrode 210 and source / drain S / D covering the second stress layer 224 are formed. The transistor is a pMos transistor. In addition, a metal oxide layer 222 is provided between the first stress layer 2 2 4 and the source / non-pole s / D to reduce the sheet resistance of the source / drain S / I). The compressive stress improves the performance of the pMOS transistor. Through suspension, a metal silicide layer 2 2 2 of the same material is also provided between the second stress layer 224 and the gate electrode 2 10. You can also use an ion implantation procedure (not shown) to implant, for example, argon ions or oxygen (〇) ions into the first stress layer 205a and the second stress layer 224 / the timing of this operation After the formation of these stress layers, and after the completion of the ion cloth, a tempering procedure between 35 (rc ~ 700 t) is performed to increase the compressive stress of the two stress layers, thereby appropriately adjusting the pressure in the channel area 220. whole

1233187 ------- V. Description of the invention (9) Body stress. Manufacturing Method First Embodiment Figures 1A to 1E are diagrams showing a method for manufacturing a MOS device. First, please refer to FIG. 1A. A substrate is provided. The substrate has a main area AA. The active area AA is formed by forming an isolation element structure in the substrate. For example, a shallow trench isolation element STI, And defined. Next, a transistor is formed in the active region, and this transistor may be a PMOS transistor = and a 0S transistor. As shown in the figure, a gate dielectric layer 102 and an interlayer electrode 104 are formed on the substrate 100. The material of the gate dielectric layer 102 can be silicon, and the material of the gate electrode 104 can be Polycrystalline silicon, metal, silicon germanium or polycrystalline silicon germanium. The formation method of the gate dielectric layer 〇2 and the gate electrode 104 is, for example, sequentially depositing a layer of a dielectric layer on the substrate 1000, and forming a patterned mask layer (not shown) on the conductive layer. After the display of the radio and television, the patterned mask layer was used as the mask, and the conductive layer and the dielectric layer were sequentially anisotropically etched to form the gate dielectric layer 102 and the gate electrode as shown in the figure. 104, and then removing the patterned mask layer. Then, a lightly doped region 106 is formed in the active region AA in the substrate 100 on both sides of the gate electrode 104, and the formation method is doped with an ion implantation method Implanted into the substrate not covered by the gate electrode 104 and the shallow trench isolation element ST. One by one, please refer to FIG. 1B to form a stress buffer liner conformably.

0503'8980ChemF (Nl): TSMC2002-0937; Shawn.ptd page 14 1233187 V. Description of the invention (10) 108 is on both sides of the gate electrode 04 and partially extends to the surface of the substrate 100. The thickness of the stress buffer lining layer 108 described above is less than 500 angstroms, and its material may be alumina f. In addition to being used as a stress buffer, the stress buffer liner 108 can protect the sidewalls of the gate electrode 丨 04 and the area near the channel area 丨 丨 4. After that, a wall 110 is formed on the stress buffer layer 108 on both sides of the gate electrode 104. The material of the spacers 110 can be a silicon nitride or a silicon oxide / silicon nitride laminate. The method for forming the stress buffer liner 108 and the gap wall 110 is, for example, forming a thin layer in compliance with the exposed surface of the substrate 100, the gate electrode 104, and the gate ^ layer 102 in sequence. Insulating layer and another relatively insulating layer; money, using anisotropic etching to form a layer Π0 and a stress buffer liner 108. Then, on the two sides of the gate electrode 104, the active region AA in the substrate 100 that is not covered by the gate electrode 104 is formed to form a heavily doped region i 12, and the y + method is to ion implantation The dopant is implanted in the substrate 100 which is not covered by the gate electrode, the spacer 110, and the shallow trench isolation element STI. 1: Doped region 106 and heavily doped region 丨 丨 2 constitute the source / drain region of the transistor θ / D ° Then, referring to FIG. 1c, remove 11 with wet or dry etching. 'Take out the stress buffer lining i 0 8. Before removing the spacer 110, it also includes performing a self-silicide process to make the spacer 11G from the source / drain 5/1} table ΓΓ, then-automatic alignment of Shi Xier Λ 'to A metal oxide compound 116 is formed on the surface of the source electrode and the S / D electrode, as shown in FIG. In the above-mentioned automatic alignment silicide process,

0503-8980CIFnVF (Nl); TSMC2002-0937; Shawn.ptd Page 15 1233187 Five 'invention description (11) What is the material of the right gate electrode 1 〇 "Shi Shi a 0i ^ ^ J 何 贝 为 夕 日 曰Silicon, silicon germanium or polycrystalline silicon containing germanium will also form a metal silicide layer on the surface, as shown in the figure. Referring to FIG. 1D, after removing the spacer 110 and completing the self-aligning silicide process, a stress layer is overlaid on the gate electrode 104, the stress buffer liner 108, and the electrode (drain S / D). 118, and in contact with the gate electrode 104 and the stress buffer liner 108, so as to increase the stress of the channel region 114 in the substrate 100 under the gate electrode 104.

The above-mentioned stress layer 118 may be a compressive stress layer or a tensile stress layer. Its material may be silicon nitride (SiN), silicon oxynitride (SiON), or silicon nitride (SiN) and silicon oxynitride. (SiON) stack, its 3J) 0 ~ 700 angstrom (A), the formation method can be plasma enhanced chemical vapor deposition (PECVD), rapid thermal process chemical vapor deposition (RTCVD) ), Atomic-level chemical vapor deposition method ^ ") ^ low pressure chemical vapor deposition (LPCVD). When the stress layer 118 is stretched using silicon nitride (SiN) / silicon oxynitride (si〇N) stack In the case of a stress layer, the tensile stress in the upper layer is larger than that in the lower layer. At this time, the material in the upper layer of the stack is preferably a nitrogen oxide layer with a high nitrogen content (siliC0n). -rich nitride), and

The material of the lower layer of the stack is preferably silicon nitride or a nitrogen-rich nitride layer (nitrogen-rich nitride). By controlling the formation conditions, the stress of the formed film layer can be adjusted. According to research, the factors that can control the stress are temperature, pressure, or gas ratio. If the plasma deposition method is used, the stress factors can be controlled. Return $ = plasma power.

〇503-8980CIPTWF (Nl): TSMC2002-0937; Shawn.ptd Page 16 Ϊ233187

For example, the plasma-enhanced chemical vapor deposition method is used to form a stress layer 11 8 which is made of nitrided material and is a pinch stress. The required temperature is approximately 300 t and 00 ° C. Therefore, The required pressure is roughly between 丨 · TOR (t〇rr) and 丨 · 5 Torr, and the required plasma power is between 丨 00 watt (w) and 2000 watt 'The process gas can be Ml · · SiH4, and the ratio is approximately 4 ~ 10. Taking the rapid thermal process chemical vapor deposition method as an example for forming silicon nitride and tensile stress, the required temperature is approximately 300 and the required pressure is approximately 150. Between Thor and 300 Tor, its process gas may be NH3: Si & the ratio is approximately 50 ~ 400; or its process gas may be digas silane (SiH2Cl2, referred to as Dcs) ): NH3, the ratio is approximately 0: [~ 1. Taking the low-pressure chemical vapor deposition method to form a stress layer 118 made of silicon nitride and compressive stress as an example, the required temperature is approximately 400 °. 〇 and 50 〇, the required pressure is approximately between 0 · Torr (t〇rr) and 50 Torr 'its process gas can be two gas silane and N1, the ratio is approximately 1-3 〇〇. If the stress layer 118 has tensile stress, the transistor composed of the gate electrode 104 and the source / drain S / D covering the stress layer 118 may be a PMOS transistor and an NMOS transistor. In this case, the compressive stress of the channel region 1 丨 4 of the CMOS element of the present invention will be reduced by about 93 ~ 128 MPa compared with the conventional structure without removing the spacer, thereby increasing the electron and hole carriers in the channel. The mobility of the region. If the stress layer 118 has compressive stress, the transistor system consisting of the gate electrode 104 and the source / drain S / D covering the stress layer 118 is a PMOS transistor. In this case, compared with the conventional structure without the spacers removed, the present invention

1233187

The compressive stress of the channel region 114 of the Ming CMOS device will increase by about 93 ~ 128 MPa, thereby improving the mobility of hole carriers in the channel region. In addition, an ion implantation procedure (not shown) can be used to implant, for example, argon (AO ions or oxygen (0) ions) into the stress layer 118. The operation timing is after the formation of the stress layer 1 18, and the ion cloth is completed. After the implantation, a tempering procedure between 350 ° C and 700 ° C is performed to increase the compressive stress of the stress layer 118, thereby appropriately adjusting the overall stress in the channel region 114. In addition, the above-mentioned stress layer may also be used. As the famous engraving stop layer for the subsequent contact window process. Then the subsequent process, such as the interconnect process, is formed. As shown in FIG. 丨 E, an inner dielectric layer 20 is formed on the stress layer 1 18, which The material is, for example, oxide seconds, phosphophosphosilicate glass (BPSG), or other similar properties. After the inner dielectric layer 120 is flattened, the inner dielectric layer 120 and the inner dielectric layer 120 are processed by a lithography etching process. A contact window opening 122 is formed in the stress layer 118. In the remaining step of the contact window, the above-mentioned stress layer 丨 8 is used as an etching stop layer 'after the money is etched to expose the stress layer 118 in the contact window opening 218 , And then convert the remaining conditions to remove the The stress layer 118 is until the device area to be connected is exposed. Figures 2A to 2G of the second embodiment illustrate the intention of another method of manufacturing a MOS device. First, please refer to Figure 2A to provide a substrate 200, in which the substrate 200 has an active area AA, wherein the active area AA is defined by forming two trenches 202 in the substrate 100. Then, a liner is formed in the trenches 202 respectively.

1233187 V. Description of the invention (14) 2 04 to smooth the surface of the groove 20 2. The underlayer 204 is, for example, a silicon oxide layer formed by a thermal oxidation method. Then, a first stress layer 205 is formed compliantly in the trench 200 and the substrate 200 and covers the inner liner layer 204 of the trench 202. Here, the first stress layer 205 can be formed with reference to the manufacturing method of the stress layer 1 to 8 in the aforementioned first embodiment. Then, an insulating material 206 is deposited on the substrate 200 in a comprehensive manner and filled into the trench 002. Then referring to FIG. 2B, the planarization step (not shown), such as one of the chemical mechanical polishing procedures, is performed to remove the insulating material 20 6 higher than the surface of the substrate 200, and then to the trench 200 An insulating layer 206a is left inside. Then, a part of the first stress layer on the substrate surface in the active area AA is removed by performing a #etching step (not shown), and finally a first stress layer 205a conforming to the trench surface is left in the trench. In the trench 202, shallow trench isolation elements defining different active regions are formed. Referring to FIG. 2C, a transistor is formed in the active region ^, and the transistor can be a PMOS transistor or an NMOS transistor. As shown in the figure, a gate dielectric layer 208 and a gate electrode 2 are formed on the substrate 2000. The material of the gate dielectric layer 208 may be silicon oxide, and the gate electrode 21 The material can be polycrystalline stone genus, genus germanium or polycrystalline stone containing germanium. The gate dielectric layer 20 and the gate electrode 210 are formed by, for example, sequentially depositing a dielectric layer and a conductive layer on the substrate 200, and forming a patterned mask layer on the conductive layer ( (Not shown), and then, using the patterned mask layer as the mask, the dielectric layer and the dielectric layer are sequentially anisotropically etched to form the gate dielectric layer 208 and The gate electrode 21 is removed, and the patterned mask layer is removed. After that, the active area AA in the substrate 200 on both sides of the gate electrode 210

1233187 V. Description of the invention (15) — ------- Lightly doped region 212 is formed by doping the gate electrode 2 1 0 and the shallow trench isolation element ST I by ion implantation. , Frost II. Ding 01, the substrate 200 of the suffix, and then referring to FIG. 2D, a stress relief 21 4 is compliantly formed on both sides of the gate electrode 21 () and partially extends to the surface of the substrate 200. The thickness of the stress buffer lining 2 1 4 is less than 500 Angstroms, and the material may be & L t. In addition to being used as a stress buffering layer, the stress buffer lining layer 214 can also be used to protect the sidewall of the gate electrode 21o and the '' area near the channel region 22o. Then, a gap 216 is formed on the stress buffer layer 2 丨 4 on both sides of the gate electrode 210. The material of the spacer 216 may be a stack of silicon nitride or silicon oxide nitride. The method for forming the stress buffer lining layer 214 and the spacer 216 is, for example, forming a thin insulating layer in compliance with the exposed surface of the substrate 20, the gate electrode 21 and the gate ^ layer 2 08 in this order. And another stricter insulating layer; then, anisotropic etching is used to form a gap gap 21 6 and a stress buffer liner 21 4. 'Then, the active region AA in the substrate 2000 which is not covered by the gate electrode 210 and the spacer 216 on both sides of the gate electrode 210 forms a heavily doped region 218, and the method of forming it by ion The implantation method implants a dopant into the substrate 200 that is not covered by the gate electrode 21, the spacer 216, and the shallow trench isolation element STI. The lightly doped region 2 1 2 and the heavily doped region 2 1 8 constitute the source / drain region ^ S / D of the transistor. Referring to FIG. 2E, the spacer 2 1 6 ′ is removed by wet etching or dry etching to expose the stress buffer liner 2 1 4. Before removing the partition wall 216, it further includes performing an automatic alignment.

〇3〇3-8980CimF (Nl); TSMC2000.937; Shawn.ptd

1233187 V. Description of the invention I (16) The compound is used to form a metal oxide compound layer 222 on the surface of the source / drain S / D; or after the spacer 216 is removed, an automatic alignment silicidation is performed. Material and clothing-A metal lithoxide layer 222 is formed on the surface of the source / non-polar S / D, as shown in FIG. 2E. In the automatic alignment silicide process described above, if the material of the gate electrode 210 is polycrystalline silicon, silicon germanium, or germanium-containing polycrystalline silicon, a metal silicide layer 22 2 is also formed on the surface, as shown in the figure. Here, the metal silicide layer 222 formed at the surface of the source / drain S / D may also exhibit a compressive stress to the channel region 220. Next, referring to FIG. 2F, after removing the spacer 216 and completing the automatic 5 f / chemical process, a second stress is covered on the gate electrode 21, the stress buffer liner 21 4 and / or the electrode S / D. The layer 224 is in contact with the gate electrode 21m and the liner layer m, so as to increase the stress in the region 200 of the 200 through region in the substrate below the gate electrode 210. In addition, an ion implantation procedure (not shown) can also be used to implant ions such as argon (Ar) or oxygen (〇) ions into the first stress layer 205a and the second stress layer 224. The timing is as follows: After the formation of these stress layers, and after the completion of the ion cloth, a tempering procedure between 35 (rc ~ 70 (rc) is performed to increase the compressive stress of this layer, thereby appropriately adjusting the overall stress in the channel region 220. The above-mentioned second stress layer 224 of r can also be used as an etching stop layer for subsequent contact window manufacturing. Then, a subsequent process, such as an interconnection process, is performed. As shown in the second figure: on the second stress layer 224 An inner dielectric layer 226 is formed. Examples of bean materials are emulsified stone, stone-filled glass (BPSG), or other similar properties till () 503-8980CimF (Nl); TSMC2002-0937; Shawn.ptd Section 21 Page 1233187 V. Description of the invention (17) The 'and the inner dielectric layer 226 is traversed' on the inner dielectric layer 226 and the first part is engraved by lithography money 2 2 80 t. ^, 1 ^ HI2 4 / _ ^ ^ ^ Force = stop layer, engraved until exposed to the next two ^ force _ again =; =: the second and the second contact window opening σ22δ from the first and second Taitai Road to be connected to the element The force layer i ί, ΐ: What can the f-layer 205a and the second stress layer 224 be the respective stretched layers of the corresponding gas, the material can be silicon nitride (SiN), the most nitrogen; m Shi Xi (SiN ) * Nitride oxide (si〇N) ^ Said that the degrees of their respective degrees are about 20 ~ 300 angstroms (A) and 3,007 angstroms (PECVD). Enhanced chemical vapor deposition

Wafer / Wang (a r_ !, Low Pressure Chemical Vapor Deposition (LPCVD). When the stress is said, the stress layer = 205a or the second stress layer 2 24) is a silicon nitride (SiN silicon oxide (Si〇N) stack) When the tensile stress layer is one of the layers, the tensile stress of the upper layer is better than that of the lower layer. At this time, the material of the lower layer of the stack is preferably silicon oxynitride or a silicon nitride layer with a higher silicon content. (sU ^ con —rich nitride), and the material on the upper layer of the stack is preferably silicon nitride or a nitrogen-rich silicon nitride layer (ni tr〇gen-rich nitride) 〇 formed by control The conditions can adjust the stress of the formed film layer. According to the research, the factors that can control the stress are temperature, pressure or process gas month and ratio. The right is plasma deposition method, and the factors that can control the stress include electricity.

05Q3-8980CIPTWF (N1); TSMC2002-0937; Shawn.ptd Page 22 1233187

Plasma power. Taking the electro-enhanced chemical vapor deposition method to form a second stress layer 2 2 4 which is nitrided and compressive stress as an example, the required temperature is approximately between 300 ° C and 500 ° C. The required pressure is roughly between 丨 · TOR (t 〇r) and 1.5 Torr, and the required plasma power is roughly between 丨 00 watt (w) and 2000 watt. In the meantime, the process gas can be NHs: SiH4, and the ratio is approximately 4 ~ 10. Taking the rapid thermal process chemical vapor deposition method as an example for forming silicon nitride and tensile stress, the required temperature is approximately between 300 and 800, and the required pressure is approximately 15 Between 〇 Tor and 300 TOR, the process gas can be NI ·· Si H4, the ratio is approximately 50 ～ 400; or the process gas can be dichlorosilane (SiH2Cl2, referred to as DCS) ): N H3, the ratio is approximately 0.1 ~ 1. Taking the low-pressure chemical vapor deposition method to form a second stress layer 224 made of silicon nitride and compressive stress as an example, the required temperature is approximately between 400 and 750 ° C, and the required pressure is approximately between Between 0.1 Torr and 50 Torr, the process gas may be DCS: NH3, and the ratio is approximately 1 to 300. If the first stress layer 224 has tensile stress and the first stress layer 206a has tensile stress, the gate electrode 21 and the source / drain S / D formed under the second stress layer 224 are covered with electricity. The crystal can be a PMOS transistor and a pseudotransistor. In this case, the compressive stress of the channel region 220 of the MOS device of the present invention will be reduced by about 100% compared with the conventional structure without the spacer wall removed, thereby increasing the electron and hole carriers in the channel region. Mobility.

0503-8980CIPnVF (Nl): TSMC2002-0937; Shawn.ptd page 23 1233187 V. Description of the invention (19) If the second stress layer 224 has compressive stress and the first stress layer 206a has tensile or compressive stress, it is covered by The transistor system composed of the gate electrode 210 and the source / drain S / D under the second stress layer 224 is a pMOS transistor. In this case, compared with the conventional structure without removing the barrier wall, the compressive stress of the channel region 220 of the MOS element of the present invention will increase by about 100-900 MPa, thereby increasing the hole load. Mobility in the channel region. In summary, the present invention utilizes a transistor in which mechanical stress is concentrated in a channel region, thereby deteriorating characteristics. In the process of manufacturing the transistor, a process of removing the spacer is added, and the ground is concentrated in the channel region of the transistor. The local mechanical stress control is used to increase the demand for the above-mentioned manufacturing of the stress layer, and the stress layers meeting their needs are manufactured separately. The provided structure and method can be used to form the machine with a low-speed operation and low energy consumption. 'Before the stress layer is deposited, the stress of the deposited stress layer can be made effective by increasing the stress. Therefore, the method can be applied to any borrowing. Process of crystal efficiency. In addition, according to the difference between the P channel and the N channel, it has compressive stress and tensile stress. It is not limited to the above-mentioned method to improve the efficiency of the transistor. Therefore, the method for forming the stress layer can be determined by other methods. Local mechanical stress control programs are applicable to the present invention. Although the present invention has been disclosed in the preferred embodiment as above, the bran bowl: the invention of 'anyone skilled in the art :: within the range' can be modified and retouched, so Honda Vision's attached patent The scope defined shall prevail. ’,

1233187 The drawings briefly explain that FIGS. 1A to 1E are schematic diagrams illustrating a method for manufacturing an M 0 S element according to an embodiment of the present invention, and FIGS. 2A to 2G are diagrams illustrating another method according to the present invention. A schematic diagram of a method for manufacturing a MOS device according to an embodiment. Symbol description Active area · AA, shallow trench isolation element: STI, STI '; source / drain: S / D; substrate: 100, 2 0; gate dielectric layer: 1 2 2, 2 0 8; Lightly doped region: 1 0 6, 2 1 2; Stress buffer liner: 1 0 8, 2 1 4 Heavyly doped region: 1 1 2, 2 1 8; Metal silicide layer: 11 6, 2 2 2 Inner layer Dielectric layer: 120, 226; Contact window opening: 1 2 2, 2 2 8; Lining layer: 2 0 4; Insulating layer: 2 0 6 a; Second stress layer: 224. Gate electrode: 104, 2 1 0; Spacer wall: 11 0, 2 1 6; Channel area: 1 14, 220; Stress layer: 1 1 8; Trench: 2 0 2; Insulating material: 2 0 6; The first stress layer: 205a;

0503-8980CIPTWF (Nl): TSMC2002-0937; Shawn.ptd page 25

Claims (1)

! 233187 Six 'application patent scope 1. A metal oxide semiconductor (MOS) device, comprising a substrate provided with at least one isolation element, wherein the isolation element includes a first stress layer; A gate electrode is disposed on the substrate; a source / drain is disposed in the substrate on both sides of the gate electrode and contacts the isolation element; a stress buffer liner is compliantly disposed on the gate And two parts of the electrode extend to the surface of the substrate; and a second stress layer is provided on the closed electrode, the source / drain of the stress buffer liner, and is in contact with the stress buffer liner, and further by Xi = two stress layers and the third stress layer to increase the stress in one channel region of the a I bottom under the gate electrode. 2. The thickness of the stress buffer liner in the metal-oxide semiconductor device described in item 1 of the scope of the patent application is less than 5000 angstroms. 3. The material of the stress buffer lining in the gold-oxygen semiconductor element described in item 1 of the scope of patent application is silicon oxide. 4. The material of the first stress layer in the gold-oxygen semiconductor device described in item 1 of the scope of the patent application is silicon nitride (SiN), oxynitride (SWN), or silicon nitride (SiN), and silicon oxynitride ( Si⑽). Φ2: If! Please refer to the metal-oxide semiconductor element described in item 1 of the patent scope; the material of the stress layer in 1 is silicon nitride (s 丨 N), nitrogen ^ (S1〇N) or silicon nitride (SlN) and nitrogen Stacking of silicon oxide (SiON). 6. The metal-oxide semiconductor element as described in item 5 of the scope of patent application: 0503-8980CIPTWF (Nl): TSMC2002-0937; Shawn.ptd, page 26, 1233187 Sixth stress application patent scope -------- The nitride chip (si N) and silicon oxynitride force layer, where the stack The layer above the layer is more complex) is a stretch. The tensile strength of the lower layer should be as described in item 5 of the scope of the patent application. The material of the lower layer is silicon-rich silicon nitride (Si 丨 · 〃 breast semiconductor element, or silicon oxynitride (SiON)). The upper layer material is 1C ^ n ~ rich nitride) nitrogen-rich nitride. Fossils of rats or nitriding of nitrogen 8. The second stress layer has tensile stress in the gold-oxygen described in item 1 of the scope of the patent application, and the n-th piece 'its: The gate electrode and Chengzhi transistor are either PM0S transistors or Longjing transistors. And the structure 9 of the metal-oxide semiconductor device according to item 1 of the scope of the patent application, wherein the second stress layer has a compressive stress and the first stress layer has a tensile or compressive stress and covers the second stress layer The transistor composed of the gate electrode and the source / non-electrode is a pMOS transistor. I 0 · The metal-oxide semiconductor device according to item 1 of the scope of the patent application, wherein the material of the gate electrode is selected from the group consisting of free polycrystalline silicon, metal, silicon germanium, and polycrystalline silicon containing faults. II. The gold gas semiconductor device according to item 1 of the patent application scope, further comprising a metal oxide layer disposed between the second stress layer and the source / drain electrode, and the second stress layer And the gate electrode. 1 2 The metal-oxide-semiconductor device according to item 9 of the scope of patent application, further comprising a metal oxide layer disposed between the far second stress layer and the source / drain electrode, and the second Between the stress layer and the gate electrode to improve 0503-8980ClPTWF (Nl); TSMC2002-0937; Sl ^ wn.ptd page 27 1233187 6. Scope of patent application For the PMOS transistor a compressive stress. 13. A method for manufacturing a metal-oxide semiconductor device, comprising: providing a substrate; forming at least one isolation element in the substrate to define an active region, wherein the isolation element includes a first stress layer; and Forming a gate electrode in the region; forming a lightly doped region in the substrate on both sides of the gate electrode in the active region and contacting the isolation element; compliantly forming a stress buffer liner on both sides of the gate electrode And partly extends to the surface of the substrate; a gap wall is formed on the stress buffer layer on both sides of the gate electrode; and in the substrate on both sides of the gate electrode which is not covered by the gate electrode and the gap wall The active region forms a densely doped region, wherein the lightly doped region and the heavily doped region constitute a source / drain region; the spacer is removed; and the gate electrode, the stress buffer liner, and The source / drain electrode is covered with a second stress layer and is in contact with the stress buffer liner, and then the second stress layer and the first stress layer are used to improve a channel region in the substrate below the gate electrode. Of stress. 14. The method for manufacturing a metal-oxide semiconductor device according to item 13 of the scope of the patent application, wherein the isolation element is a shallow trench isolation element, and the first stress layer is compliantly formed in the shallow trench isolation. Component. 1 5. The method for manufacturing a metal-oxide semiconductor device according to item 13 of the scope of patent application, wherein the thickness of the stress buffer lining is less than 500 angstroms. 0503-8980CIPTWF (Nl); TSMC2002-0937; Shawn.ptd Page 28 1233187 Six 'application patent scope 1 6 · The manufacturing method of the metal-oxide semiconductor device described in the patent application scope item 3, wherein the stress buffer lining The material of the layer is silicon oxide. 17 · The method for manufacturing a metal-oxide-semiconductor device according to item 13 of the scope of the patent application, wherein the material of the first stress layer is selected from free silicon nitride (SiN), oxynitride (siON), and It is a group consisting of a stack of gasified stone evening (SiN) and gas silicon oxide (Si ON). 1 8. The method for manufacturing a metal-oxide-semiconductor device according to item 3 in the scope of the patent application, wherein the material of the second stress layer is selected from free silicon nitride (SiN), silicon oxynitride (siON), and It is a group consisting of a stack of silicon nitride (SiN) and silicon oxynitride (Si ON). 1 9 · The method for manufacturing a metal-oxide semiconductor device according to item 3 of the patent application scope, wherein the method for forming the first stress layer is plasma enhanced chemical vapor deposition (PECVD), rapid thermal process chemical gas Phase deposition (RTCVD), atomic-level chemical vapor deposition (ALCVD), or low-pressure chemical vapor deposition (LPCVD). 2 0. The method for manufacturing a metal-oxide semiconductor device according to item 13 of the scope of patent application, wherein the method for forming the second stress layer is plasma enhanced chemical vapor deposition (PECVD), rapid thermal process chemical gas Phase deposition (RTCVD), atomic-level chemical vapor deposition (ALCVD), or low-pressure chemical vapor deposition (LPCVD). 2 1 · The method for manufacturing a metal-oxide semiconductor device according to item 3 of the scope of the patent application, wherein the second stress layer has tensile stress and the first stress layer has tensile stress, covering the second stress layer The transistor formed by the gate electrode and the source / drain below is a PMOS transistor or a pass transistor. 0503-8980CIPTWF (Nl); TSMC2002-0937; Shawn.ptd page 29 1233187 6. Application for patent scope 2 2 · The method for manufacturing a metal-oxide semiconductor device according to item 13 of the scope of patent application, wherein the second stress The layer has a compressive stress and the first stress; a transistor having tensile or compressive stress covering the gate electrode and the source / drain electrode under the second stress layer is a PMOS transistor. 2 3 · The method for manufacturing a metal-oxide semiconductor device according to item 3 of the patent application scope, wherein the material of the gate electrode is selected from the group consisting of free polycrystalline silicon, metal, silicon germanium, and germanium-containing polycrystalline silicon. 24. The method for manufacturing a gold-oxygen semiconductor device according to item 3 of the patent application scope, wherein the material of the spacer is silicon nitride. 2 5 · The method for manufacturing a metal-oxide semiconductor device as described in item 13 of the scope of patent application, wherein the method of removing the spacer is wet engraving. 2 6 · The method for manufacturing a metal-oxide semiconductor device according to item 3 of the patent application scope, wherein the method of removing the spacer is dry etching. 2 7. The method for manufacturing a metal-oxide-semiconductor device according to item 13 of the scope of patent application, wherein before removing the spacer, it further comprises performing an auto-aligned silicide process on the source / drain A metal silicide is formed on the surface. 2 8 · The method for manufacturing a metal-oxide-semiconductor device according to item 13 of the scope of patent application, wherein after removing the spacer, the method further includes performing an auto-aligned silicide process for the source / drain A metal silicide is formed on the surface. 2 9 · The method for manufacturing a metal-oxide-semiconductor device as described in item 22 of the scope of patent application, wherein before removing the spacer, it further includes performing an automatic alignment process on the silicon oxide, so that the source / injection A metallic stone is formed on the surface of the pole 〇503-8980CIPTWF (Nl); TSMC2002-0937: Shawn. Ptd page 30 1233187 6. Patent application compounds, in which the metal silicide provides a compression force for the PMOS transistor. 30. The method for manufacturing a metal-oxide-semiconductor device according to item 22 of the scope of patent application, wherein after removing the spacer, it further comprises performing an auto-aligned silicide process for the source / drain A metal silicide is formed on the surface, and the metal silicide provides a compressive stress to the PMOS transistor. 3 1. The method for manufacturing a metal-oxide-semiconductor device as described in item 13 of the scope of patent application, further comprising the following steps: forming an inner dielectric layer on the stress layer; using the stress layer as a rest stop layer, A contact window opening is etched into the inner dielectric layer; and the stress layer in the contact window opening is removed. 3 2. The method for manufacturing a metal-oxide semiconductor device according to item 13 of the scope of the patent application, further comprising an ion implantation process performed by the second stress layer to adjust the overall stress of the channel region. 3 3. The manufacturing method of the gold-oxygen semiconductor device according to item 32 of the scope of the patent application, wherein the dopant used in the ion implantation procedure is argon ion or oxygen ion. 0503-8980CIPTWF (N1); TSMC2002-0937; Shawn.ptd page 31