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TWI232541B - Aluminum hillock-free metal layer, electronic part, and thin flat transistor and its manufacturing method - Google Patents

Aluminum hillock-free metal layer, electronic part, and thin flat transistor and its manufacturing method Download PDF

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TWI232541B
TWI232541B TW92119085A TW92119085A TWI232541B TW I232541 B TWI232541 B TW I232541B TW 92119085 A TW92119085 A TW 92119085A TW 92119085 A TW92119085 A TW 92119085A TW I232541 B TWI232541 B TW I232541B
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layer
aluminum
thickness
alloy
patent application
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TW92119085A
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TW200503164A (en
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Kung-Hao Chang
Shyi-Ming Yeh
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Chi Mei Optoelectronics Corp
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Priority to TW92119085A priority Critical patent/TWI232541B/en
Priority to JP2004193115A priority patent/JP4729661B2/en
Priority to US10/885,782 priority patent/US7235310B2/en
Priority to KR1020040053579A priority patent/KR101070761B1/en
Publication of TW200503164A publication Critical patent/TW200503164A/en
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Publication of TWI232541B publication Critical patent/TWI232541B/en
Priority to US11/802,350 priority patent/US7944056B2/en

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Abstract

A kind of aluminum hillock-free metal layer and its manufacturing method are disclosed in the present invention. The compound film composed of aluminum neodymium alloy and aluminum is used as the metal layer, in which the aluminum layer is located on top of the aluminum neodymium alloy layer and the aluminum layer thickness is larger than aluminum neodymium alloy layer thickness. Thus, the formation of aluminum hillock can be suppressed effectively; and the manufacturing cost can be greatly reduced.

Description

12325411232541

【發明所屬之技術領域】 本發明是有關於一種鋁導線層,且赞別是有關於一種 一 /、〗凸起之金屬層(hillock-free gate)、電子元件與 薄膜電晶體及其製造方法。 【先前技術】 在半V體製程中’ 一般係選用鉬(m〇iybdenum,Mo)或 絡(Cr)做為金屬層之材料,然而,價格昂貴的鉬或鉻金屬 會使整個製程成本居高不下。地球上含量最豐富的金屬 鋁’不但容易取得,且價格便宜,一般多應用於金屬 .囑4程中。選用純紹做為金屬層製程之材料,其優點是:铭 '、有低氣阻係數’且與基板(s u b s t r a t e )間有良好的依附 性’在钱刻製程中亦表現出較佳的蝕刻特性。然而,若使 用炼點(melting point)較一般金屬低的純鋁作為金屬 層’其表面會有鋁尖凸(Hillock)形成之問題。 明參照第1 A圖’其繪示金屬沉積於玻璃基板之示意 圖。先在較低的溫度下(約150 τ )將金屬沉積在玻璃基板 上’因此玻璃基板102土有晶粒(crystal particle) 1〇4,晶粒l〇4和晶粒104之間則有晶界(grain boundary) 囉J 〇 6形成。當然,實際上的晶粒並不會如第丨A圖一樣方 正’在此係為了方便說明而以整齊的方形晶粒表示。接 著’進行回火(anneal ),藉由高溫加熱所提供的熱能增加 晶粒的振動,使晶粒原子的排列得以重整,晶粒得以藉由 缺卩曰的消失而進行再結晶(r e c r y s t a 11 i n e )。經過再結晶[Technical field to which the invention belongs] The present invention relates to an aluminum wire layer, and the invention relates to a hillock-free gate, electronic components, and thin film transistors, and a manufacturing method thereof. . [Previous technology] In the semi-V system process, molybdenum (moybdenum, Mo) or Cr is generally used as the material of the metal layer. However, the expensive molybdenum or chromium metal will make the entire process cost high. No less. The most abundant metal on the earth, aluminum, is not only easy to obtain, but also cheap. It is usually used in metals. Choosing pure Shao as the material for the metal layer process has the following advantages: “Made in low air resistance coefficient” and good dependence on the substrate (substrate) also shows better etching characteristics . However, if pure aluminum having a melting point lower than that of a general metal is used as the metal layer ', there will be a problem of formation of aluminum spikes on the surface. Referring to Fig. 1A ', a schematic diagram showing metal deposition on a glass substrate is shown. First deposit the metal on the glass substrate at a lower temperature (about 150 τ). Therefore, the glass substrate 102 has crystal particles 104, and there are crystals between the crystal particles 104 and 104. The grain boundary 啰 J 〇6 is formed. Of course, the actual grains will not be as square as in Figure A. Here, for the sake of explanation, the crystal grains are neatly square. Then, “annealing” is performed, and the vibration of the crystal grains is increased by the thermal energy provided by the high temperature heating, so that the arrangement of the crystal grain atoms can be reorganized, and the crystal grains can be recrystallized by the disappearance of the crystals (recrysta 11 ine). After recrystallization

1232541 案號 92119085 曰 修正 五、發明說明(2) 的晶粒’其内應力(i n n e r s t r e s s )將因差排及缺陷密度的 降低而急劇下降。如果回火的溫度再繼續升高,使再結晶 階段形成的晶粒有足夠的能量克服晶粒間的表面能 (surface energy)時,晶粒將開始在消耗小晶粒的過程中 成長,形成較大的晶粒,並且使小晶粒的晶界消除,此 時,晶粒的内應力將更進一步的降低。 使用純鋁作為金屬層之金屬時,會有小凸起的問題產 生。請參照第1 B圖,其繪示回火後的鋁於玻璃基板之示意 圖。回火過程的高溫,使鋁晶粒1 〇 4和玻璃基板1 〇 2均產生 膨脹(thermal expansion),但鋁的熱膨脹係數大於玻 璃的熱膨脹係數,使鋁晶粒1 〇 4產生極大的應力 (compressive stress),由於鋁係附著在玻璃基板1〇2 上,因此鋁原子會沿著晶界1 〇 6成長而在其上方形成鋁尖 凸(hillock)llO。這種在金屬層上形成的鋁尖凸11〇,不 但會造成後續製程中其他層厚度的不平坦(unevenness), 且過大的鋁尖凸110可能會穿越金屬層上方的絕緣層,而 與另一層金屬層接觸,造成短路。 一般常見也最有效的傳統做法,是在鋁中加入少許熔 更高的其他元素,如鈥(Nd)、鈦(Ti)、鍅(Zr)、钽 (Ta)、矽(Si)或銅(Cu),以解決上述鋁尖凸的問題。請參 照第2A圖,其繪示回火後的鋁合金於玻璃基板之示意圖。 玻璃基板2 0 2上方的鋁合金之晶粒2 〇 4,經過回火後(高溫 加熱),由於非鋁元素無法和鋁互溶,因此當晶粒2 〇 4成長 時,非鋁元素會轉移至晶界20 6,而在晶界20 6中聚集成一1232541 Case No. 92119085 said Amendment 5. The internal stress (in n e r s t r e s s) of the grains of the invention description (2) will decrease sharply due to the reduction of the defect row and defect density. If the tempering temperature continues to increase, so that the grains formed during the recrystallization stage have enough energy to overcome the surface energy between the grains, the grains will start to grow and consume in the process of consuming small grains. Larger grains and the grain boundaries of small grains are eliminated. At this time, the internal stress of the grains will be further reduced. When pure aluminum is used as the metal of the metal layer, there is a problem of small bumps. Please refer to Figure 1B, which shows a schematic view of tempered aluminum on a glass substrate. The high temperature of the tempering process causes thermal expansion of both aluminum grains 104 and glass substrates 102, but the thermal expansion coefficient of aluminum is greater than the thermal expansion coefficient of glass, which causes great stress on aluminum grains 104. compressive stress), since the aluminum system is adhered to the glass substrate 102, aluminum atoms grow along the grain boundary 106 and aluminum hillocks 110 are formed thereon. The aluminum spikes 11 formed on the metal layer not only cause unevenness in the thickness of other layers in the subsequent process, but excessive aluminum spikes 110 may pass through the insulating layer above the metal layer and cause A metal layer is in contact, causing a short circuit. The most common and most effective traditional practice is to add a few other higher melting elements to aluminum, such as “(Nd), titanium (Ti), hafnium (Zr), tantalum (Ta), silicon (Si) or copper ( Cu) to solve the above-mentioned problem of aluminum spikes. Please refer to Figure 2A, which shows the schematic diagram of the tempered aluminum alloy on the glass substrate. After the tempering (high temperature heating) of the aluminum alloy grains 204 on the glass substrate 202, the non-aluminum elements cannot be miscible with aluminum, so when the grains 204 grow, the non-aluminum elements will be transferred to Grain boundary 20 6 and aggregated into one in grain boundary 20 6

92082TW-修正.ptc 第5頁 1232541 五、發明說明(3) 丄:? ,21 〇 k些小顆粒210會堵住晶界2 06之通道,使鋁 :者曰曰界206成長時’無法通過小顆粒21〇而突出於晶粒 π #\方七進而抑㈣紹尖凸之形《°且彡過電子顯微圖片 L々a ‘ i,層的晶粒結構較為緻密,而參雜有金屬顆粒 ,金層1晶粒結構較為鬆散,有孔隙出現。因此,後 :產生的熱應力可經由链合金層的鬆散結ΐ 中釋放,而不會推擠紹馬;你廿 罹褙铝原子使其沿著晶界1 06而成長為鋁 大凸h111〇ck)110。其中,又以日本K〇beic〇公 紹钕Ul-Nd)合金最為知名而被廣泛應用。 的 歛的原子3:大,炼點高,可有效地在晶界中形成 粒以阻撞銘原子從晶界之通道中突起,當溫度達約 = w然不會有無小凸起形成。然而’敍為稀有金 ,成Ή ’且因摻_d,需使用較慢的錢鍵速率 (sputtering rate)以防止噴濺(splash)之產生;更重要 敍具有高電阻值’使紹鉞合金的總電阻值高於純銘 甚多。 根據上述,如何在一般半導體製程或在液晶顯示器之 金屬層製程中,應用銘以降低成本,但又可防制小凸起 (hU lock)的產生,係為業者一重要研究目標。 【發明内容】 有鑑於此,本發明的目的就是在提供一種不具鋁尖凸 ^ ^屬層及其製造方法,以鋁鉉合金和鋁所組成之複合膜 作為金屬| ’不但有效抑制鋁尖凸之形成,更大幅降低製92082TW-correction.ptc page 51232541 V. Description of the invention (3) 丄:?, 2 0k These small particles 210 will block the channel of the grain boundary 2 06, so that the aluminum: when the boundary 206 grows, it cannot pass through the small Particles 21〇 and protruding out of the grain π # \ 方 七 and further suppress the shape of the sharp convex "° and pass the electron micrograph L々a 'i, the grain structure of the layer is more dense, and mixed with metal particles The gold layer 1 has a relatively loose grain structure with pores. Therefore, the rear: The thermal stress generated can be released through the loose junction of the chain alloy layer without pushing Shaoma; you can suffer from aluminum atoms to grow along the grain boundary 106 to become aluminum bumps h111. ck) 110. Among them, Japan's Kobeic 0 Neodymium Ul-Nd) alloy is the most well-known and widely used. Concentrated atom 3: large, high refining point, can effectively form particles in the grain boundary to prevent the atom from protruding from the channel of the grain boundary. When the temperature reaches about = w, no small bumps will be formed. However, 'Syringe is a rare gold, and it is Ή', and because of _d, a slow sputtering rate must be used to prevent splashing. More importantly, it has a high resistance value. The total resistance value is much higher than the pure name. According to the above, how to apply inscriptions to reduce costs in general semiconductor processes or metal layer processes of liquid crystal displays, but to prevent the generation of hU locks, is an important research goal for industry players. [Summary of the Invention] In view of this, the object of the present invention is to provide a metal layer without aluminum spikes and a method for manufacturing the same. A composite film composed of aluminum alloy and aluminum is used as the metal | Formation

1232541 五、發明說明⑷ " 晒 " 造成本。 根據本發明的目的,提出一種不具鋁尖凸之金屬層及 其製造方法,以避免產生鋁尖凸(hi丨1〇ck),其中,金屬 層係位於一基板上,且至少包括兩層之鋁層。首先形成一 鋁鈥合金(Al-Nd)層於基板上;接著形成一鋁層於鋁鈥合 金層之上方。其中’鋁鈥合金層的厚度約在1〇〇A〜4〇〇 〇A 範圍之間’且較佳地約在3〇〇 A〜900A範圍之間。鋁層的厚 度約在5 0 0 A〜4 5 0 0 A範圍之間,且較佳地約在 1500A〜3000A範圍之間。 為讓本發明之上述目的、特徵、和優點能更明顯易 懂’下文特舉較佳實施例,並配合所附圖式,作詳細說明 如下: 【實施方式】 本發明之技術特點在於,應用紹錄)合金和紹之複合 膜’以抑制小凸起(hi 1 lock)之產生。其中,蘇層的厚度 係大於銘鈦合金層之厚度。本發明特別是應用於電子元 件,如薄膜電晶體(Thin film transistor)中,以作為其 金屬電極層。 請參照第2圖,其繪示依照本發明一較佳實施例之鋁 鈥合金-鋁之複合膜的示意圖。首先,在基板202上形成一 鋁鈥合金(Al-Nd)層204。其膜厚範圍約在100A〜4000A之 間,且較佳地約在300 A〜90 0A之間。 接著,在鋁鈦合金層上方形成一鋁層206。其膜厚範1232541 V. Description of the invention ⑷ " Exposure to the sun " According to the purpose of the present invention, a metal layer without aluminum spikes and a manufacturing method thereof are proposed to avoid the occurrence of aluminum spikes. The metal layer is located on a substrate and includes at least two layers. Aluminum layer. An aluminum-alloy (Al-Nd) layer is first formed on the substrate; then an aluminum layer is formed over the aluminum-alloy layer. Among them, the thickness of the "aluminum alloy layer is in the range of about 100A to 4,000A" and preferably in the range of about 300A to 900A. The thickness of the aluminum layer is in a range of about 500 A to 4 500 A, and preferably in a range of about 1500 A to 3000 A. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, hereinafter, preferred embodiments are described in detail with the accompanying drawings as follows: [Embodiment Mode] The technical features of the present invention are applications Shaolu) alloy and Shao's composite film 'to suppress the generation of small bumps (hi 1 lock). Among them, the thickness of the Su layer is greater than that of the titanium alloy layer. The present invention is particularly applied to electronic components such as thin film transistors as its metal electrode layer. Please refer to FIG. 2, which illustrates a schematic diagram of an aluminum-alloy-aluminum composite film according to a preferred embodiment of the present invention. First, an aluminum-alloy (Al-Nd) layer 204 is formed on the substrate 202. Its film thickness ranges between about 100A and 4000A, and preferably between about 300A and 900A. Next, an aluminum layer 206 is formed over the aluminum-titanium alloy layer. Film thickness range

IIMI IEH1I TW1106F(奇美).ptd 第 7 頁IIMI IEH1I TW1106F (Chi Mei) .ptd Page 7

1232541 一丨 . 五、發明說明(5) 圍約在50 0人〜4500人之間,且較佳地約在15〇〇乂〜3〇〇〇人之 間。且鋁層的厚度係大於鋁鈥合金層之厚度。 至於形成銘鈥合金(Al-Nd)層204和鋁層206的成膜條 件則沒有特殊限制,可採用一般成膜壓力,如〇· 3Pa、或 〇.4Pa。位於鋁層206下方的鋁鈥合金層204,可在後續的 问/皿製程中釋放熱應力,而有效抑制鋁尖凸的形成。 另外’在紹層206上方還可形成一層不易氧化之保護 層’其材料例如金屬鉬(M〇)、氮化鉬(M〇N)、鈦(Ti)或其 合金材料等(未顯示於圖中)。 以下即為本發明之複合膜結構的一系列實驗,並經過 回火溫度3 2 0。(:,回火時間約1 〇分鐘後,以掃描式電子顯 微鏡(Scanning electron microscope)觀察銘層上方是否 有紹尖凸形成。另外,在本發明之複合膜上形成氮化鉬層 (MoN) ’並檢查其剖面(pr〇Hie check)。表一列出本發明 之幾組實驗結果。 ΗΐΠΗί 第8頁 TW1106F(奇美).Ptd 1232541 五、發明說明(6) 紹敛合金層 之膜厚(A) 鋁層之獏厚 (A) 回火後是否產生鋁 尖凸起 剖面檢查 0 2000 有 細 1800 0 無 良好 300 1000 無 良好 300 2000 無 良好 450 2000 無 良好 450 1000 良好 900 2000 無 良好 900 1000 無 良好 1800 2000 無 良好 1800 1000 無 良好1232541 I. V. Description of the invention (5) It is about 500 to 4500 people, and preferably about 150 to 300 people. And the thickness of the aluminum layer is greater than the thickness of the aluminum 'alloy layer. As for the film forming conditions for forming the Al-Nd layer 204 and the aluminum layer 206, there are no particular restrictions, and a general film forming pressure such as 0.3 Pa or 0.4 Pa can be used. The aluminum 'alloy layer 204 located under the aluminum layer 206 can release thermal stress in the subsequent interfacial process and effectively suppress the formation of aluminum spikes. In addition, a “protective layer that is not easily oxidized can be formed on the top layer 206”. Materials such as metallic molybdenum (MO), molybdenum nitride (MON), titanium (Ti), or alloy materials thereof (not shown in the figure) in). The following is a series of experiments for the composite membrane structure of the present invention, and the tempering temperature is 3 2 0. (: After the tempering time is about 10 minutes, use a scanning electron microscope (Scanning electron microscope) to observe the formation of sharp protrusions on the top layer. In addition, a molybdenum nitride layer (MoN) is formed on the composite film of the present invention. 'And check its profile (pr〇Hie check). Table 1 lists several experimental results of the present invention. ΗΐΠΗί Page 8 TW1106F (Chimei). Ptd 1232541 V. Description of the invention (6) The thickness of the alloy layer ( A) Thickness of aluminum layer (A) Check whether there is an aluminum tip bump profile after tempering. 0 2000 Fine 1800 0 No good 300 1000 No good 300 2000 No good 450 2000 No good 450 1000 Good 900 2000 No good 900 1000 No good 1800 2000 No good 1800 1000 No good

H ( *照組) 在基板上,以成膜壓力〇·3 Pa沉積一鋁層,其厚度為 2000 A 。經過回火溫度320〇c,回火時間約1〇分鐘後,以掃 描式電子顯微鏡(Scanning electron microscope)觀察紹 層上方是否有鋁尖凸形成。 觀察結果顯示:在僅使用銘層的情形下,會產生銘尖 凸。 宜-驗.二(對照組) 在基板上,以成膜壓力〇· 3 Pa沉積一鋁敍合金層,其 厚度為1800a 。經過回火溫度32 0°C,回火時間約1 〇分鐘 後’以掃描式電子顯微鏡(Scanning eiectfQn microscope)觀察鋁鈥合金層上方是否有鋁尖凸形成。H (* Photo group) An aluminum layer was deposited on the substrate with a film forming pressure of 0.3 Pa, and its thickness was 2000 A. After a tempering temperature of 320 ° C and a tempering time of about 10 minutes, a scanning electron microscope (Scanning electron microscope) was used to observe whether there were aluminum spikes formed over the layer. Observation results show that when only the inscription layer is used, the inscription is protruded. Yi-Experiment. 2 (control group) An aluminum alloy layer was deposited on the substrate with a film forming pressure of 0.3 Pa to a thickness of 1800a. After a tempering temperature of 32 ° C and a tempering time of about 10 minutes, a scanning electron microscope (Scanning eiectfQn microscope) was used to observe whether aluminum spikes were formed on the aluminum 'alloy layer.

1232541 五、發明說明(7) 觀察結果顯示··在僅使用鋁鉞合金層的情形下,沒有 铭尖^凸產生。 另外,在鋁鈥合金層上方係形成一層金屬鉬(M〇),其 厚度為1 Ο Ο Ο A 。並以掃描式電子顯微鏡檢查其剖面 (prof i le check),其結果顯示剖面十分良好。 然而,全部使用鋁鈥合金作為金屬層,其成本太高。 另外鋁鈥合金的電阻值約為鋁的兩倍,因此需要更長的 獏時間以形成較厚的膜厚,而達到元件設計的要求。、又 實驗三 在基板上’以成膜壓力〇· 3 Pa沉積一鋁斂合金層, 厚度為300 A ;接|,在鋁鈥合金層上方形成一鋁層,复、 度為2000 A。經過回火溫度32〇〇c (回火時間約1〇分鐘、 後,以掃描式電子顯微鏡觀察。觀察結果顯 凸產生。 又巧銘尖 之鋁i :金ΐ㈤m步驟在另_基板上形成厚度同#為3〇〇 A ° 但鋁層之厚度減半為1 0 0 0 Α 。經過回火 觀 竅%竅灶里#寺間約10分鐘後’以掃描式電子顯微鏡 察。視察、、"果顯示:/亦沒有鋁尖凸產生。 、a後’在兩者之鋁層上方形成一層金屬鉬(Mo),其厚 度為9〇〇A 。並以掃描式電子顯微鏡檢查其剖面(profile check) ’其結果顯示:兩者之剖面均十分良好。 實驗四1232541 V. Explanation of the invention (7) Observation results show that · When only the aluminum-rhenium alloy layer is used, there is no indentation. In addition, a layer of metallic molybdenum (Mo) is formed on the aluminum 'alloy layer, and its thickness is 100 Å. A scanning electron microscope was used to examine the profile (prof i le check), and the results showed that the profile was very good. However, it is too expensive to use all aluminum alloys as the metal layer. In addition, the resistance value of aluminum's alloy is about twice that of aluminum, so it takes longer time to form a thicker film thickness to meet the requirements of component design. 3. Experiment 3 An aluminum alloy layer was deposited on the substrate at a film forming pressure of 0.3 Pa, with a thickness of 300 A; then, an aluminum layer was formed over the aluminum alloy layer to a degree of 2000 A. After the tempering temperature of 3200 ° C (tempering time of about 10 minutes, it was observed with a scanning electron microscope. The observation results were prominent. The sharp aluminum i: gold ΐ㈤m step was formed on another substrate to form a thickness The same # is 〇〇〇 °, but the thickness of the aluminum layer is halved to 1000 Α. After tempering, it is about 10 minutes after the temple is inspected with a scanning electron microscope. Inspection, & quot The results show: / Also no aluminum spikes are formed. After a, a layer of metal molybdenum (Mo) is formed over the aluminum layer of the two, and its thickness is 900A. The profile is checked with a scanning electron microscope (profile) check) 'The results show that the profiles of both are very good. Experiment 4

第10頁 TW1106F(奇美).ptd 1232541 發明說明(8) 層之】ΐ=Γ,除了銘鈥合金層之厚度為45。… r德m。經過回火溫度320。。,回火時間約10分 產: 顯微鏡觀察。觀察結果顯示:沒有紹 金芦同!”也2 ί:基板上形成厚度同樣為45〇Α之銘敍合 金層’但鋁層之厚度減半為1 000 Α。經過 回火時間約1 0分鐘後,以掃描4雷j ^ i 又 果顯示:亦沒有銘尖凸產^式鏡觀察。觀察結 然後,在兩者之鋁層上方係形成一層金屬鉬(M0),豆 1度為900 A。並以掃描式電子顯微鏡檢查其剖面(pr〇fiie check),其結果顯示··兩者之剖面十分良好。 實驗五 · 同只驗二之步驟,除了鋁鈦合金層之厚度為900A ,鋁。 曰之厚度為2 0 00 A 。經過回火溫度32〇〇c,回火時間約1〇分 鐘後,以掃描式電子顯微鏡觀察。觀察結果顯示:沒 尖凸產生。Page 10 TW1106F (Chi Mei) .ptd 1232541 Description of the invention (8) of the layer] ΐ = Γ, except that the thickness of the alloy layer is 45. … R de m. After tempering temperature 320. . Tempering time is about 10 minutes. Production: Microscope observation. Observation results show that there is no Shaojin Lutong! "Also 2 ί: an inscription alloy layer with a thickness of 45〇Α is also formed on the substrate, but the thickness of the aluminum layer is halved to 1,000 A. After tempering time is about 10 minutes Later, scanning with 4 ray j ^ i also showed that there was also no observing convex-type microscope observation. After observing the knot, a layer of metal molybdenum (M0) was formed over the aluminum layer of the two, and the bean 1 degree was 900 A. 。 And the scanning electron microscope to check its cross section (pr0fiie check), the results show that the two cross sections are very good. Experiment 5 The same two steps, except that the thickness of the aluminum titanium alloy layer is 900A, aluminum The thickness is 2000 A. After the tempering temperature is 3200c, and the tempering time is about 10 minutes, it is observed with a scanning electron microscope. The observation results show that no sharp protrusions are generated.

同樣地,在另一基板上形成厚度同樣為9〇〇A之鋁鈥合 金層,但鋁層之厚度減半為1 0 0 〇 A 。經過回火溫度3 2 〇。匸, 回火時間約1 0分鐘後,以掃描式電子顯微鏡觀察。觀察結 果顯不:亦沒有紹尖凸產生。 然後,在兩者之鋁層上方係形成一層金屬鉬(M0),其 厚度為900 A 。並以掃描式電子顯微鏡檢查其剖面(pr〇file check),其結果顯示兩者之剖面十分良好。Similarly, an aluminum alloy layer having a thickness of 900 A was also formed on another substrate, but the thickness of the aluminum layer was halved to 1000 A. After tempering temperature 3 2 0. Alas, after a tempering time of about 10 minutes, it was observed with a scanning electron microscope. Observation results were not obvious: there were no sharp peaks. Then, a layer of metallic molybdenum (M0) was formed over the aluminum layer of the two, with a thickness of 900 A. The scanning electron microscope was used to check its profile (pr0 file check), and the results showed that the profile of both was very good.

1232541 五、發明說明(9) 同實驗三之步驟,除了鋁鈥合金層之厚度為1800Α , 鋁f之厚度為2 〇 〇 〇 a 。經過回火溫度3 2 〇。(:,回火時間1 0分 鐘後,以掃描式電子顯微鏡觀察。觀察結果顯示··沒有鋁 尖凸產生。 ^ 同樣地’在另一基板上形成厚度同樣為1 8 Ο Ο A之鋁鈥 曰金層’但銘層之厚度減半為丨〇 〇 〇 A 。經過回火溫度 3 2 0 °C ’回火時間約丨〇分鐘後,以掃描式電子顯微鏡觀 察。觀察結果顯示:亦沒有紹尖凸產生。 然後’在鋁層上方係形成一層金屬鉬(),其厚度為 9〇〇a °並以知描式電子顯微鏡檢查其剖面(pr〇fiie check) ’其結果顯示剖面十分良好。 由上述可知,在基板和鋁層之間鍍上一層鋁鉉合金 層’的確可有效抑制鋁尖凸的形成。 在實際應用上,可選用膜厚較薄的鋁鈥合金層與膜厚 較厚的鋁層搭配,以降低生產成本。以實驗五為例,選用 膜厚450A的鋁鈦合金層與膜厚2000A的鋁層,其成本約只 有全選用膜厚1800A的鋁鈥合金層的三分之二。另外,|呂 的阻值比鋁鈥合金的阻值低(約只有二分之一),因此相同 膜厚條件的A1N d / A1複合膜之片電阻值較鋁層低,使元件 設計上所需的膜厚可以較薄,不但減少了鍍膜時間,更降 低了產品的總厚度,並改善產品的平坦度。1232541 V. Description of the invention (9) The same procedure as in Experiment 3, except that the thickness of the aluminum alloy layer is 1800A and the thickness of aluminum f is 2000a. After tempering temperature 3 2 0. (: After a tempering time of 10 minutes, observe with a scanning electron microscope. The observation results show that there are no aluminum spikes. ^ Similarly, an aluminum with a thickness of 1 8 〇 A is also formed on another substrate. "The gold layer", but the thickness of the Ming layer is halved to 丨 00〇A. After tempering temperature of 320 ° C 'tempering time of about 丨 0 minutes, observation with a scanning electron microscope. The observation results show that: Shao-convex formation. Then 'a layer of metallic molybdenum () was formed on the aluminum layer, with a thickness of 900a ° and the profile was checked with a scanning electron microscope (promifi check)' The results showed that the profile was very good From the above, it can be seen that plating an aluminum alloy alloy layer between the substrate and the aluminum layer can indeed effectively suppress the formation of aluminum spikes. In practical applications, a thinner aluminum alloy layer with a thinner film thickness can be used. The thickness of the aluminum layer is matched to reduce the production cost. Taking Experiment 5 as an example, an aluminum-titanium alloy layer with a film thickness of 450A and an aluminum layer with a film thickness of 2000A are selected. Two-thirds. In addition, | The resistance value is lower than that of aluminum 'alloy (only about one half), so the sheet resistance value of the A1N d / A1 composite film under the same film thickness condition is lower than that of the aluminum layer, so that the film thickness required for component design can be thinner , Not only reduces the coating time, but also reduces the total thickness of the product, and improves the flatness of the product.

ιϋΒ1 TW1106F(奇美).ptd 第12頁 1232541 五、發明說明(10) 本發明上述實施例所揭露之不具鋁尖凸之金屬層及其 製造方法,其優點除了可有效抑制小突起的產生外,成本 較傳統只使用鋁鉉合金要大幅降低,且產能提高,對元件 縮小化亦有正面助益。 本發明之不具鋁尖凸之金屬層,可應用於一電子元 件,以作為其電極。以下則以一薄膜電晶體(Thin film transistor)為例,說明應用本發明形成其金屬閘極。第3 圖繪示一薄膜電晶體之底閘極(bottom gate)之剖面示意 .圖。首先,提供一基板300,且於基板300上方沉積一閘極 層,並利用微影與蝕刻技術圖案化閘極層,以形成一閘極 3 1 0。其中,閘極層的沈積方法如前述之方法,先沉積一 銘鈦合金(A卜Nd)層,膜厚範圍約在1〇〇 a〜4000A之間,且 較佳地約在300 A〜900A之間。然後,在鋁歛合金層上方沉 積一紹層’膜厚範圍約在5 0 〇 A〜4 5 0 0 A之間,且較佳地約 在1500A〜3000A之間。接著,在紹層上方沉積一金屬鉬 (Mo)層,膜厚範圍約在300 A〜1 20 0A之間。 接著’於閘極31 0上方形成一閘極絕緣層3 2 〇。然後, 利用沈積、微影和蝕刻製程,形成一非晶矽層3 3 〇與一歐 姆接觸層(ohmic contact layer) 340於閘極絕緣層32〇之 上。 接著’形成一没極360與一源極365。形成方法是先將 一金屬層,如鉻、鋁等金屬,沉積於整個基板3〇〇之上, 並利用微影與蝕刻製程,對金屬層進行圖案化的步驟,則 於閘極上方的金屬層中,形成一暴露非晶矽層33〇的開ιϋΒ1 TW1106F (Chimei) .ptd Page 121232541 V. Description of the invention (10) The metal layer without aluminum spikes disclosed in the above embodiments of the present invention and the manufacturing method thereof have the advantages of effectively suppressing the generation of small protrusions, Compared with the traditional use of aluminum hafnium alloy alone, the cost is greatly reduced, and the production capacity is increased, which also has a positive effect on the reduction of components. The metal layer without aluminum spikes of the present invention can be applied to an electronic device as its electrode. In the following, a thin film transistor is taken as an example to illustrate the application of the present invention to form a metal gate electrode thereof. Fig. 3 is a schematic cross-sectional view of a bottom gate of a thin film transistor. First, a substrate 300 is provided, and a gate layer is deposited on the substrate 300, and the gate layer is patterned using lithography and etching techniques to form a gate 3 10. The gate layer is deposited as described above. A titanium alloy (AbNd) layer is deposited first, with a film thickness in the range of 100a to 4000A, and preferably in the range of 300A to 900A. between. Then, a film thickness ranging from about 500 A to about 450 A is deposited over the aluminum alloy layer, and preferably between about 1500 A to 3000 A. Next, a metal molybdenum (Mo) layer is deposited over the Shao layer, and the film thickness ranges between 300 A and 120 A. Next, a gate insulating layer 3 2 0 is formed over the gate 3 10. Then, an amorphous silicon layer 3 3 0 and an ohmic contact layer 340 are formed on the gate insulating layer 32 0 by a deposition, lithography and etching process. Next, 'a pole 360 and a source 365 are formed. The forming method is a step of depositing a metal layer, such as chromium, aluminum, and the like on the entire substrate 300, and patterning the metal layer by using a lithography and etching process. In the layer, an opening exposing the amorphous silicon layer 33 is formed.

第13 TW1106F(奇美).ptd 1232541 發明說明(11) 此時’ 一 /及極3 6 0與一源極3 6 5亦形成。其中沒極3 6 0 及源極3 6 5係以一通道隔開。 ^ 然後,沉積一保護層370於整個基板300之上,並藉由 微影與蝕刻步驟,形成一開口於保護層37〇中,以暴露汲 極360。最後’ 一透明電極層38〇覆蓋於保護層37〇之上, 並填滿暴硌至汲極3 6 0的開口,同樣的,再利用微影與蝕 刻製程,圖案化透明電極層3 8 〇。 當然,電子元件的種類十分多樣,而薄膜電晶體亦有 許多不同之製程,上述只是其中一實施例,因此應用本 明作為閘極之方法並不以上述為限。而應用本發明所製^ 之電子元件,不但成本大幅降低,亦可有效抑制小突 產生,其總阻值也較傳統完全使用鋁鈦合金要來 、 元件的電子特性有正面助益。 -’對 綜上所述,雖然本發明已以較佳實施例揭露如上,、 其並非用以限定本發明,任何熟習此技藝者,在不,然 發明之精神和範圍内,當可作各種之更動與潤飾,離本 發明之保護範圍當視後附之申請專利範圍所界定者為=本The thirteenth TW1106F (Chimei) .ptd 1232541 Description of the invention (11) At this time, 'a / and pole 3 6 0 and a source 3 6 5 are also formed. Among them, the pole 3 6 0 and the source 3 6 5 are separated by a channel. ^ Then, a protective layer 370 is deposited on the entire substrate 300, and an opening is formed in the protective layer 37 through the lithography and etching steps to expose the drain 360. Finally, a transparent electrode layer 38o covers the protective layer 37o, and fills the openings exposed to the drain electrode 360. Similarly, the lithography and etching processes are used to pattern the transparent electrode layer 38. . Of course, the types of electronic components are very diverse, and there are many different processes for thin film transistors. The above is just one example, so the method of applying the present invention as a gate is not limited to the above. The electronic components manufactured by using the present invention not only greatly reduce the cost, but also effectively suppress the occurrence of small protrusions. The total resistance value is also positively beneficial compared with the traditional use of aluminum-titanium alloys. -'To sum up, although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in this art can make various changes within the spirit and scope of the invention. Changes and modifications that depart from the scope of protection of the present invention should be defined as the scope of the attached patent application as follows:

1232541 圖式簡單說明 【圖式簡單說明】 第1A圖繪示金屬沉積於玻璃基板之示意圖; 第1B圖繪示回火後的鋁於玻璃基板之示意圖; 第2圖,其繪示依照本發明一較佳實施例之鋁鉉合金 鋁之複合膜的示意圖;及 第3圖繪示一薄膜電晶體之底面板之剖面示意圖。 圖式標號說明 102、202、300 :基板 104 ··晶粒(crystal particle) 106 ··晶界(grain boundary) 110 :小凸起(hi 1 lock) 2 0 4 :紹鈦合金層 2 0 6 : I呂層 31 0 β·閘極 3 2 0 :閘極絕緣層 3 3 0 :非晶矽層 340 :歐姆接觸層 3 6 0 :汲極 3 6 5 :源極 370 :保護層 3 8 0 :透明電極層申請專利範圍1232541 Brief description of the drawings [Simplified description of the drawings] Figure 1A shows a schematic diagram of metal deposited on a glass substrate; Figure 1B shows a schematic diagram of tempered aluminum on a glass substrate; Figure 2 shows a diagram according to the present invention A schematic view of a composite film of aluminum-rhenium alloy aluminum according to a preferred embodiment; and FIG. 3 is a schematic cross-sectional view of a bottom panel of a thin film transistor. Explanation of reference numerals 102, 202, and 300: substrate 104 · crystal grain 106 · grain boundary 110: small bump (hi 1 lock) 2 0 4: titanium alloy layer 2 0 6 : I Lu layer 31 0 β · gate 3 2 0: Gate insulating layer 3 3 0: Amorphous silicon layer 340: Ohmic contact layer 3 6 0: Drain 3 6 5: Source 370: Protective layer 3 8 0 : Scope of patent application for transparent electrode layer

TW1106F(奇美).ptd 第15頁TW1106F (Chi Mei) .ptd Page 15

Claims (1)

1232541 六、申請專利範圍 1. 一種不具紹尖凸之金屬層(Hillock-free gate), 係於一基板(substrate)上形成至少兩層之含鋁層,該金 屬層包括: 一:is鈦合金(Al-Nd)層,置於該基板上;以及 一鋁層,置於該鋁鈥合金層之上方。 2 ·如申請專利範圍第1項所述之金屬層,其中該鋁層 的厚度大於該鋁鈥合金層之厚度。 3 ·如申請專利範圍第1項所述之金屬層,其中該紹鈦 合金層之厚度約在100A〜4000A範圍之間,該鋁層的厚度 約在50 0 A〜45 00A範圍之間。 4 ·如申請專利範圍第1項所述之金屬層,其中該鋁鈥 合金層之厚度較佳地約在300 A〜900A範圍之間,該銘層的 厚度較佳地約在1 50 0 A〜3000A範圍之間。 5· —種不具銘尖凸之金屬層之製造方法,用以避免 產生不平坦之鋁尖凸(hi 1 lock),其中,該金屬層係位於 一基板上,至少包括兩層之鋁層,該製造方法包括下列步 驟: 形成一鋁鈥合金(A1-Nd)層於該基板上;以及 形成一鋁層於該鋁鈦合金層之上方; 且邊紹層的厚度係大於該紹鈹合金層之厚度。 6·如申請專利範圍第5項所述之製造方法,其中形成 之該紹敍合金層的厚度約在丨〇 〇 A ~ 4 0 0 0 A範圍之間,該鋁 層的厚度約在500A〜450〇A範圍之間。 7·如申請專利範圍第5項所述之製造方法,其中形成1232541 6. Scope of patent application 1. A metal layer (Hillock-free gate) without sharp edges is formed on a substrate to form at least two aluminum-containing layers. The metal layer includes: a: is titanium alloy (Al-Nd) layer on the substrate; and an aluminum layer on the aluminum 'alloy layer. 2. The metal layer according to item 1 of the scope of patent application, wherein the thickness of the aluminum layer is greater than the thickness of the aluminum 'alloy layer. 3. The metal layer according to item 1 of the scope of the patent application, wherein the thickness of the titanium alloy layer is between 100A and 4000A, and the thickness of the aluminum layer is between 50A and 4500A. 4. The metal layer as described in item 1 of the scope of the patent application, wherein the thickness of the aluminum alloy layer is preferably between about 300 A and 900 A, and the thickness of the coating layer is preferably about 150 A Between ~ 3000A range. 5. · A method for manufacturing a metal layer with no sharp edges to avoid the occurrence of uneven aluminum hi (lock), wherein the metal layer is located on a substrate and includes at least two aluminum layers, The manufacturing method includes the following steps: forming an aluminum 'alloy (A1-Nd) layer on the substrate; and forming an aluminum layer above the aluminum-titanium alloy layer; and the thickness of the edge layer is larger than the beryllium alloy layer Of thickness. 6. The manufacturing method as described in item 5 of the scope of the patent application, wherein the thickness of the formed alloy layer is in the range of 丨 00A ~ 400 0 A, and the thickness of the aluminum layer is in the range of 500A ~ 450 ° A range. 7. The manufacturing method as described in item 5 of the scope of patent application, wherein 第16頁 1232541 六、申請專利範圍 之該鋁鈦合金層的厚度較佳地約在3 Ο Ο A〜9 Ο Ο A範圍之間, 該鋁層的厚度較佳地約在1 5 〇 〇 A〜3 Ο Ο Ο A範圍之間。 8·如申請專利範圍第5項所述之製造方法,其中形成 該鋁鈥合金(A1-Nd)層與該鋁層的成膜壓力約為0. 3Pa。 9· 一種電子元件,該電子元件至少包含置於一基板 上之一電極,其中該電極至少包括: 一鋁鉉合金(A1 - N d )層,置於該基板上;以及 一鋁層,置於該鋁鈦合金層之上方; 其中,該鋁層的厚度係大於該鋁鈥合金層之厚度。 10·如申請專利範圍第9項所述之電子元件,其甲該 鋁鈥合金層之厚度約在1 〇 〇 A〜4 0 0 〇 A範圍之間,該鋁層的 厚度約在500人〜450(^範圍之間。 11·如申請專利範圍第9項所述之電子元件,其中該 鋁鈥合金層之厚度較佳地約在3 〇 0 A〜9 0 0 A範圍之間,該鋁 層的厚度較佳地約在1 500 A〜3 0 00A範圍之間。 12·如申請專利範圍第9項所述之電子元件,其中該 電極更包含一保護層置於該鋁層之上方。 13·如申請專利範圍第1 2項所述之電子元件,其中該 保護層係選自翻(Mo)、氮化銦(MoN)、欽(Ti)及其合金材 料其中之一。 14· 一種薄膜電晶體(Thin film transistor)元件, 包括一基板,一閘極層置於該基板上,該閘極層上方依序 沈積一閘極絕緣層、一非晶石夕層和一歐姆接觸層,而位於 該閘極上方處有一通道,且該通道兩側各有一金屬層以作Page 161232541 6. The thickness of the aluminum-titanium alloy layer in the scope of the patent application is preferably between about 3 OO A and 9 OO A, and the thickness of the aluminum layer is preferably about 15 OOA. ~ 3 Ο Ο Ο A range. 8. The manufacturing method according to item 5 of the scope of patent application, wherein the film forming pressure for forming the aluminum 'alloy (A1-Nd) layer and the aluminum layer is about 0.3 Pa. 9. An electronic component comprising at least an electrode disposed on a substrate, wherein the electrode includes at least: an aluminum-rhenium alloy (A1-N d) layer disposed on the substrate; and an aluminum layer disposed on the substrate; Above the aluminum-titanium alloy layer; wherein the thickness of the aluminum layer is greater than the thickness of the aluminum 'alloy layer. 10. According to the electronic component described in item 9 of the scope of the patent application, the thickness of the aluminum alloy layer is in the range of 1000A to 400A, and the thickness of the aluminum layer is about 500 people. The range between 450 ° and 11 °. 11. The electronic component as described in item 9 of the patent application range, wherein the thickness of the aluminum alloy layer is preferably in the range of 300 A to 900 A. The aluminum The thickness of the layer is preferably in the range of 1500 A to 300 A. 12. The electronic component according to item 9 in the scope of the patent application, wherein the electrode further includes a protective layer disposed above the aluminum layer. 13. The electronic component according to item 12 of the scope of application for a patent, wherein the protective layer is selected from one of Mo (Mo), Indium Nitride (MoN), Chi (Ti), and alloy materials thereof. A thin film transistor element includes a substrate, and a gate layer is disposed on the substrate. A gate insulating layer, an amorphous stone layer, and an ohmic contact layer are sequentially deposited on the gate layer. There is a channel above the gate, and there are metal layers on both sides of the channel for TW1106F 倚美).ptd 第17頁 1232541 六、申請專利範圍 為一源極和一沒極,該源極和該汲極並覆蓋該歐姆接觸層 與部分該基板,在該源極和該汲極並覆蓋一保護層,其 中,該閘極之特徵在於: 由一紹欽合金(Al-Nd)層與一紹層所組成,其中該鋁 層係形成於該銘鉉合金層上方,以抑制紹尖凸之形成,且 該銘鈥合金層的厚度約在丨00 A〜4000A範圍之間,該鋁層 的厚度約在500 A〜4500A範圍之間。 15·如申請專利範圍第1 4項所述之薄膜電晶體元件, 其中在該閘極更包含一保護層置於該鋁層之上方。 16·如申請專利範圍第1 5項所述之薄膜電晶體元件, 其中該保護層係選自鉬(M〇)、氮化鉬(MoN)、鈦(Ti )及其 合金材料其中之一。 17· —種電子元件,具有一圖案化電極,其中該電極 至少包括: 一鋁鈥合金(Al-Nd)層;以及 一鋁層,置於該鋁鈥合金層之上方。 18.如申請專利範圍第1 7項所述之電子元件,其中該 鋁層的厚度係大於該鋁鈥合金層之厚度。 鬌 19·如申請專利範圍第1 7項所述之電子元件,其中該 鋁鈦合金層之厚度約在100A〜4000A範圍之間,該鋁層的 厚度約在500 A〜4500A範圍之間。 20.如申請專利範圍第17項所述之電子元件,其中該 鋁鈥合金層之厚度較佳地約在3 0 〇 A〜9 〇 〇 A範圍之間,該鋁 層的厚度較佳地約在1 500 A〜3 0 00A範圍之間。TW1106F) .ptd Page 171232541 6. The scope of patent application is a source and an electrode, the source and the drain cover the ohmic contact layer and part of the substrate, and the source and the drain And covered with a protective layer, wherein the gate is characterized by: a Shao-Qin alloy (Al-Nd) layer and a Shao layer, wherein the aluminum layer is formed on the Ming-Yu alloy layer to suppress Shaojian The convexity is formed, and the thickness of the alloy layer is between about 00 A and 4000 A, and the thickness of the aluminum layer is between about 500 A and 4500 A. 15. The thin film transistor device according to item 14 of the scope of patent application, wherein the gate electrode further comprises a protective layer disposed above the aluminum layer. 16. The thin film transistor device according to item 15 of the scope of the patent application, wherein the protective layer is selected from one of molybdenum (Mo), molybdenum nitride (MoN), titanium (Ti), and alloy materials thereof. 17. An electronic component having a patterned electrode, wherein the electrode includes at least: an aluminum-alloy (Al-Nd) layer; and an aluminum layer disposed above the aluminum-alloy layer. 18. The electronic component as described in item 17 of the scope of patent application, wherein the thickness of the aluminum layer is greater than the thickness of the aluminum 'alloy layer.鬌 19. The electronic component as described in item 17 of the scope of patent application, wherein the thickness of the aluminum-titanium alloy layer is in the range of about 100A to 4000A, and the thickness of the aluminum layer is in the range of about 500A to 4500A. 20. The electronic component according to item 17 of the scope of the patent application, wherein the thickness of the aluminum alloy layer is preferably between about 300A and 900A, and the thickness of the aluminum layer is preferably about In the range of 1 500 A to 3 00 A. TW1106F(奇美).ptd 第18頁 1232541 六、申請專利範圍 21. 如申請專利範圍第1 7項所述之電子元件,其中該 電極更包含一保護層置於該鋁層之上方。 22. 如申請專利範圍第21項所述之電子元件,其中該 保護層係選自鉬(Mo)、氮化鉬(MoN)、鈦(Ti)及其合金材 〇 料其中之 〇 mTW1106F (Chimei) .ptd Page 18 1232541 6. Scope of patent application 21. The electronic component as described in item 17 of the scope of patent application, wherein the electrode further includes a protective layer placed above the aluminum layer. 22. The electronic component according to item 21 of the scope of patent application, wherein the protective layer is selected from the group consisting of molybdenum (Mo), molybdenum nitride (MoN), titanium (Ti), and alloys thereof 〇 m TW1106F(奇美).ptd 第19頁TW1106F (Chi Mei) .ptd Page 19
TW92119085A 2003-07-11 2003-07-11 Aluminum hillock-free metal layer, electronic part, and thin flat transistor and its manufacturing method TWI232541B (en)

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TW92119085A TWI232541B (en) 2003-07-11 2003-07-11 Aluminum hillock-free metal layer, electronic part, and thin flat transistor and its manufacturing method
JP2004193115A JP4729661B2 (en) 2003-07-11 2004-06-30 Aluminum layer free from hillocks and method for forming the same
US10/885,782 US7235310B2 (en) 2003-07-11 2004-07-08 Hillock-free aluminum layer and method of forming the same
KR1020040053579A KR101070761B1 (en) 2003-07-11 2004-07-09 Hillock-free aluminum layer and method of forming the same
US11/802,350 US7944056B2 (en) 2003-07-11 2007-05-22 Hillock-free aluminum layer and method of forming the same

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Publication number Priority date Publication date Assignee Title
TWI400804B (en) * 2005-05-13 2013-07-01 Samsung Display Co Ltd Multilayer film, thin film transistor array panel including the same, and manufacturing method of the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI400804B (en) * 2005-05-13 2013-07-01 Samsung Display Co Ltd Multilayer film, thin film transistor array panel including the same, and manufacturing method of the same

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