1229905 五、發明說明（1) 【技術領域】 本發明係關於一種半導體製程，特別是關於一種應用於半 導體製程中的關鍵線寬（c r i t i c a 1 d i m e n s i ο η，C D )控制方 法，可製作出顯影後關鍵線寬（人461'-〇6¥61〇0-Inspection CD，ADI CD)幾乎等於飯刻後關鍵線寬 (After-Etch-Inspection CD，AEI CD)之奈米等級閘極結 構。 【先前技術】 於半導體製程中，形成具有圖案之光阻的方法通常是先在 晶片表面形成一層光阻層，以特定的光罩進行曝光後再經 過顯影（deve 1 opment )，將晶片表面上的光阻層經過曝光 的部份，藉由化學反應加以清除，以便將曝光步驟中轉移 至光阻層上的潛在圖案顯現出來。利用此經過顯影的光阻 層圖案做為蝕刻遮罩，即可以繼績進行蝕刻製程，並將光 罩圖案轉移至晶片上。通常在顯影步驟之後以及蝕刻之 後，皆會執行一個品管的動作，分別稱為顯影後檢視 (After Develop Inspection; ADI)以及 刻後檢視 (After Etch Inspection; A E I ) 〇這些品管步驟的目的是 用來確保微影製程的正確性，使任何異常都能在進行以下 的製程前被發覺，並藉著重做（rework )來補救，以避免使 得整片或整批的晶片因後續的製程，而產生永久性的傷1229905 V. Description of the Invention (1) [Technical Field] The present invention relates to a semiconductor process, and in particular, to a critical line width (critica 1 dimensi ο η, CD) control method used in the semiconductor process, which can be produced after development. The key line width (461′-〇6 ¥ 61〇-Inspection CD, ADI CD) is almost equal to the nano-grade gate structure of the After-Etch-Inspection CD (AEI CD). [Previous technology] In the semiconductor manufacturing process, the method of forming a photoresist with a pattern is usually to first form a photoresist layer on the surface of the wafer, expose it with a specific photomask, and then develop (deve 1 opment) the wafer surface. The exposed portion of the photoresist layer is removed by chemical reaction so that the potential pattern transferred to the photoresist layer during the exposure step is revealed. By using the developed photoresist layer pattern as an etching mask, the etching process can be continued and the mask pattern can be transferred to the wafer. Usually after the development step and after etching, a quality control action is performed, which is called After Develop Inspection (ADI) and After Etch Inspection (AEI). The purpose of these quality control steps is It is used to ensure the correctness of the lithography process, so that any abnormalities can be detected before the following processes are performed, and rework is used to remedy them, so as to avoid making the whole piece or batch of wafers due to subsequent processes, Cause permanent injury
1229905 五、發明說明（2) 害，終而報廢。 隨著半導體元件線寬越來越小，我們發現ADI關鍵線寬與 A EI關鍵、線寬之間的差異也越來越大。如圖一以及圖二所 示，以製作線寬在奈米等級或以下之閘極結構為例，在半 導體基底10表面先形成閘極介電層1 2、多晶矽層1 4、矽化 鎢層1 6以及氮化矽頂蓋層1 8之堆疊結構2 0。接著於堆疊結 構2 0表面上塗佈一光阻層，並以黃光製程將光罩上的閘極 圖案定義在光阻層中，顯影後形成光阻圖案30，其ADI關 鍵線寬為。接著以光阻圖案30為蝕刻遮罩，進行一非等 向性乾蝕刻製程，蝕刻氮化矽頂蓋層1 8，將光阻圖案3 0轉 移至氮化矽頂蓋層1 8，然後再以氮化矽頂蓋層1 8為蝕刻遮 罩繼讀钱刻石夕化鎢層1 6以及多晶矽層1 4，如此完成閘極結 構4 0之定義，而AEI關鍵線寬為W2。其中，在將光阻圖案 3 0轉移至氮化矽頂蓋層1 8的蝕刻步驟中，輕微的光阻層側 壁蝕刻即會產生ADI關鍵線寬與AEI關鍵線寬之間的明顯差 異，亦即Ψ2< W丨。 習知解決此問題之方式有採先加大AD I關鍵線寬以補償光 阻在14刻過程中的C D損失，然而此法並不易控制。因此， 如何改善半導體製程以使ADI關鍵線寬與ΑΕΙ關鍵線寬之間 的差異最小，即成為製程線寬在奈米等級及以下所亟待解 決之問題。1229905 V. Description of the invention (2) Harm and eventually scrapped. As semiconductor device line widths become smaller and smaller, we find that the differences between ADI critical line widths and A EI critical, line widths are also increasing. As shown in FIG. 1 and FIG. 2, taking a gate structure with a line width of nanometer level or below as an example, a gate dielectric layer 1 2, a polycrystalline silicon layer 1 4, and a tungsten silicide layer 1 are first formed on the surface of a semiconductor substrate 10. 6 and the stack structure 20 of the silicon nitride cap layer 18. Then, a photoresist layer is coated on the surface of the stack structure 20, and the gate pattern on the photomask is defined in the photoresist layer by a yellow light process. After development, a photoresist pattern 30 is formed, and the ADI key line width thereof is. Then, using the photoresist pattern 30 as an etching mask, an anisotropic dry etching process is performed to etch the silicon nitride cap layer 18, transfer the photoresist pattern 30 to the silicon nitride cap layer 18, and then The silicon nitride cap layer 18 is used as an etching mask to read the engraved tungsten carbide layer 16 and the polycrystalline silicon layer 14 to complete the definition of the gate structure 40, and the key line width of the AEI is W2. Among them, in the etching step of transferring the photoresist pattern 30 to the silicon nitride cap layer 18, a slight etching of the sidewall of the photoresist layer will cause a significant difference between the ADI critical line width and the AEI critical line width. That is, Ψ2 < W 丨. The conventional way to solve this problem is to first increase the critical line width of AD I to compensate for the CD loss of the photoresistor in the 14-minute process, but this method is not easy to control. Therefore, how to improve the semiconductor manufacturing process to minimize the difference between the critical line width of ADI and the critical line width of AEI is a problem that needs to be solved urgently when the process line width is at or below the nanometer level.
1229905 五、發明說明（3) 【内容】 ί t J Ϊ主要百的即在於提供一種應用於半導體繫P tb d rj ^ ^^ ^ ^ ^ ^ ^ ^ i ί ϊ u：;1229905 V. Description of the invention (3) [Content] The main purpose of til t Ϊ is to provide a kind of P tb d rj applied to the semiconductor system ^ ^^ ^ ^ ^ ^ ^ ^ u :;
CD)成手專於蝕刻後關鍵線寬（A I 根據 保護 底表 層， 直側 鍍形 遮罩 至該 向性 上表 本發明 以控制 面上形 於該頂 之較 關键 成一 蓋層 壁;選擇性 成一 >5夕薄膜 向性 ;以 該半 直側 ，非等 頂蓋層 乾钱刻 面及垂 佳實 線寬 半導 上形 地於 •，利 乾飯 及利 導體 壁之 施例 之方 體層 成一 該光 用該 刻該 用該 層。 厚度 ，本發 法，包 ;於該 光阻圖 阻圖案 矽薄膜 頂蓋層 頂蓋層 其中， 分別為 明提供一 含有提供 半導體層 案，其具 之上表面 以及該光 ，藉此將 作為触刻 該矽薄膜 y以及X， 種利用光阻 一基底；於 上形成一了貝 有一 及垂 阻圖 該光 遮罩 於該 其中 上表面 直側壁 案作為 阻圖案 ，繼續 光阻圖 X< y 〇 側壁 該基 蓋 及垂 上濺 餘刻 轉移 非等 案之 術所限 技而以 及然加 徵。明 特圖發 之附本 明與對 發明來 本說用 渾田 .111- 暸詳並 步之， 一明用 近發明 更本說 能關助 員有輔 委下與 查以考 審閱參 貴參供 請僅 使，式。 了容圖者 為内附制 1229905 五、發明說明（4) 請參閱圖三至圖六，圖三 佺實施例製作奈米等級或 方法。熟習該項技藝者應 明較佳實施例僅以提出^ 應用於其它積體電路中不 A E I C D之差異’例如接觸 三所示，同樣以製作線寬 例’在半導體基底1 〇表面 1 4、矽化鎢層1 6以及氮化 於堆疊結構20表面上塗佈 上的閘極圖案定義在光阻 30’，其ADI關鍵線寬為w] 度Η小於習知光阻之厚度t 及垂直側壁32。根據本發 可以為商業上所常採用之 解，在其它例子中，光阻 加一底部抗反射（A R C )層（ 至圖六以剖面方式顯示本發明較 奈米等級以下線寬之閘極結構之 可理解，圖三至圖六所示之本發 極結構為例做說明，本發明亦可 同元件之定義，以改善ADI CD與 洞（9 〇 n t a c t h ο 1 e )之定義。如圖 在奈米等級或以下之閘極結構為 先形成閘極介電層1 2、多晶石夕層 石夕頂蓋層1 8之堆叠結構2 0。接著 一光阻層，並以黃光製程將光罩 層中，顯影後形成光阻圖案 ’其光阻厚度為H，其中光阻厚 光阻圖案30’具有一上表面31以 明之較佳實施例，所用之光阻層 正光阻。習知該行業者應可理 與氮化矽頂蓋層1 8之間可以再增 如圖四所示接著利用錢鍍技術（s p u 11 e r i n g )選擇性地僅 於光阻圖案30’之上表面31以及垂直侧壁32上形成#一> ^ 石夕薄膜50,其在光阻圖案3〇,之垂直側壁“上的厚度 而在光阻圖案30’之上表面31的厚度為y，其中χ< y。利用 濺鍍技術沈積矽膜並不會形成於氮化矽頂蓋層丨8表面上，CD) Hand focus on the key line width after etching (AI according to the protection of the bottom surface layer, a straight-side plated mask to the direction of the above table. The present invention uses the control surface to form a cover layer wall that is more critical; It is a directional film on the 5th night; With this semi-straight side, non-equid cap layer dry money facet and vertical solid line width semiconducting shape on the shape of the example of dry rice and conductive wall The body layer is formed by the light and the layer should be used at the moment. Thickness, the present method, the package; the photoresist pattern silicon film top cover layer and the top cover layer, wherein, respectively, a semiconductor layer containing a semiconductor layer is provided. The upper surface and the light will be used to etch the silicon films y and X, using a photoresistor as a substrate; a photoresist and a vertical resistive pattern are formed on the upper surface of the silicon film. As the resist pattern, the photoresist X < y 〇 side wall of the base cover and the vertical splash of the transfer of non-equal cases and other technical limitations and natural additions. The attached copy of Mingtetu and the original invention Speaking of Hun Tian. 111- In other words, Yiming uses recent inventions to say that the assistants can be assisted by sub-committees and inspecting and reviewing the petitions of the participants, please use only the formula. The person who understands the picture is attached with the system 1229905 5. Description of the invention (4) Please Refer to Figure 3 to Figure 6. Figure 3 shows the example of making nanometer grades or methods. Those skilled in the art should know that the preferred embodiment is only to propose the difference of ^ applied to other integrated circuits without AEICD. The gate pattern on the surface of the semiconductor substrate 10, the tungsten silicide layer 16 and the nitrided layer 20 on the surface of the stacked structure 20 is also defined as the photoresistor 30 ', and its ADI key line The width w] is less than the thickness t of the conventional photoresist and the vertical sidewall 32. According to the present invention, it can be a commonly used solution. In other examples, the photoresist plus a bottom anti-reflective (ARC) layer (to FIG. 6) It is understandable to show the gate structure of the present invention with a line width below the nanometer level in a cross-section manner. The present emitter structure shown in Figs. 3 to 6 is taken as an example for illustration. The present invention can also be defined with components to improve ADI. CD and hole (9 〇ntacth ο 1 e) Definition. As shown in the figure, the gate structure at the nanometer level or below is a stacked structure of a gate dielectric layer 1 2, a polycrystalline stone layer, a stone cap layer 18, and a photoresist layer. A photoresist pattern is formed in the photoresist layer in a yellow light process after development. The photoresist thickness is H, and the photoresist thick photoresist pattern 30 'has an upper surface 31 to illustrate the preferred embodiment. The photoresist layer used Positive photoresist. It is known to those in the industry that it can be added to the silicon nitride cap layer 18 as shown in Figure 4, and then use the money plating technology (spu 11 ering) to selectively only the photoresist pattern 30 '. On the upper surface 31 and the vertical side wall 32, a ^ stone evening film 50 having a thickness on the vertical side wall "of the photoresist pattern 30, and a thickness on the surface 31 above the photoresist pattern 30 'is y, where χ < y. The silicon film deposited by sputtering technology is not formed on the surface of the silicon nitride cap layer.
第10頁 1229905 五、發明說明（5) 而僅形成於阻圖案3 0 ’之上表面3 1以及垂直側壁3 2上。根 據本發明之較佳實施例，濺鍍矽薄膜50在光阻圖案30’之 垂直側壁3 2上的厚度X係小於5 0埃（a n g s t r 〇 m)，較佳小於 10埃。 如圖五所示，接著，利用濺鍍石夕薄膜5 0以及光阻圖案 30’為蝕刻遮罩，進行非等向性電漿乾蝕刻製程，乾钱刻 未被光阻圖案30’遮蔽之氮化矽頂蓋層18，並將光阻圖案 3〇’轉移至氮化矽頂蓋層18。此蝕刻步驟中，由於濺鍍矽 薄膜5 0保護住光阻圖案3 0 ’之垂直側壁3 2，因此使得蝕刻 後的氮化矽頂蓋層18閘極圖案線寬等於光阻圖案30’之ADI 關鍵線寬W!。此外，由於光阻圖案30’上有滅鍍矽薄膜50 保護，因此本發明之光阻層厚度與習知技藝相比較可以較 薄，更可以增加曝光步驟的精準度。 如圖六所示，在將光阻圖案30’轉移至氮化矽頂蓋層18 後，接著，繼續以氮化矽頂蓋層1 8作為蝕刻遮罩，蝕刻矽 化鎢層1 6以及多晶矽層1 4，形成閘極結構8 0。所形成的閘 極結構8 0之關鍵線寬約荨於光阻圖案3 0 ’之AD I關鍵線寬Page 10 1229905 V. Description of the invention (5) Only formed on the upper surface 31 and the vertical sidewall 32 of the resist pattern 3 0 ′. According to a preferred embodiment of the present invention, the thickness X of the sputtered silicon film 50 on the vertical sidewall 32 of the photoresist pattern 30 'is less than 50 angstroms (an ng strom), preferably less than 10 angstroms. As shown in FIG. 5, next, a sputtering stone film 50 and a photoresist pattern 30 ′ are used as an etching mask to perform an anisotropic plasma dry etching process. The dry money is not covered by the photoresist pattern 30 ′. The silicon nitride top cap layer 18 is transferred to the silicon nitride top cap layer 18. In this etching step, since the silicon film 50 is sputtered to protect the vertical sidewalls 32 of the photoresist pattern 30 ′, the line width of the gate pattern of the silicon nitride cap layer 18 after the etching is equal to that of the photoresist pattern 30 ′. ADI key line width W !. In addition, since the photoresist pattern 30 'is protected by a silicon-extinguishing film 50, the thickness of the photoresist layer of the present invention can be thinner than that of the conventional art, and the accuracy of the exposure step can be increased. As shown in FIG. 6, after the photoresist pattern 30 ′ is transferred to the silicon nitride cap layer 18, the silicon nitride cap layer 18 is then used as an etching mask to etch the tungsten silicide layer 16 and the polycrystalline silicon layer. 14 to form the gate structure 80. The key line width of the gate structure 8 0 is about the AD I key line width of the photoresist pattern 3 0 ′.
Wr 以上所述僅為本發明之較佳實施例，凡依本發明申請專利 範圍所做之均等變化與修飾，皆應屬本發明專利之涵蓋範 圍0Wr The above description is only a preferred embodiment of the present invention. Any equal changes and modifications made in accordance with the scope of the patent application of the present invention shall belong to the scope of the invention patent.
1229905 圖式簡單說明 圖式之簡單說明 圖一以及圖二為習知製作閘極結構產生明顯ADI關鍵線寬 與AEI關鍵線寬差異的剖面示意圖。 圖三至圖六為本發明較佳實施例以保護光阻側壁控制關鍵 線寬之方法的剖面示意圖。 圖式之 符 號 說 明 10 半 導 體 基 底 12 閘 極 介 電 層 14 多 晶 矽 層 16 矽 化 嫣 層 18 氮 化 矽 頂 蓋層 2 0 堆 疊 結 構 30 光 阻 圖 案 30, 光 阻 圖 案 31 上 表 面 32 垂 直 側 壁 40 閘 極 結 構 50 濺 鍍 矽 薄 膜 80 閘 極 結 構1229905 Brief description of the diagrams Brief description of the diagrams Figures 1 and 2 are cross-sectional schematic diagrams of the obvious difference between the critical line width of ADI and the critical line width of AEI due to the conventional fabrication of the gate structure. Figures 3 to 6 are schematic cross-sectional views of a method for controlling a critical line width by protecting a photoresist sidewall in a preferred embodiment of the present invention. Symbols of the drawings 10 semiconductor substrate 12 gate dielectric layer 14 polycrystalline silicon layer 16 silicide layer 18 silicon nitride cap layer 2 0 stacked structure 30 photoresist pattern 30, photoresist pattern 31 upper surface 32 vertical sidewall 40 gate Structure 50 Sputtered Silicon Film 80 Gate Structure
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