TWI222179B - Method of fabricating NMOS and CMOS transistors - Google Patents

Abstract

A method of fabricating an NMOS transistor, a substrate is provided, and a cleaning procedure is performed thereon, a gate dielectric layer is formed on the substrate, a plasma nitridation procedure is performed in the gate dielectric layer, the gate dielectric layer is annealed, and a gate conductive layer is formed on the gate dielectric layer. Procedures are performed in a multi-chamber system, a cluster process, with vacuum maintained. Finally, a gate electrode with patterning on the gate dielectric layer is formed, and a source and drain are formed on both sides of the gate electrode. A method of fabricating the CMOS transistor is also disclosed.

Description

1222179

Method of the invention to which the invention belongs U 5 ΪAbout the manufacture of a #N type metal-oxide-semiconductor (NM0S) transistor = Ϊ = OFF:; Integrating various processes in a vacuum-free environment This recipe can also be applied to CMOS Manufacturing of transistors. In the prior art, by increasing the integration degree of the integrated circuit, in order to make more transistors on the unit surface of the chip i, the volume of the transistor itself must be able to make I $ ^ ^ so that the line can be continuously and smoothly Advance. In this case, if you want to maintain the good electrical properties of the device, such as high capacitance or high current, the equivalent oxide thickness (EOT) of the transistor must also be Be able to scale down simultaneously. The area covered by the thickness of the vertical-effect oxide layer includes: (1) an oxide layer buried on a silicon substrate, (2) a gate dielectric layer, and (3) a doped distribution region in a polycrystalline silicon layer— ( 4) the contact interface between the silicon substrate and the gate dielectric layer, and (5) the contact interface between the gate dielectric layer and the polycrystalline silicon layer. It is said that the thickness of the contact interface described in (4) and (5) is increased because the wafer is exposed to the environment of the air during the entire manufacturing process; Hydrogen and carbon atoms are waiting for the substrate, after the main washing step is completed, before the gate dielectric layer starts to grow, and after the gate dielectric layer 2 long step is completed, before the polycrystalline spar layer begins to deposit The time gate (queue time, Q time) will adhere to and deposit on the silicon substrate and gate; Furthermore, if the subsequent high-temperature process is followed, the thickness of the contact interface ^ will grow and accumulate upwards, resulting in a significant increase in E 0 T and affecting the quality of the device. ,spirit

1222179

V. Description of the invention (2) According to the reasons for the increase in the thickness of the contact interface, if the% concentration of oxygen, hydrogen, carbon and other atoms in the environment can be sought, or the impurities (1 attached to the substrate and Methods such as the extent on the surface of the gate dielectric layer, or minimizing the waiting time between the spear-making steps, can be considered as solutions: the improvement methods disclosed in U.S. Patent No. 6,232,24 1 Here, before the formation of a gate dielectric layer on the substrate, a cleaning process including several steps is performed. First, the surface of the substrate is cleaned with a first cleaning solution, and the metal ions and carbon on the substrate are removed. And organic substances of hydrogen. Then, continue cleaning the surface of the substrate with a second cleaning solution, mainly removing particles and organic substances on the substrate, and then perform a third cleaning step with a third cleaning solution, mainly cleaning the substrate on the substrate. The heavy metal ions and other residual liquid on the bottom of the chemical enter the formation process, and the interface can be reached. After the ring is deposited equivalent to the subsequent body, the first particles or chemicals are cleaned in one step. The substrate-reactive layer is quality-free when it is protected from damage and oxidation. A better expected effect through the above multiple steps is with oxygen and carbon, plus the thickness of this layer during deposition control. The substrate gate boundary electrical oxidation layer 'once washed the substrate, and since most of it has been removed at this time, the first cleared into a very thin chemical oxide layer, thinning the surface of the substrate on subsequent high-temperature thermal-dimensional substrates and gates. The 'monthly cleaning procedure of the contact between the oxide layers, cleaning on the substrate, that is, the cleaning in these several steps: impurities such as hydrogen will not be easy to reattach. 4 The formation of a chemical oxide layer, and also provide a good contact interface, All these are conducive to reduction.

1222179 V. Description of the invention (3) However, due to the waiting time after cleaning, the wafer is still in a vacuum-breaking environment where moisture and carbides are abundant. In this way, impurities will begin to accumulate on the substrate surface. 'And the waiting time is not shortened here, so that the impurities have more time to accumulate on the substrate. Various results will greatly reduce the previous work of cleaning the substrate, and reduce the effect of reducing the thickness of the equivalent oxide layer. As another improvement method disclosed in US Patent No. 6, 4 98, 107, the cleaned substrate is placed in a vacuum reaction chamber, and the heating temperature is between 20 ° C and 4 ° C. At the same time, the substrate is bombarded with an inert gas such as nitrogen or rat gas to remove impurities such as oxides or carbides remaining on the surface of the substrate, and then a gate dielectric layer is continuously grown on the surface of the substrate in the same chamber. on. On the bottom surface of the chamber of the gate, an electrical layer formed in a different cavity but a later cavity system (cluster and wafer before the formation of a water vapor dielectric layer), because the substrate is placed in a vacuum waiting, Because λ 'can effectively prevent the moisture and impurities from attaching to the substrate, a better contact interface quality is obtained. Moreover, the intermediate step is performed in the same-chamber, which can also reduce the transfer chamber. First, the step of depositing the conductive layer of the gate, except that the process used in this step is not in series with the chamber used in the previous step), this will cause the conductive layer of the gate to be deposited during this waiting process. In a vacuum-breaking environment, the chance of impurities sticking to the surface of the dielectric layer is also greatly increased.

1222179 V. Description of the invention (4) In view of this, the object of the present invention is to provide a method for manufacturing an NMMOS transistor integrating various process steps in a closed environment, in which a multi-chamber (mul ti-chamber) is used The series connection process of the reaction chambers and an environmental condition without breaking vacuum can not only effectively reduce the waiting time between process steps, but also avoid the deposition of water vapor and impurities on the substrate and the gate dielectric layer. It has a significant contribution to the reduction of the EOT of the component. In order to achieve the above object, the present invention provides a method for manufacturing a NMOS transistor, including the following steps: providing a substrate, performing a cleaning process on the surface of the substrate, and continuing to form a gate dielectric layer on the substrate, and then A plasma nitriding process is performed on the gate dielectric layer, and a tempering process is performed on the gate dielectric layer, and then a gate conductive layer is formed on the gate dielectric layer. The above steps are constituted as a series connection process, wherein the process has a multi-chamber reaction chamber and is maintained without breaking the vacuum, and each step is performed in a separate chamber of the multi-chamber reaction chamber. The multi-chamber reaction chamber tandem process can save the waiting time for wafers to be transported to and from different machines, and eliminate the waiting time for batch type injection of wafers in the traditional process, and the multi-chamber reaction The series connection process of the chamber is performed in a vacuum-proof environment. All of these are conducive to reducing the adhesion of impurities in the air to the surface of the substrate and the gate dielectric layer, so that the interface thickness between the layers does not increase, the EOT is reduced, and the effect of improving electrical properties is achieved. Finally, the gate conductive layer is patterned to form a gate structure, and a source and a drain are formed in the substrate on both sides of the gate structure.

Page 812222179 V. Description of the invention (5) The present invention further provides a method for manufacturing a CMOS transistor, including the following steps: providing a substrate having a first region where a NMOS transistor is scheduled to be formed and a PMOS transistor which is scheduled to form A second region of the crystal, and a first gate dielectric layer and a second gate conductive layer are sequentially formed on the first region and the second region on the substrate. Before the gate dielectric layer is formed, on the surface of the substrate, Perform a cleaning procedure. The above steps are constituted as a series connection process, wherein the process has a multi-chamber reaction chamber and is maintained without breaking the vacuum, and each step is then performed in a separate chamber of the multi-chamber reaction chamber. Continue to define the gate conductive layer to form a gate structure on the first region and the second region, respectively. A first mask layer is formed on the first region, and a P + doping is performed to form a source and a drain in the substrate on both sides of the gate in the second region. The gate, The transistor formed by the source and the drain is a PMOS transistor. The first mask layer is removed, a second mask layer is formed on the second region, and an N + doping is performed to form a source electrode in the substrate on both sides of the gate in the first region. A drain, the transistor formed by the gate, the source and the drain is a NMOS transistor. After that, the second cover layer is removed. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows:

0503-9763twf (nl); tsmc2002-1015; David.ptd page 9 1222179 V. Description of the invention (6) Implementation method Example 1

Electricity 22 = 1a to 1c, according to one embodiment of the present invention, NMOS ΠίΓ, the operation includes the following steps: as shown in FIG. 1a 'provide a substrate, j sequentially formed on the soil bottom 110 The material of the gate dielectric layer 120 and the gate conductive layer / and the middle substrate 110 can be silicon, the material of the gate dielectric layer 120 can be oxide oxide or oxynitride, and the thickness of the gate dielectric layer 120 Generally " at 10-20 angstroms, the material of the gate conductive layer 13o may be polycrystalline silicon. First, the substrate 11 is sent from the wafer transfer chamber 500 to the first reaction chamber 50 2 in the multi-chamber series connection chamber J, as shown in FIG. 5. A cleaning process is performed on the substrate 110 = ^, and the cleaning solution used in this cleaning process includes: ammonia, hydrogen peroxide, and deionized water, and the composition ratio of the composition is ~ 1: 1 ~ 2: 80. After concentration conversion, the weight percentage of ammonia is less than 2.3%. The working temperature of this cleaning procedure is generally between 25 ~ 45 ° C. After the cleaning process is completed, the substrate 110 is moved to the f / inverter / chamber 504 in the reaction chamber in series to perform thermal growth of the gate dielectric layer 120. The gate dielectric S is formed by the thermal oxidation method, and the operating temperature of the thermal oxidation method is large. After the dielectric layer 120 is formed, the substrate is transferred to the substrate. The third reaction chamber 506 in the chamber is connected in series, and a UH = red sequence is performed on the layer. The working temperature of the plasma nitridation process is generally between 10 and 350 degrees Celsius, and the working pressure is generally between 5 millitorr. ~ 5 is between 100 ~ 150 0 watts. After the completion of the electro-polynitriding process, it is performed in the fourth reaction chamber 508.

V. Description of the invention (7) A tempering procedure to damage by the bucket and the pimple. The tempering process ^ evening dual energy ^ the conductive layer 130 caused by the plasma to the gate dielectric layer 120 is determined by the fifth / V first temperature Roughly between 10 and 350 degrees Celsius. Sedimentation method. The low-pressure chemical vapor deposition process performed in the upper and lower chambers 510 has a multi-cavity anti-storage system ^ r ^ k. The system is composed of a series of processes. The individual chambers of the chamber are: Each step is reversed before this multi-cavity: ί: 5 ί: During the process of growing the gate dielectric layer 12 and the deposition gate conductive layer 13o, the wafer: processing ί:? Controlled waiting time, and these two sections Waiting for the carbide gas environment, a lot of oxygen or more, and thickening the surface layer of the equivalent oxygen bottom 110 and the closed dielectric layer 120] t technology ϊ 决? When this problem is resolved, whether it is to strengthen the cleaning each is covered.,部分 Serial part of the process steps are performed in the same chamber, etc., to prevent water and air from being exposed to the elephant on the substrate 110 or the gate dielectric layer 120. The reason is that the wafer still has the opportunity to be rolled during the process. , Yi Xiong, and the process steps have not been fully integrated into a series of = :; there is still waiting time between each step, but also promote the water, gas, miscellaneous-埶 t will be the cleaning process on the surface of the substrate 11 〇 ", Gate dielectric layer 120", rolling step, plasma nitriding process of gate dielectric layer 120, gate dielectric layer 12 :: fire process and charge The chemical vapor deposition of layers 1 to 30 and other steps are combined to form a multi-chamber reaction chamber in a tandem process, and to maintain the multi-chamber reaction: the unbreakable S shape of the chamber is considered to make the wafer in each process After the end of the step, the transmission process can still be in a vacuum-free environment to prevent the adhesion of water vapor and impurities. 5. Description of the invention (8). Τ ^ In the operation of the 5H series process, almost two steps between each step The next step is to carry out the next step, and it will continue to work, that is, the electricity will greatly reduce the thickness of the equivalent oxide layer, so as to: improve the electrical properties and quality of the 70 electricity bodies. Tiida's oxygen production further explains the stringency of the multi-chamber reaction chamber. 1 on the second reduction and component electrical properties, quality improvement: Girl brother 2 shown in the figure, the vertical position only happened (Angstroms), the horizontal axis is the wafer thickness of the observation layer 4 emulsified layer electrical layer 2 20 Electrical ° = ;: Gate dielectric layer m 220 is a series sequence: tempering process of 12 ° and interlayer dielectric layer 12 °, polynitriding process, but the idle dielectric step d and open dielectric layer 12. The tempering procedure of the electrician & 1 2 0 is not connected in series, 9 4 f) is also connected to the gate dielectric layer 12. The electrical tritium tandem is connected in series, but on the interlayer dielectric layer 12. The thermal oxidation step is not stringed: the tempering of layer 120 is known, and 260 is the electrical polynitriding process and connection of gate dielectric layer 1 120] Second: chemical: step, gate dielectric layer and gate dielectric layer 120 层 oxidation ^ Tempering procedure of layer m '28 0 is the tempering of the serial sequence and the gate dielectric layer) 20: The plasma nitriding process of the gate dielectric layer 120 is not connected in series. Ren Dan ’s deposition of the gate conductive layer 13 0 from 200 to 260 in the figure does not affect the change in thickness. It can be found that as the dream thickness is equal to the thickness of the chemical layer of the equivalent oxide thickness, Quite a significant increase in the number of concatenations, the equivalent oxygen connection of the 26 0 process is more complete than the process steps ^: salty ^ by the fruit, if the process steps are completely connected to the 200 process which is not connected to the king, its equivalent oxygen 1222179 5 2. Description of the invention (9) The thickness of the chemical layer can be reduced by 4 to 6 angstroms. It is very important to have a reduction effect of this size, especially for gates below 0.1 m. During the 280 process, the thickness of the equivalent oxide layer was increased again to the result of applying the 20,000 process. From this, it can be inferred that if the deposition step of the gate conductive layer 30 is connected in series with the foregoing steps, It is very possible to reduce the thickness of the equivalent oxide layer successively to less than 15 angstroms, and achieve better component quality. From Figures 3a and 3b, you can observe the series combination of different process steps. It also has a certain degree of influence on the electrical properties of the device, such as the improvement of the drain current and the control of the leakage current. ^ As shown in Figure 3a, the ordinate is the amount of leakage current (nanoamperes / micron), and the abscissa is the amount of saturated drain current (microamperes / micron). The hollow circle in p in Figure ^ is the gate dielectric layer The thermal oxidation step of 1.2, the gate dielectric layer, and the electric power of the gate dielectric layer: the oxidization process, the tempering process of the gate dielectric layer, and the hollow square in the sink diagram of the gate conductive layer are connected in series. The cleaning process of the 110 surface, = thermal oxidation step of the electrical layer 1 20, the gate dielectric layer] 20 :, the tempering process of the idle dielectric layer 120, the intermediate conductive layer, and the drain current distribution pattern 32g . It can be seen from the eyes that, when the current amount is (eg, 100 nanoamperes / micron), the current value is 3 spoons :) The current value is higher than that in status 34. The corresponding counterpart is approximately 30% higher (as shown in Figure 3b, as shown in Figure 3b. At 3b, the vertical axis is ㈣ // cm2), and the 帛 coordinate is the equivalent oxide thickness (Angstroms). ^ &Amp; of

0503-9763twf (nl); tsmc2002-1015; David.ptd p. 13 1222179

ί = The thermal oxidation step in the form of a gate dielectric layer 12G in series, the electro-nitriding procedure of the gate dielectric layer 120 and the tempering procedure of the gate dielectric layer 120, but the deposition step of the gate conductive layer ^ 30 is not Distribution of Equivalent Oxide Layer Thickness in Series

The hollow triangle in the figure is the thermal oxidation of the gate dielectric layer, the thermal oxide gate dielectric layer, and the dielectric layer, which are connected in series with the gate dielectric layer. The deposition step of the conductive layer U0, and the substrate The appearance of the equivalent oxide layer thickness distribution pattern when the surface cleaning roll sequence is not connected in series 37. The hollow shape in the figure is the thermal oxidation step of the gate dielectric layer 12 series, the gate dielectric layer " 〇 == Chemical procedure 1 Tempering procedure of the dielectric layer 12G, this and v step of the interconducting layer 13 °, and equivalent distribution pattern 3 90 during the cleaning procedure of the surface of the substrate 1 10. "+ &Amp; It can be seen in the figure that with the increase in the number of concatenations in the process steps, such as state 350 to state 39 0, the equivalent oxide thickness can be up to 20.1 angstroms to 19.5 angstroms, generally The h 4 Angstrom is reduced, and the leakage current here only increases slightly and slowly. Next, as shown in FIG. Lb, the gate conductive layer 30 is defined to form a gate structure 132, and the step of defining the gate pattern can be etched by an isotropic surname in dry etching such as reactive ion etching (R IE) Technology reached.

As shown in FIG. 1C, the 卩 —light # impurity ion implantation procedure forms a lightly doped drain region in the substrate 1 10 on both sides of the gate, and then continues by chemical vapor deposition on the substrate. A sidewall 134 is grown on the side wall of the gate electrode 132, and then a heavily doped ion implantation process is performed on both sides of the lightly doped drain region 14 to form a 3 pole 150 and a drain 16 to form _NM. 〇s transistor structure 100, of which

1222179 V. Description of the invention (11) The lightly-doped and heavily-doped ionic implantation procedures are performed using plasmas such as cans or shishen. Embodiment 2 Please refer to FIGS. 4 a to 4 c. According to another embodiment of the present invention, a method for fabricating a CMOS transistor. First, as shown in FIG. 1, a substrate 41 is provided. The substrate has a predetermined structure. Form a first region 42 of the NMOS transistor and a second region 430 that is scheduled to form a PMOS transistor. The first region 420 and the second region 430 on the substrate 410 sequentially form a gate dielectric. The layer 435 and a gate conductive layer 46, wherein the material of the substrate 410 may be silicon, and the material of the gate dielectric layer 4 35 may be nitride nitride, silicon oxide, or silicon oxynitride, and the gate dielectric layer 43 The thickness of 5 is generally between 10 and 20 angstroms, and the material of the gate conductive layer 460 may be polycrystalline silicon. First, the substrate 410 is sent from the wafer transfer chamber 5000 to this multi-chamber tandem reaction. The first reaction chamber 512 in the chamber is shown in Figure 5. On the surface of the substrate 10, a cleaning process is performed. The cleaning liquid used in this cleaning process includes ammonia, hydrogen peroxide, and deionized water. , The composition of the mixing ratio is 0.25 ~ 1: 1 ~ 2 ... 80. After concentration conversion, the weight of ammonia water For the rate, the temperature is less than 2.3%. The working temperature of this cleaning procedure is generally between 25 and 45 degrees Celsius. After completing the cleaning procedure, continue to move the substrate 41 to the second reaction chamber in the tandem reaction chamber. The chamber 514 is used for thermal growth of the gate dielectric layer 435. The gate dielectric layer 435 is formed by the thermal oxidation method, and the operating temperature of the thermal oxidation method is generally between 7 00 and 1200 degrees Celsius. The layer 435 also includes a thermal nitriding process. The reaction gas system of the thermal nitriding process includes ammonia.

1222179 V. Description of the invention (12) (NH3), nitric oxide (N0) or nitrous oxide (N2O). The gate conductive layer 460 is deposited by a low-pressure chemical vapor deposition method performed in the third reaction chamber 51-6. The above steps are performed in separate chambers of a multi-chamber reaction chamber without breaking the vacuum to form a series connection process. ~ The gate conductive layer 460 is patterned, as shown in FIG. 4b, to form a gate structure 442, 452 on the first region 420 and the second region 430, respectively. As shown in FIG. 4c, a first mask layer 47o is formed on the _ area 42o, and a P + doping is performed. A source 480 and a drain 490 are formed in the substrate 410 on both sides of the gate 4 5 2 in the second region 4 3 0. The gate 452, the source 480 and the drain 490 are formed. The transistor is a pM0s transistor 400, as shown in FIG. 4d. The first mask layer 470 is removed, a second mask layer 495 is formed on the second region 430, and an N + doping is performed, as shown in the figure ". The gate electrode in the first region 420 A source / 44 and a sum electrode 4 4 6 are formed in the substrate 410 on both sides of 442. The transistor 4 4 2, the source 4 4 4 and the drain 4 4 6 constitute an NMOS. The transistor 405, as shown in FIG. 4f, is thereafter removed from the second cover layer 495. Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit or limit the present invention. Anyone skilled in the art, Changes and modifications can be made without departing from the scope and scope of the present invention. Therefore, the scope of protection of the present invention is determined by the scope of the attached patent application.

1222179 Brief description of the drawings Figures 1a to 1c are schematic cross-sectional views of an NMOS transistor process according to an embodiment of the present invention. Fig. 2 is a schematic diagram of comparison of equivalent oxide layer thicknesses according to different series combinations according to an embodiment of the present invention. Fig. 3a is a schematic diagram of a comparison of the amount of saturation anode current according to different series combinations according to an embodiment of the present invention. Figure 3b is a schematic diagram comparing the equivalent oxide layer thickness and the leakage current according to different series combinations according to an embodiment of the present invention.

4a to 4f are schematic cross-sectional views of a CMOS transistor structure according to another embodiment of the present invention. Figure 5 is a top perspective view of a multi-chamber series reaction chamber according to an embodiment of the present invention. Explanation of symbols 100, 40 5 ~ NM0S transistor; 110, 410 ~ substrate; 120, 435 ~ gate dielectric layer; 130, 132, 44 2, 45 2, 460 ~ gate conductive layer;

1 4 0, 4 4 5, 4 8 5 ~ lightly doped electrodeless region; 150, 444, 48 0 ~ source; 160, 446, 490 ~ drain; 2 0 0 ~ completely unconnected process group; 22 0, 24 0, 28 0, 34 0, 3 5 0, 37 0 ~ Incomplete process

0503-9763twf (nl); tsmc2002-1015; David.ptd page 17 1222179 The drawing briefly illustrates the process group of 260, 320, 390 ~ completely connected; 40 0 ~ PMOS transistor; 4 2 0 ~ the first area; 4 3 0 ~ second area; 4 70 ~ first cover layer; 49 5 ~ second cover layer; 5 0 0 ~ wafer transfer chamber; 50 2 5 1 2 ~ first reaction chamber; 5 0 4, 5 1 4 to the second reaction chamber;

506, 516 to the third reaction chamber; 508 to the fourth reaction chamber; and 510 to the fifth reaction chamber.

0503-9763twf (nl); tsmc2002-1015; David.ptd p.18

Claims (1)

1222179 VI. Scope of patent application 1. A method for manufacturing an N-type metal-oxide-semiconductor (NMOS) transistor, including the following steps: providing a substrate; performing a cleaning process on the surface of the substrate; forming a gate dielectric layer on the substrate; On the substrate; performing a plasma nitridation process on the gate dielectric layer; performing a tempering process on the gate dielectric layer; forming a gate conductive layer on the gate dielectric layer; and the above steps are performed in more than one step Multi-chamber reaction chambers are performed in individual chambers without breaking vacuum to form a cluster process. 2. The method for manufacturing an N-type metal-oxide semiconductor transistor as described in item 1 of the scope of patent application, wherein the substrate is a shixi substrate. 3. The method for manufacturing an N-type metal-oxide semiconductor transistor as described in item 1 of the patent application scope, wherein the gate dielectric layer is composed of silicon nitride, silicon oxide, or silicon oxynitride. 4. The method for manufacturing an N-type metal-oxide semiconductor transistor as described in item 1 of the scope of patent application, wherein the thickness of the gate dielectric layer is generally between 10 and 20 angstroms. 5. The method for manufacturing an N-type metal-oxide semiconductor transistor as described in item 1 of the scope of patent application, wherein the gate conductive layer is composed of polycrystalline silicon. 6. The method for manufacturing an N-type metal-oxide semiconductor transistor as described in item 1 of the scope of the patent application, wherein the cleaning procedure uses a cleaning solution, and the cleaning solution includes ammonia, hydrogen peroxide, and deionized water. 7. Manufacturing of N-type metal-oxide semiconductors as described in item 6 of the scope of patent application 0503-9763twf (nl); tsmc2002-1015; David.ptd page 19 1222179 6. Method for applying for a patent, wherein the mixing ratio of the ammonia, hydrogen peroxide and deionized water is 0 · 2 5 ~ 1: 1 ~ 2 ·· 80, and the weight percentage concentration of the ammonia water is less than 2.3 ° / 〇. 8. The method for manufacturing an N-type metal-oxide-semiconductor crystal as described in item 1 of the scope of the patent application, wherein the working temperature of the cleaning procedure is generally between 25 and 45 degrees Celsius. 9. The method for manufacturing an N-type metal-oxide-semiconductor crystal according to item 1 of the scope of the patent application, wherein the gate dielectric layer is formed by thermal oxidation. 10. The method for manufacturing an N-type metal-oxide semiconductor transistor as described in item 9 of the scope of patent application, wherein the operating temperature of the thermal oxidation method is generally between 70 ° C and 120 ° C. 11. The manufacturing method of the N-type metal-oxide semiconductor transistor described in the first item of the scope, wherein the working temperature of the plasma nitriding process is generally between 10 and 350 degrees Celsius, and the working pressure is generally between 5 mTorr and 5 torr. The power is generally between 100 and 1500 watts. 12. The method for manufacturing an N-type metal-oxide-semiconductor crystal according to item 1 of the scope of patent application, wherein the working temperature of the tempering process is generally between 10 and 350 degrees Celsius. 13. The method for manufacturing an N-type metal-oxide-semiconductor crystal according to item 1 of the scope of the patent application, wherein the gate conductive layer is formed by a low-pressure chemical vapor deposition method. 1 4. The method for manufacturing an N-type metal-oxide semiconductor transistor as described in item 1 of the scope of patent application, wherein the step of forming the gate conductive layer further comprises: patterning the gate conductive layer to form a gate structure; as well as 0503-9763twf (nl); tsmc2002-1015; David.ptd Page 20 1222179 Sixth, the scope of the patent application forms a source and a drain in the substrate on both sides of the gate structure 15.-N-type gold oxide A semi-t crystal manufacturing method includes the following steps: A substrate is provided on the substrate to sequentially form a closed dielectric layer and a conductive layer; on the surface of the substrate, before the gate dielectric layer is formed, A cleaning procedure is performed; and the above steps are performed in individual chambers of a multi-chamber reaction chamber without breaking the vacuum to form a series connection process. 16 · The method for manufacturing an N-type metal-oxide-semiconductor crystal as described in item 15 of the scope of patent application, wherein the substrate is a silicon substrate. 17 · The method for manufacturing an N-type metal-oxide-semiconductor crystal according to item 15 of the scope of patent application, wherein the gate dielectric layer is composed of silicon nitride, silicon oxide, or oxynitride. 18. The method for manufacturing an N-type metal-oxide-semiconductor crystal according to item 5 in the scope of the patent application, wherein the thickness of the gate dielectric layer is generally between 10 and 20 angstroms. 1 9 · The method for manufacturing an N-type metal-oxide-semiconductor crystal as described in item 15 of the scope of patent application, wherein the gate conductive layer is composed of polycrystalline silicon. The method for manufacturing an N-type metal-oxygen semi-electric f lotion according to item 5, wherein the cleaning procedure is a use / cleaning solution and the month system includes ammonia, hydrogen peroxide, and deionized water. " Lei Yueti No. 21. Such as the application of the scope of the patent No. 20 households described N-type metal oxygen === example of the manufacturing method, wherein the ammonia, hydrogen peroxide and female ion water mixture: the system is 0. 25 ~ 1: ： 1 ~ 2: 80, and the weight percentage of the ammonia water is 1222179 At 2.3%. The N-type metal-oxygen semi-thunder manufacturing method as described in item 15 of Shenyan's patent scope, wherein the working temperature of the cleaning procedure is approximately between 45 degrees and 45 degrees. Stomach 2 3 · The N-type metal-oxygen semi-electric manufacturing method as described in item 15 of the Shin-Ken patent scope, wherein the gate dielectric layer is formed by thermal oxidation. 3 _ of 24 · The N-type metal-oxygen semi-electric manufacturing method as described in item 23 of the scope of patent application, wherein the operating temperature of the thermal oxidation method is generally between 700 and 1200 degrees of 9 _. 25 ° C · The N-type metal-oxygen semi-thunder method xe method described in item 15 of the scope of patent application, wherein the gate dielectric layer is formed and a normalization process is also included. 1T cooked rat • 2 6 · The method for manufacturing N-type metal oxysemiconductor as described in item 25 of the patent application scope, wherein the reaction gas system of the thermal nitridation process includes ammonia-of (NΗ3), nitric oxide (NO) or nitrous oxide (N20).卞 少 ， 2 7 · The method for manufacturing N-type metal-oxide-semiconductor crystals as described in item 5 of the patent application scope, wherein the gate conductive layer is formed by low-pressure chemical vapor deposition = sink =. 2. 28. The method for manufacturing an N-type metal-oxide-semiconductor crystal as described in item 5 of the patent application scope, wherein after forming the gate conductive layer, the method further includes: patterning the gate conductive layer to form a gate. A pole structure; and a source and a drain formed in the substrate on both sides of the gate structure. 29 · —A method for manufacturing a complementary metal oxide semiconductor (CM0s) transistor, including the following steps: 0503-9763twf (nl); tsmc2002-l0l5; David.ptd α々179 'Scope of patent application —. A substrate is provided. The substrate has an upper region that is intended to form a nmos transistor and a second region that is intended to form a PMOS transistor, and a gate is sequentially formed on the substrate " Heihe region and the second region. The dielectric layer is a conductive layer; 前 Before the formation of the edge gate dielectric layer, a cleaning process is performed on the surface of the substrate; and each step is described in a separate chamber of a multi-chamber reaction chamber. And different, empty to form a series connection process. Body 7 · The manufacturing method of the complementary metal-oxide-semiconductor one described in item 29 of the patent application scope, wherein the substrate is a silicon substrate. 31. The complementary metal-oxide-semiconductor method described in item 29 of the scope of the patent application, wherein the gate dielectric layer is composed of silicon nitride, silicon oxide, or silicon nitride. 〆, 埃 32 · The manufacturing method of complementary metal-oxide-semiconductor as described in item 29 of the patent application scope, wherein the thickness of the gate dielectric layer is generally between 10 and 20 crystals_ 33 · The method for manufacturing a complementary metal-oxide-semiconductor crystal according to item 29, wherein the gate conductive layer is composed of polycrystalline silicon. 34. The complementary metal-oxygen halves as described in item 29 of the scope of the patent application, wherein the cleaning process uses a cleaning solution, and the cleaning solution includes ammonia, hydrogen peroxide, and deionized water. . 3 5 · The manufacturing method of the complementary metal-oxygen semi-thunder body as described in item 34 of the scope of patent application, wherein the mixing ratio of the ammonia water, hydrogen peroxide water and deionized water is 0.2 5 to 1: 1 ~ 2: 80, and the weight percentage concentration of the ammonia water 0503-9763twf (nl); tsmc2002-1015; David.ptd page 23 1222179 VI. The scope of patent application is less than 2.3%. 36. The method for manufacturing a complementary metal-oxide semiconductor as described in item 29 of the scope of the patent application, wherein the working temperature of the cleaning process is generally between 25 and 45 degrees Celsius. 37. The method for manufacturing a complementary metal-oxide semiconductor as described in item 29 of the scope of the patent application, wherein the gate dielectric layer is formed by a thermal oxidation method. 38. The method for manufacturing a complementary metal-oxide-semiconductor as described in item 37 of the scope of the patent application, wherein the working temperature of the thermal oxidation method is generally between 700 and 1200 degrees Celsius. 39. The method for manufacturing a complementary metal-oxide-semiconductor as described in item 29 of the patent application scope, wherein forming the gate dielectric layer further includes performing a thermal nitridation process. 40. The method for manufacturing a complementary metal-oxide-semiconductor as described in item 39 of the scope of the patent application, wherein the reaction gas system of the thermal nitriding process includes ammonia, nitrogen monoxide, or nitrous oxide. 41. The method for manufacturing a complementary metal-oxide-semiconductor crystal according to item 29 of the scope of the patent application, wherein the gate conductive layer is formed by low-pressure chemical vapor deposition. 42. The method for manufacturing a complementary metal-oxide-semiconductor crystal according to item 29 of the patent application scope, wherein the step of forming the gate conductive layer further comprises: defining the gate conductive layer to form a gate structure respectively On the first region and the second region; forming a first mask layer on the first region; and performing a P + doping to form a substrate on both sides of the gate of the second region Source 0503-9763twf (nl); tsmc2002-1015; David.ptd page 24 1222179 6. The scope of patent application and a drain, the transistor formed by the gate, the source and the drain is a PMOS transistor; Removing the first mask layer; forming a second mask layer on the second region, and performing an N + doping to form a source electrode in the substrate on both sides of the gate electrode in the first region; A drain, the transistor formed by the gate, the source, and the drain is an NMOS transistor; and the second mask layer is removed. 0503-9763twf (nl); tsmc2002-1015; David.ptd p. 25