玖、發明說明 【發明所屬之技術領域】 本發明是有關於一種半導體積體電路之線路架構,且 特別是有關於-種功率金氧半電晶體產品之線路架構。 【先前技術】 常見的功率半導體有功率金氧半電晶體 M〇SFET)、絕緣閘極雙載子電晶體(insulated gate bip〇iar transistor ; IGBT)以及蕭基氏二極體(Sch〇uky di〇de)。這 些功率半導體通常需要能夠攜帶大電流、承受高逆向偏壓 以及將元件處於逆向偏壓下之漏電流降至最低。這些功率 半導體之應用非常廣泛,例如功率金氧半電晶體可應用在 、/气車之電力系統與電源供應裔等等,這些都是市場上常見 之商品。 但是以能攜帶大電流之功率金氧半電晶體來說,因為 其P型基體區無法在N型蟲晶石夕層中形成似無限平行 (semi-infinite parallel)之p-n接面,因此在「關」的狀態 下,易因為電崩潰而使p-n接面產生漏電流。請參考第 1A圖,第1A圖係繪示習知功率金氧半電晶體之p型基 體區與N型蠢晶石夕之p-n接面邊緣的剖面結構示意圖。在 第1A圖中,因為P型基體區110與]Sf型蠢晶;^ 1〇〇之 Ρ-η接面邊緣的空乏區120之曲度較大,所以電場密度較 大,如第1Α圖中箭頭所示。因此常在ρ型基體區no與 Ν型磊晶矽100之ρ-η接面邊緣在較低之電壓下就產生電 1220784 崩潰而產生漏電流。因此,一般都會在晶粒(die)上之元件 主動區的邊緣設計主動區終止結構(terminati〇n structwe) 來防止電崩潰現象的發生。 請參考第1B圖與第1C圖,一般元件主動區邊緣的 終止結構有兩種,一種是場環(field ring),一種是場板 (field plate)。第1B圖係繪示習知利用場環以減少功率金 氧半電晶體之P型基體區與N型磊晶矽之p_n接面邊緣 的曲度,以減少該處之電場密度。在p型基體區11〇之外 側再形成一個比P型基體區110要小得多之p型摻雜區 130作為場環,用以減少空乏區12〇a邊緣之曲度,進而 減少此處之電場密度。 第1C圖係繪示習知利用場板以減少功率金氧半電晶 體之P型基體區與N型磊晶矽之P_n接面邊緣的曲度, 以減少該處之電場密度。或者在p型基體區11〇之外側對 N型磊晶矽層丨00施予和p型基體區【丨〇相同大小之偏 壓,亦即透過場板14〇對N型磊晶矽層1〇〇施以逆向偏 壓則叮以減少空乏區120a邊緣之曲度,進而減少此處 之電場密度。 在習知之有關功率金氧半電晶體之產品設計上,係在 1極連接線(gate bus)之外圍佈上場板線路,而場板線路 疋與源極金屬連接,亦即和源極為等電位。但是此種設計 頗伯空間’無法有效地減少晶粒尺寸,因此本發明提供— 種新的線路架構來解決此問題。 6 1220784 【發明内容】 因此本發明的目的就是在 體產品之線路架構,用以m 種功羊金義半電晶 亍稱用以大幅縮小產品晶粒的尺寸。 根據本發明之上述目 上您目的,提出一種功率金氧半 產品之線路架構,該線路架盖 日日一 接線與閘極墊所組成。上述 €極連 晶體陣列之源極相接,而 和卞电 金屬之外η“ “ 接線係圍繞在源極 ®、〜、功旱金氧半電晶體陣列之間極相接。閘極 畜、1立於源極金屬之—側並與閑極連接線相接。當功率金 氧半電晶體陣列處於「關」的狀態時,上述之閉極連接線 做為場板連接線之用。上述之閘極塾與閘極連接線可由同 一層多晶矽層所構成。 因為在功率金氧半電晶體處於「關」的狀態時對Ρ 型基體區與Ν型蟲晶石々® + k f l猫日日矽層之p-n接面漏電流較為敏感,而 ㈣閘極之f壓與源極相同’皆為接地。所以可將場板連 接線與閘極連接線合而為—,如此可節省十分大之空間, 對於產品晶粒尺寸之減少十分有幫助。 【實施方式】 〇月多第2圖,其繪示依照習知之功率金氧半電晶體 產品之線路架構俯視示意圖。在第2圖中,基板200上具 有功率金氧半電晶體陣列,此功率金氧半電晶體陣列被源 極金屬2 1 〇所覆蓋住。源極金屬2 1 〇經由介層窗220與圍 %在源極金屬2 1 0周圍之場板連接線230相接,因此源極 1220784 金屬210與場板連接線23〇為雷 比炎吐L ^ & ^ ^ 寺電位,白為接地。在場板 = 與 屬210之間,則為與功率金氧半電晶 體陣列的閘極相接之閘極連接線 盥„托埶, 〇。閘極連接線240亦 與閘極墊(gate pad) 250相接。 提供與外部電路相接之接觸面^屬210與閑極塾⑽ 由第2圖之設計可知為了要維 陣列在「關」日夺,其邊緣之„ & &牛電曰曰體 亚少h玄… ㈣接面不會有漏電流,必須 要在功率金氧半電晶體陣列 2,n ± 干幻之邊緣圍繞一圈場板連接線 /曰杨板連接線23G佔據了相當大之晶粒面積,因 此日日粒尺寸很難再進一步縮小。 、 因為在功率金氧半電晶體 之電流相當大,因…不2為開」時’其所攜帶 法。…又不到等級約* 1〇_9安培之漏電 μ但疋虽功率金氧半電晶體陣列為「 之漏電流就影響非當大,田& W』 上4寺、、及 童以曰Μ 場板連接線之功用在功率金 氧半電晶體陣列為「|| η± ^ ^ ^關」時較為重要。又習知之場板連接 線之設計是與源極金屬箄雷你门士 琢板連接 電晶體陣列為「關 刀手i乳牛 據本發明之一較佳實施你丨收s U此根 實也例,將场板連接線與閘極連接線合 ”、、,八、、、路架構圖請參照第3圖。 第3圖係!會示佑昭士文 .^ χ ^ …、本發明一較佳實施例的一種功率 金氧半電晶體產品夕綠物* 7J ^ 之線路采構俯視示意圖。在第3圖中, 基板300上之功率今氫坐 手金虱+電晶體陣列被源極金屬3 蓋。場板連接線以閘極„ 蜀j 10所覆 閘極連接線320取而代之,在功率全 半電晶體陣列為「關^ ^ 」夺考x揮作用。閘極連接線3 2 0亦與 1220784 閘極墊330相接。源極金屬21〇與閘極墊25〇提供與外部 電路相接之接觸面。上述之閘極連接線32〇與閘極墊 幸乂佳為利用同一層之多晶石夕層所形成。 s由上述本發明較佳實施例可知,本發明將閘極連接線 ^場板連接線合而為一,不僅可以維持場板連接線之功 月b還可以即省場板連接線所佔據之面積。因此,對於產 品晶粒之縮小,十分有幫助。 雖然本發明已以一較佳實施例揭露如上,然其並非用 以限:本發明,任何熟習此技藝者,在不脫離本發明之精 神和乾圍内’當可作各種之更動與潤飾,因此本發明之 護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 為讓本發明之上述和其他目的、特徵、和優點能 顯易懂’下文特舉一較佳實施例,並配合所 細說明如下: F # 第1A圖係纷示習知功率金氧半電晶體之?型 與N型蟲晶石夕之p_n接面邊緣的剖面結構示意圖。土-第1B圖係緣示習知利用場環以減少功率金氧半2. Description of the invention [Technical field to which the invention belongs] The present invention relates to a circuit architecture of a semiconductor integrated circuit, and in particular, to a circuit architecture of a power metal-oxide semiconductor product. [Prior technology] Common power semiconductors include power metal-oxide semiconductors (MOS transistors), insulated gate bipolar transistors (IGBTs), and Schottky diodes (Schooky di〇 de). These power semiconductors typically need to be able to carry large currents, withstand high reverse bias voltages, and minimize leakage currents to components under reverse bias voltages. These power semiconductors are used in a wide range of applications. For example, power metal-oxide semiconductors can be used in the power system and power supply of gas cars. These are common products in the market. But for a power metal-oxide semiconductor that can carry a large current, because its P-type matrix region cannot form a semi-infinite parallel pn junction in the N-type wormite layer, so In the "off" state, it is easy to cause leakage current due to electrical breakdown. Please refer to FIG. 1A. FIG. 1A is a schematic diagram showing the cross-sectional structure of the edge of the p-n junction between the p-type matrix region of a conventional power metal-oxide semiconductor transistor and the N-type spun stone. In FIG. 1A, because the curvature of the empty region 120 at the edge of the P-η junction of the P-type matrix region 110 and the Sf-type stupid crystal; ^ 100, the larger the electric field density, as shown in FIG. 1A. Shown by the middle arrow. Therefore, in the p-type substrate region no and the ρ-η junction edge of the N-type epitaxial silicon 100, an electrical 1220784 collapse occurs at a lower voltage and a leakage current is generated. Therefore, an active region termination structure (termination structwe) is usually designed on the edge of the active region of the element on the die to prevent electrical breakdown. Please refer to FIG. 1B and FIG. 1C. There are two types of termination structures at the edge of the active area of general components. One is a field ring and the other is a field plate. FIG. 1B shows the conventional use of a field ring to reduce the curvature of the edge of the p-type junction between the P-type base region of the power metal-oxide semiconductor and the n-type epitaxial silicon to reduce the electric field density there. A p-type doped region 130, which is much smaller than the p-type substrate region 110, is further formed as a field ring on the outside of the p-type substrate region 110, which is used to reduce the curvature of the edge of the empty region 120a, thereby reducing this. The electric field density. Figure 1C shows the conventional use of a field plate to reduce the curvature of the P-type substrate region of the power metal-oxide semiconductor and the P_n junction edge of the N-type epitaxial silicon to reduce the electric field density there. Alternatively, the N-type epitaxial silicon layer is applied to the N-type epitaxial silicon layer on the outside of the p-type substrate region 11o, and the bias voltage is the same as that of the p-type substrate region. 〇〇 Applying a reverse bias will reduce the curvature of the edge of the empty region 120a, thereby reducing the electric field density here. In the conventional product design of power metal-oxide semiconductor transistors, field plate circuits are placed on the periphery of the gate bus, and the field plate circuit is connected to the source metal, which is equal to the source electrode. . However, this design Pube space 'cannot effectively reduce the grain size, so the present invention provides a new circuit architecture to solve this problem. 6 1220784 [Summary of the invention] Therefore, the object of the present invention is the circuit structure of an in-vivo product, which is used for m kinds of power semiconductor gold sense semi-transistors. According to the above purpose of the present invention, a circuit structure of a power metal oxide product is proposed. The circuit frame cover is composed of a daily connection and a gate pad. The above electrodes are connected to the source of the crystal array, and η "" wirings outside the galvanic metal are connected around the source ®, ~, and alumina-metal oxide semi-electric crystal arrays. Gate animal, 1 stands on the side of the source metal and is connected to the idler connection line. When the power metal-oxide-semiconductor array is in the "off" state, the above-mentioned closed-pole connection line is used as a field plate connection line. The above-mentioned gate electrodes and gate connection lines may be formed of the same polycrystalline silicon layer. Because when the power metal-oxide semiconductor is in the "off" state, it is more sensitive to the leakage current of the pn junction of the P-type matrix region and the N-type worm crystal 々® + kfl cat day silicon layer, and the f The voltage and source are the same. Therefore, the field board connection line and the gate connection line can be combined into one, which can save a very large space, which is very helpful for reducing the grain size of the product. [Embodiment] FIG. 2 is a schematic diagram showing a top view of a circuit structure of a conventional metal-oxide-semiconductor product according to conventional power. In FIG. 2, the substrate 200 has a power metal-oxide semiconductor array, and the power metal-oxide semiconductor array is covered by the source metal 210. The source metal 2 1 〇 is connected to the field plate connection line 230 surrounding the source metal 2 1 0 through the interlayer window 220. Therefore, the source 1220784 metal 210 and the field plate connection line 23 are Rayby Yantu L ^ & ^ ^ Temple potential, white for ground. Between the field plate = and the 210, it is the gate connection line connected to the gate of the power metal-oxide semiconductor transistor array. The gate connection line 240 is also connected to the gate pad. ) 250 contacts. Provides contact surfaces for connection with external circuits. ^ Belongs to 210 and idle pole. From the design of Figure 2, we know that in order to maintain the array in the "off" day, the edge of the & & The body is small and thin. The junction will not have a leakage current, and it must be surrounded by a circle of field plate connection line / Yang plate connection line 23G on the edge of the power metal-oxide semiconductor transistor array 2, n ± dry magic. Because of the relatively large grain area, it is difficult to further reduce the size of the daily grains. Because the current of the power metal-oxide semiconductor is quite large, because ... when 2 is not on, it's the carrying method. … It's less than the level of about * 10 ~ 9 amps of leakage current μ. However, although the power metal-oxide semiconductor transistor array is "the leakage current will affect the unreasonable, Tian & W" on the 4th Temple, and Tong Yiyue The function of the Μ field plate connection line is more important when the power metal-oxide semiconductor transistor array is "|| η ± ^ ^ ^ Off". It is also known that the design of the field board connection line is to connect the transistor array with the source metal thymine slab, and it is "Kuan Dao Shou I Dairy Cow. According to one of the inventions, you can implement it. This example is also an example. , Make the field board connection line with the gate connection line. Picture 3! ^ ^ ^ ^, A preferred embodiment of the present invention, a power metal-oxide semiconductor product, green material * 7J ^, a schematic top plan view of the circuit structure. In FIG. 3, the power on the substrate 300 is covered with the source metal 3 and the crystal array is covered by the source metal 3. The field board connection line is replaced by the gate electrode «Shu J 10, and the gate connection line 320 is replaced, which is used to test the x-wave effect in the power full half transistor array. The gate connection line 3 2 0 is also connected to the 1220784 gate pad 330. The source metal 21o and the gate pad 25o provide a contact surface for contact with an external circuit. The gate connecting line 32 and the gate pad described above are formed by using a polycrystalline layer of the same layer. From the above-mentioned preferred embodiments of the present invention, it can be known that the present invention integrates the gate connection line ^ the field plate connection line into one, not only can maintain the power of the field plate connection line b, but also can be occupied by the provincial field plate connection line area. Therefore, it is very helpful for the reduction of product grains. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit it: the present invention, anyone skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention, Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application. [Brief description of the drawings] In order to make the above and other objects, features, and advantages of the present invention comprehensible ', a preferred embodiment is exemplified below, and the detailed description is as follows: F # FIG. 1A Know the power of metal oxide semiconductors? Schematic diagram of the cross-sectional structure of the edge of the p_n junction with the N-type spar stone. Soil-Figure 1B shows the use of a field ring to reduce power
體之P型基體區與石曰访夕 & 会 M n 型猫日日矽之p_n接面邊緣的曲声, 以減少該處之電場密度。 a 乐ic圖係繪示習知利用場板 〜7切千^ 體之Ρ型基體區與Ν型磊晶矽之”接面邊与 電晶度, 1220784 以減少該處之電場密度。 電晶體產品之 第2圖係繪示依照習知之功率金氧半 線路架構俯視示意圖。 第3圖係繪示依照本發明一較佳實施例的一種功率 金氧半電晶體產品之線路架構俯視示意圖。 【元件代表符號簡單說明】 100 : N型遙晶石夕 110 : P型基體區 120、120a、120b:空乏區 1 3 0 : P型掺雜區 140 :場板 200 > 300 :基板 2 1 0、3 1 0 :源極金屬 220 :介層窗 230 :場板連接線 2 4 0、3 2 0 :閘極連接線 250、330 :閘極墊 10The P-type base area of the body and Shi Yue's visit to the evening will sing at the edge of the p_n junction of the M n -type cat Riri silicon to reduce the electric field density there. a The Leicing diagram shows the conventional use of a field plate ~ 7 cuts of the P-type base region of the body and the N-type epitaxial silicon "junction edge and electrical crystallinity, 1220784 to reduce the electric field density there. Transistor The second diagram of the product is a schematic plan view of a power metal-oxide-semiconductor circuit structure according to the conventional art. The third diagram is a schematic diagram of a circuit structure of a power metal-oxide-semiconductor product according to a preferred embodiment of the present invention. Simple description of element representative symbols] 100: N-type telexite 110: P-type base region 120, 120a, 120b: empty region 1 3 0: P-type doped region 140: field plate 200 > 300: substrate 2 1 0 , 3 1 0: source metal 220: interlayer window 230: field plate connection line 2 4 0, 3 2 0: gate connection line 250, 330: gate pad 10