TWI283514B - CMOS buffer circuits, and integrated circuits and ring oscillation circuits using circuit - Google Patents

Abstract

CMOS buffer circuits with reduced short circuit current. In the CMOS buffer circuit, an output stage drives an output terminal and comprises a first output transistor of a first conductive type and a second output transistor of a second conductive type. An output driving unit produces a first signal to turn off the first output transistor according to a delay signal. A bidirectional delay unit is controlled by the input signal to turn on the second output transistor after the first output transistor be turned off. In the bidirectional delay unit, a bidirectional logic unit generates two logic signals according to an inversion signal of the input signal, first and second bidirectional buffers are coupled to the output driving unit, generating a second signal to turn on the second output transistor according to the input signal and the two logic signals.

Description

1283514 IX. Description of the Invention: [Technical Field] The present invention relates to a snubber circuit, and more particularly to a snubber circuit capable of reducing a short-circuit current and an associated integrated circuit and a ring-shaped oscillating circuit. ·~--- [Previous technical standard] The CMOS buffer circuit is widely connected to the driver circuit of the stage. In general, the electrical energy loss of a CMOS circuit is a dynamic electric energy loss or a short-circuit electric energy loss, and the dynamic electric energy loss is unavoidable, but the short-circuit electric energy loss causes the electric energy to be inspected. With the advancement of process technology: MOS electro-crystals evade the blanket j, making the secret current often occur. In order to reduce the short-circuit power consumption, the current focus is on reducing the short-circuit current of a buffer (10) such as a clock buffer with a high switching rate. In addition, the short-circuit current of the CMOS buffer also causes electrostatic interference (EMI). Therefore, reducing the short-circuit current of the CM〇s snubber circuit will be a very important issue. Various methods have also been proposed to reduce the short circuit current of the CMOS buffer circuit. The first diagram shows a CMOS snubber circuit 200 capable of reducing the short circuit current, however, the short circuit current does not only occur in the pre-driver stage 310' but also occurs in the output driver stage 350. For example, when the input dust (IN) is initially at a low level, the nodes 20 and 30 will be at a high level, causing the transistors M36-M37 to turn on and the transistor M38 to turn off. When the input voltage (in) is changed from the low level to the high level, the transistor M38 is turned on, the transistor M36 is turned off, and the transistor M37 is turned on until the level on the node 20 becomes the low level. Since the transistor M36 is connected to the gate of M38, when the gate voltage crosses the middle of the power supply voltage and the ground voltage, the transistors M36 and M38 are turned on together to cause a short-circuit current. Furthermore, if the levels on the nodes 20 and 30 are lowered from the high level to the low level, the inverter will be made when the gate voltage crosses the middle of the supply voltage and the ground voltage! Both N3 and the transistor are turned on, so there will also be a short circuit flow through inverters IN3 and IN4. Similarly, when the input voltage (IN) goes from the high level to the low level, there will also be a short circuit current through the transistor M33-M35 and the inverters IN3 and IN4.

Client's Docket Ν〇·:93Ν001 TT’s Docket No:0492-A40340-TW/Finak/Wu Zhengying/2005-12-14 1283514 Figure 2 shows a CM〇s snubber circuit 5〇〇 capable of reducing short-circuit current. When the wheel terminal 5〇1 changes from the low level to the south level, the level of the node 582 will remain at the high level, and the level of the node will be lowered to the low level, so that the crystal sister Conducted with the cockroaches until the node of the milk in the county is fresh, and the purpose is to check the short circuit. Su-, Yu-Yu 35 M5 is connected to the idle pole of _, and the transistors M5 and M6 will always be turned on, so when the level of the input terminal 501 changes, a short-circuit current will be generated. In other words, the buffer drive stage 350 shown in Fig. 1 and the drive stage 550 shown in Fig. 2 still have a short-circuit current. SUMMARY OF THE INVENTION In view of the above, it is a primary object of the present invention to provide a CMOS buffer circuit that reduces short-circuit current. According to the above object, the present invention provides a CM〇s buffer circuit including an output stage for driving-outputting, including a _first-conducting type _th output transistor and a second-conducting-second output a transistor; an output driving unit for generating a No. 4 to turn off the first output transistor according to the delay signal; and a bidirectional delay unit controlled by an input signal for the first output, the crystal cutoff After that, the second round of the output transistor is turned on, including a bidirectional logic 70' rib according to the input signal - the inverted signal m logic signal and a logic money, and the first and second bidirectional buffers, _ output a stage for generating a "second signal" to turn on the second output transistor according to the input u tiger and the first and second logic signals. The invention also provides an integrated circuit comprising at least two stages of the aforementioned CM〇s buffer circuit connected in series, and the output end of each stage of the CM0S buffer circuit is coupled to the output drive of the CM〇s buffer circuit of the next stage. unit. The invention also provides a ring oscillator circuit comprising first and second CM s s buffer circuits connected in series, wherein the output end of the first CMOS snubber circuit is secreted to the output drive of the second CM 〇 s buffer circuit And an inverter, comprising: an input terminal connected to the second CM〇s buffer circuit, and an output terminal coupled to the input terminal of the _CM〇s_ circuit. The above and other objects, features, and advantages of the present invention will become more apparent and understood. The embodiment is described in detail with reference to the accompanying drawings, and the third embodiment is a schematic diagram of a CMOS buffer circuit of the present invention. As shown, the CM〇s_buffer circuit 100 includes a wheel-in terminal 1 (n, an output stage 11A, a wheel-out drive unit H. a bidirectional delay unit 130, and a delay unit 140. The wheel-in terminal 101 is configured to receive An input signal S; [, the output stage 11 〇 includes a PM 〇 s body 翌 - and a 迴 03⁄4 for driving the output terminal 102. The PM0S transistor φ M13 includes a first terminal for the first voltage source, a first The second terminal is coupled to the input terminal and the control terminal is coupled to the output driving unit 120. The NM〇S transistor M12 includes a first end coupled to the output port 102'. The first end is coupled to the second voltage source GND and a control terminal. The output driving unit 120 is used to generate a first signal V1/V2 to turn off the MOS transistor M13/M12 according to a delay signal SD. The output driving unit 120 includes a pm 〇S transistor Mil . . . · · - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - a voltage source Vdd, a second end coupled to the control end of the PM0S transistor M13, and a control end coupled to the delay signal SD°NM0S transistor M5 The first end is coupled to the control terminal of the PM0S transistor M12, the second end is coupled to the second voltage source GND, and the control terminal is coupled to the delay signal SD. The bidirectional delay unit 130 is controlled by the input signal SI. For MOS transistors

Ml main charge is the main sergeant, 7 爹 power Jingxia M12/M13. The bidirectional delay unit 130 includes a ', _-to-logic unit 1310 and second and second bidirectional buffers 1320 and 1330. The bidirectional logic unit 1310 is configured to generate two logic signals (not shown in the figure) according to the inverted signal SV of the input signal SI. The bidirectional logic unit 1310 can be a bidirectional logic gate or a bidirectional logic chain containing a plurality of series connected bidirectional logic gates. The first ------ first, second bidirectional buffer 1320 ^: 1330 is coupled to the output drive unit 120, according to the input --------- a--...- ____-... ........... 一一—_______> The input signal SI and the aforementioned two logic signals generate a second signal V2/V1 for conducting the crystal

Client’s Docket No. :93N001 TT,s Docket No:0492-A40340-TW/Finak/Wu Zhengying/2005-12-14 1283514 M12/M13. For example, when the input signal changes from the high level to the low level, the output driving unit 120 generates the first signal VI to turn off the driving M13 according to the delay signal SD. The bidirectional delay unit 13 is configured to turn on the transistor M12 after the transistor M13 is turned off according to the input signal SI. Or, when the input signal changes from the low level to the high level, the output driving unit 12 uses ^ to generate the first signal V2 according to the delay signal SD to turn off the driving Μ12. The bidirectional delay unit 130 is configured to turn on the transistor Μ13 after the transistor Μ12 is turned off according to the input signal SI. Therefore, when the input signal SD changes from the low level to the high level or from the high level to the low level, the PM 〇s Lu crystal M13 and the NMOS transistor M12 are not turned on at the same time, thereby preventing the short circuit current from being generated. Figure 4A is an embodiment of the bidirectional logic gate of the present invention. As shown, bidirectional logic gate 1310A is used to generate two logic signals OT1 and OT2 based on control signal CS and two input signals ΓΓ1 and IT2, and includes two NMOS transistors M1 and M2 and PMOS transistors M3 and M4. The NMOS transistor M1 includes a first end face connected to the second voltage source 〇_, a control end coupled to the control signal CS and a second end, and the NMOS transistor M2 includes a first end coupled to the NMOS transistor At the second end of the M1, a control terminal is coupled to the input signal IT1, and a second terminal is coupled to the node N1. The PMOS transistor M3 includes a first terminal coupled to the node N1, a control terminal coupled to the input signal IT2, and a second terminal. The PMOS transistor M4 includes a first end coupled to the second end of the PMOS transistor M3, a control terminal coupled to the control signal cs, and a second terminal coupled to the first voltage source Vdd. When the control "CS is two levels", the transistors M1 and y[4 will be turned on and off respectively. If the input signal IT1 is at the high level, the voltage 1 on the node !^ will become low. Otherwise, the voltage VL will remain in a high impedance state (high_impedance; Hiz). Therefore, A is used to generate a voltage % having a low voltage level as the logic signals 〇τι and 〇τ2, and output to the first and second bidirectional buffers 1320. When the 1330〆 or ^low level is used, the transistors M1 and Μ4 will be turned off and on, respectively. If the turn signal ιτ2 is low, the client's Docket Ν〇·:93Ν001 TT's Docket N〇:0492-A40340-TW/Finak / Wu Zhengzhi/2005-12-14 8 1283514 'When the bit is set, the voltage VL on node N1 will become high level, otherwise the voltage VL will remain in high impedance state (high-impedance; Hiz). Therefore, bidirectional logic The unit 131A is used to generate the electromigration VL having a high voltage level as the logic signals 〇T1 and 〇T2, and output to the first and second bidirectional buffers 1320 and 1330. • The fourth diagram is the two-way of the present invention. Another embodiment of the logic gate. As shown in the figure, the two-way logic and the 13th excitation system are in the fourth diagram. The bidirectional logic gate 1310 is similar except that the nM〇S transistor Μ3Χ and the PMOS transistor M2XaNM〇S transistor Μ2 are coupled between the node N1 and the second end of the ship 3 transistor M1, and include a control terminal coupling. Connected to the input signal φ transistor M3X is between the node N1 and the second end of the PMOS transistor M4, and includes a control end face connected to the light input signal IT2. When the control 彳§03 is at a high level The transistors M1 and ]^# will be turned on and off respectively. If the input signal IT1 or IT2 is at a high level, the voltage I on the node N1 will become a low level, otherwise the power M VL will be secret. In this case, the bidirectional logic unit 1310B is used to generate a voltage % having a low voltage level as a logic signal 〇τι and OT2 'output to the first and second bidirectional buffers to measure 133 〇. When the control signal cs is at a low level, the transistors M1 and M4 are respectively turned off and on. If the input signal ιτι or IT2 is at a low level, the voltage % on the node N1 will become a high level, otherwise Voltage%

Will remain in a high-impedance (Hiz). Therefore, the bidirectional logic unit 1310A is configured to generate the electric dust VL having a high voltage level as the logic signals 〇T1 and 〇T2, and output to the first and second bidirectional buffers 1320 and 1330. First Embodiment A fifth embodiment is an embodiment of a bidirectional buffer circuit. As shown, the buffer circuit 1 includes an input terminal 10, an output stage u, an output driver unit 12, a bidirectional delay unit τ 103, and a delay circuit 14A. The output stage 11〇 and the output drive unit 12 are the output stage 10 of the buffer circuit 100 shown in FIG. 3, and the unit 1310 and the unit 1310 are shown in FIG. The bidirectional logic gate 1310A is similar.

Client's Docket N〇.:93N001 TT s Docket No:0492-A40340-TW/Finak/Wu Zhengying/2005-12-14 1283514 In the bidirectional logic unit 1310, the control terminal of the PM0S transistor M3 is coupled to the voltage V2' The control terminal of the NMOS transistor M2 is coupled to the voltage vi. The control terminals of the transistors M1 and M4 are coupled to the inverted signal sv from the delay circuit 140. The voltage % is coupled to the bidirectional logic buffers 1320 and 1330 as the first and second logic signals. The bidirectional buffer 1330 includes two PMOS transistors M6 and M7 connected between the first voltage source Vdd and the voltage V2, and the bidirectional buffer 132 includes two PMOSs connected between the second voltage source GND and the voltage VI. Transistors M9 and M10. The control terminals of the transistors M7 and M9 are connected to the input #SI, and the control terminals of the transistors VI6 and M10 are connected to the voltage vi. The delay circuit 140 includes inverters 51A and 52A connected in series, wherein the inverter 51' is used to generate the inverted signal SV of the input hash number SI, and the inverter 520 is used to generate the delayed signal SD. The following is a description of FIGS. 5A and 6 for explaining the operation of the buffer circuit 1A. As shown in Figure 6, at the beginning, the input signal SI will remain at the high level, the inverted signal sv will remain at the low level and the delayed signal SD will remain at the high level. Therefore, the electromigration vi and V2 will remain at the low level and the voltage VL will remain at the high level, so the voltage νουτ at the output terminal 1〇2 will remain at the south level. When the interval between % is tl, the rounding signal SI will become low level, and the transistors M7 and M9 will be turned on and off respectively. Since the voltage VL is still maintained at a high level, the transistor ¥6 is still off, so there is no short-circuit current passing through the transistors M5-M7 at this instant. At time t2, the inverted signal SV becomes a high level, and the transistors M1 and ... are turned on and off, respectively. Since the voltage V1 is still maintained at the low level, the transistor M2 is still turned off, so that no short-circuit current passes through the transistors M1-M4 at this moment. At time t3, the delay signal SD becomes a low level, and the transistors M5 and M11 are turned off and on, respectively. Since the transistor M9 has been turned off in accordance with the input signal 31, there is no short-circuit current passing through the transistors M9-M11 at this instant. At time t4, since the electro-ceramic M11 is turned on at time t3, the voltage % becomes a high level. Since the Lai V1 is at a high level, the transistor M13 is turned off. That is, the wheel drive must

Client's Docket No.: 93N001 TT’s Docket No: 0492-A40340-TW/Finak/Wu Zhengying/2005-12-14 1283514 The transistor M丨3 is turned off according to the delay signal SD generating voltage V1. At time t5, since the voltage % is at a high level, the transistor "2 will be turned on, and since the transistors M1 and M2 are both turned on, the voltage % will become a low level. That is, the bidirectional logic unit 1310A will be based on the input. The inverted signal sv of the signal SI generates a voltage % (logic signal). Since the transistor M2 has been turned off at time t2, there is no short-circuit current passing through the transistor M1 at this instant. At time t6, the voltage vl is At low level, the transistors M6 and M1〇 will be turned on and off respectively. Since the transistors 6 and 7 are turned on, the voltage V2 will become high, because the transistor M5 is off, so at this moment There will be no short-circuit current through the transistor grandmother. • At time t7, since the voltage V2 is at a high level, the transistor M12 will be versatile to drive the output terminal 102, so the power ν 〇υ τ on the output terminal 102 will become The low level, that is, the first and second bidirectional buffers 1320 and 1330 will conduct the voltage V12 according to the input signal illusion and the voltage % (first, second logic 唬) generating voltage V2. Therefore, the transistor Μ12 will The transistor Μ13 is turned off after being turned off. In other words. In the meantime, the dragon and the hall will not be turned on at the same time, so there will be no short _ flow through 1 off]\412 and]\413. - It can be seen that when the input money 81 changes from low level to high level, it is output. There is no short-circuit current generated in stage 110, output drive unit 12A and bidirectional delay unit 13A. Conversely, at time t8, input signal si will become high level, and transistors Μ7 and _ will be cut off respectively. And the conduction. Since the cage 4 is still at the low level, the crystal hall is still cut off, so there will be no short-circuit current passing through the transistor Μ9_Μη at this moment. In the dead t9, the inverted signal sv becomes low. The level, the transistor M1 and "々 will be cut off and on, respectively. Since the electric repeatedly V2 is still at the high level, the transistor is still cut off, so there is no short-circuit current passing through the transistor m1_M4 at this moment. At time t10, the delay signal SD becomes a high level, and the transistors M5 and Mn are turned on and off, respectively. Since the transistor M7 will be cut off according to the wheeling signal, there will be no short-circuit current through the transistor M5-M7 at this moment.

Client's Docket Νρ·:93Ν001 TT's Docket No:0492-A40340-TW/Finak/Wu Zhengying/2005-12-14 1283514 At time til 'g] is the transistor M5 is turned on at time cafe, so the voltage % " Low level. Since the dragon V2 is at a low level, the transistor M12 is turned off, and the wheel drive = will turn off the transistor M12 according to the delay signal SD generating voltage V2. When the time is like, since the voltage % is at a low level, the transistor M3 is turned on, and both the transistors MS and _ are turned on, and the voltage v1 becomes a high level. That is, the bidirectional logic unit 1310A generates an electrical sigma (logic signal) based on the inverted signal sv of the input signal Si. Since the transistor M1 is turned off, there is no short-circuit current passing through the transistor side at this moment. At time t13, since the voltage is a high level, the transistor full and Μι〇 will be off and on, respectively. Since the transistors M9 and M1〇 are both turned on, the voltage V1 will become a low level: Since the transistor Mil will be turned off, there will be no short-circuit current passing through the power M9-M11 at time t14 due to The voltage ¥1 is at a low level, and the transistor is generalized to drive the output terminal 102, so the voltage ν〇υτ on the output terminal 102 becomes a high level. That is, the first and second bidirectional buffers 1320 and 1330 generate a voltage VI based on the input signal SI and the voltage VL (first and second logic signals) to conduct the transistor 13. Therefore, the transistor 13 is turned on after the transistor Μ12 is turned off. In other words, the transistors Μ12 and Μ13 are not turned on at the same time, so that no short-circuit current flows through the transistors Μ12 and Μ13. It can be seen that when the input signal SI changes from the high level to the low level, no short-circuit current is generated in the input stage H0, the output driving unit 12A, and the bidirectional delay unit. Since no short-circuit current is generated in the output stage 110, the output driving unit 120, and the bidirectional delay unit 13A, the present invention can avoid the short-circuit current occurring in the output driving stages shown in the second and second figures, and thus Traditionally, the circuit can reduce electrical energy consumption and static interference. SECOND EMBODIMENT Figure 5B is another embodiment of a bidirectional buffer circuit. As shown in the figure, the snubber circuit 10QB is similar to the snubber circuit ιοοΑ in the figure 5A except that the double-life buffer 1330 is coupled to the control terminal of the transistor M13 instead of the first voltage. Source Vdd, and Client's Docket No: 93N001 TT's Docket No: 0492-A40340-TW/Finak/Wu Zhengying/2005-12-14 !283514 and the second end of the transistor M9 in the bidirectional buffer 1320 is coupled to The control terminal of the transistor M12, instead of the second voltage source GND. The operation of the buffer circuit 100B is similar to that of the buffer circuit 1A, and will not be described here. Since the first end of the transistor M7 in the bidirectional buffer 1330 is connected to the control terminal of the transistor M13 and the second end of the transistor in the bidirectional buffer 1320 is connected to the transistor. The control terminal of M12 can thus automatically prevent the gate voltage of the transistor M13 from exceeding the gate voltage of the transistor M12 or the gate voltage of the transistor M12 exceeding the gate voltage of the transistor M13. Third Embodiment Lu 5C is another embodiment of a bidirectional buffer circuit. As shown, the buffer circuit 1〇〇c is similar to the buffer circuit i〇OA in Figure 5A except that the bidirectional buffer, 131〇c includes three bidirectional logic gates connected in series instead of single-two-way logic. The operation of the gate and the snubber circuit 1〇〇c is similar to that of the snubber circuit 100A, and will not be described here. In the snubber circuit 1GGC, the delay _ is increased by the addition of Shuangsaki, because the short-circuit current is not generated in the bidirectional logic, so the total short-circuit current of the entire snubber circuit does not increase. Figure 7 shows an embodiment of a long delay circuit. Such as riding, long delay circuit (10) including two-stage cascade of thief roads and 1G (L2, its smashing circuit〗 (8) 丨 迁 迁 迁 系 系 系 働 働 働 , , , , , , , , , —_ Circuitry ^ 7Λ 100-2 is similar to that shown in Figure 5A. Therefore, the increase of the snubber circuit does not increase the current. ^ 嶋 嶋 is a ring-shaped circuit - an embodiment. The first and second buffer circuits 1() (the U and the second-2, the first buffering device are connected to the wheel drive unit of the second buffer circuit 100_2). Others; including one round of the end coupled to the second buffer circuit 1〇〇2 wheel ', the buffer circuit HXU's input end. -% and - round end secret to the first - belongs to the Qing Lai lion from the 姊 (4) -Caf will Cliffs Docket No.:93N001 '一^^, s Docket NO:0492-A40340-TW/Finak/吴政谚/2005-12-14 13 1283514 The current increases with the number of winter phase devices. In the ring-shaped vibration f path, since there is no short-circuit current generated in the output stage no, the wheel drive unit (4) and the bidirectional delay unit 0 in each stage, the short-circuit current does not occur. The present invention has been disclosed in the above preferred embodiments, and it is not intended to limit the present invention. Any of the π, 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 Fanmu #_如_怀面状者转. Figure 1 shows a traditional CMOS buffer circuit. _ S 2 ® shows the county CMQS buffer circuit. The third picture is the CM〇s of the present invention. A schematic diagram of one of the buffer circuits. Fig. 4A is an embodiment of the bidirectional logic gate of the present invention. Fig. 4B is another embodiment of the bidirectional logic gate of the present invention. Fig. 5A is one of the bidirectional buffer circuits. Embodiment 5B is another embodiment of a bidirectional buffer circuit. Fig. 5C is a further embodiment of a bidirectional buffer circuit. Fig. 6 is a timing control diagram of a buffer circuit in Fig. 5A. The figure shows an embodiment of a long delay circuit. ® Figure 8 is an example of a ring oscillator circuit. [Main component symbol description], 100, 100J, 100-2, 200, 500: CMOS slow Crush circuit; 100A, 100B, 100C: bidirectional buffer circuit; 101, 501: input terminal; 102: output terminal; 110: output stage; .120: output drive unit; 130: bidirectional delay unit;

Client's Docket No.: 93N001 TT, s Docket No: 0492-A40340-TW/Finak/Wu Zhengying/2005-12-14 14 1283514 Λ 140: delay unit; 300: ring oscillator circuit; 310: pre-driver stage; 520, 530, IN3, IN4: inverter; . 1310: bidirectional logic unit; 1320, 1330 · · bidirectional buffer; SI, ΓΓ 1, IT2 · · input signal;

Vdd: first voltage source; GND: second voltage source; ® SD ··delay signal; V Bu V2, VI', V2': signal; SV: inverted signal; CS: control signal; ΟΤΙ, OT2: logic signal ; Μ, 20, 30, 582, 594 ·· nodes; VL, VL, VOUT, VOUT,: voltage; IN: input voltage; • Ml ~ M7, M9 ~ M13, M2X, M3X, Ml A ~ M4A, M1B ~M4B, M1 C to M4C, M33-M38, M101 to M107, M109 to Ml 13, M201 to M207, M209 to M213: MOS transistor.

Client 5s Docket N〇.:93N001 TT’s Docket No:0492-A40340-TW/Finak/吴政谚/2005-12-14

Claims (1)

1283514 X. Patent application scope: 1. A CMOS buffer circuit comprising: an input terminal for receiving an input signal; - an output stage for driving-outputting, including - a first conductivity type - a first output current a second output transistor of the crystal body and a second conductivity type; - an output driving unit for generating a -first signal according to the -delay signal to turn off the first output transistor; and - a bidirectional delay unit, The second output transistor is turned on, and the bidirectional logic unit 70 is used to turn on the money according to the signal of the miscellaneous person after the _th output _ crystal is turned off. Generating a first logic signal and a second logic signal; and the +- and second bidirectional buffers H, coupled to the output stage, and recording the input signal and the first and second logic signals to generate a _ The two signals are used to turn on the second output transistor. 2. If the (10) (7) buffer circuit described in item 1 of the special plane n is applied, the delay circuit is further configured to generate the delayed signal and the signal according to the input signal. 3. The CMOS snubber circuit of claim 2, wherein the delay circuit comprises: an electric 'first inverter, comprising an input coupled to the input signal and the inverted signal; and The output terminal is coupled to the second inversion H., including the input terminal, the first wheel of the first inverter, and an output terminal for outputting the delay signal. Driving 4: The 2CM 〇 冲 circuit according to item 2 of the patent application, wherein the upper lash unit includes ·· ', % output - has the above-mentioned first-conducting type m body, including _th-end_source, - control end The above delay signal, and a second end to turn out the above pressure 4, · Client's Docket N〇.:93N001 IT's Docket N〇:0492-A40340-TW/Finak/吴政谚/2005-12_14 16 1283514 and source a second transistor having the above second conductivity type, comprising a pull-control terminal, said extension _m ^: a second voltage buffer circuit, wherein said first bidirectional 5. CMQS 'phase as recited in claim _4 - nickname. The buffer includes: a third transistor number of the input type of the seventy-sixth counter-lean conductivity type, and a first end; and a fourth transistor having the second conductivity type, including The first-end control terminal of the _th-end crystal is reduced to "the first-signal; Μ and - the second-end _upper and the above-mentioned two-way bidirectional buffer includes: 'including a control terminal coupled to the input signal- a fifth transistor number of the first conductivity type, and a first end; and - a sixth transistor having the above-mentioned first conductivity type, including a _th-end difficult to be the fifth-electrode-end'-second The terminal is configured to output the second signal, and the control terminal secretizes the first logic signal. The CMOS buffer circuit of claim 5, wherein the third electrical body further includes a second end coupled to the second voltage source, and the fifth transistor further includes a second end The first voltage source is coupled to the first voltage source. The CMOS snubber circuit of claim 5, wherein the third transistor further comprises a second end coupled to one of the control ends of the second output transistor, and the fifth electrode body is further The second end is connected to one of the control ends of the first output transistor. 8. The CMOS buffer circuit of claim 4, wherein the bidirectional logic unit comprises at least one bidirectional logic gate. 9. The CMQSw buffer circuit of claim 4, wherein the biphasic logic unit comprises a bidirectional logic gate connected by a plurality of strings. Client's Docket Ν〇·:93Ν001 TT s Docket No:0492-A40340-TW/Finak/吴政谚/2005-12-14 17 • 1283514 LOCK = CM0S snubber circuit as described in claim 8 of the patent application, wherein a two-way logic-having a seventh transistor having the above-mentioned first conductivity type, comprising: a first flipping said first electrical first control terminal coupled to said inverted signal, and a second end; 曰~ having said first conductivity type a first human transistor, including a first end - the seventh electrical signal first end - the second end of the control end domain, and - the second end touches the logic signal; the short dead r has the second conductivity type The ninth transistor includes - the first end - the second logic described above.控制 a control terminal coupled to the first signal and a second terminal; and 曰-the tenth transistor having the second conductivity type, including a first end lightly connected to the second end of the ninth transistor - the control terminal inputs the inverted signal, and - the second terminal - the second 11. The CM 〇 S snubber circuit logic gate as described in claim 1 further includes: The eleventh transistor includes a second end of a seventh transistor, a control end coupled to the first signal, and a second end of the eighth transistor; The bidirectional end is coupled to the first end of the first leg, and the first end is connected to the first end. The second end is coupled to the first twelfth transistor having the second conductivity type, including a first transistor. The second end, a control end is coupled to the second signal, and the first end of the ten-electrode. 12· an integrated circuit comprising at least two stages, such as the CMOS buffer circuit described in claim 1 of the patent scope, connected in series, wherein each of the above-mentioned CMOS buffers is defeated by Xishan: the output end of the circuit is coupled to the lower The output driver unit of the CMOS snubber circuit of the first stage. A ring-shaped oscillating circuit, comprising: the first and the second CMOS snubber circuit according to claim 1, connected in series, wherein the first CMOS snubber circuit is coupled to the wheel end To the above second cm 〇 ^ ^ ^ Glienfs Docket N〇.: 93N001 TT's Docket No: 0492-A40340-TW/Finak / Wu Zhengyu / 2005-12-14 18 1283514 circuit output drive unit; and an inverter, including An input end is coupled to the output end of the second CMOS buffer circuit, and an output end is coupled to the input end of the first CMOS buffer circuit. Client’s Docket Ν〇·:93Ν001 TT’s Docket No:0492-A40340-TW/Finak/吴政谚/2005-12-14