1263048 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種訊號產生器及其移位暫存器（Shift Register)，且特別是有關於一種使用單一 p型金氧半（p_type1263048 IX. Description of the Invention: [Technical Field] The present invention relates to a signal generator and a shift register thereof, and in particular to a single p-type gold-oxygen half (p_type)
Metal Oxide Semiconductor’PMOS)電晶體或 N 型金氧半（NMOS) 電晶體之訊號產生器及其移位暫存器。 【先前技術】 傳統應用低溫多晶矽（Low Temperature Poly Silicon，LTPS) 技術實現於玻璃基板之移位暫存器係為互補式移位暫存器，其 電路中往往包含了 N型薄膜電晶體（Thin Film Transistor，TFT) 以及P型薄膜電晶體。 第1A圖是習知多級互補式移位暫存器之電路結構圖。請 參照第1A圖，第一級移位暫存器100具有二顆PMOS電晶體 MP1及MP2以及二顆NMOS電晶體MN1及MN2。電晶體MP2 之閘極與電晶體MN2之閘極耦接，並接收輸入訊號input。電 晶體MP2之源極與電晶體MN2之汲極耦接，並輸出第一訊號 S1。第一訊號S1經由第一反相器102後輸出第一輸出訊號 out-Ι。電晶體MP1之閘極接收時脈訊號XCK，且電晶體MN1 之閘極則接收時脈訊號CK。時脈訊號CK與XCK係為反相訊 號。另外，電晶體MP1之源極耦接電晶體MP2之汲極，且電 晶體MN1之汲極耦接電晶體MN2之源極。 同樣地，第二級移位暫存器11〇包括PMOS電晶體MP3 及MP4以及NMOS電晶體MN3及MN4。電晶體MP4之閘極 與電晶體MN4之閘極耦接，並接收第一訊號S1。電晶體MP4 之源極與電晶體MN4之汲極耦接，並輸出第二訊號S2。第二 1263048 訊號S2經由第二反相器112後輸出第二輸出訊號〇ut_2。電晶 體MP3之閘極接收時脈訊號CK，且電晶體MN1之閘極則接收 4脈讯號XCK。另外，電晶體MP3之源極耦接電晶體MP4之 汲極，且電晶體MN3之汲極耦接電晶體MN4源極。 第1B圖係繪示第ία圖中移位暫存器1〇〇及11〇之輸入訊 號input、輸出訊號out-l及out_2之時序圖。如第a圖所示， 輸出訊號out-2相位係輸出訊號outq之相位向右平移半個周期 T/2。由於互補式移位暫存器100及11〇包含了 ntft以及 P-TFT製程所需之光罩成本較高，不符合ltps技術上降低成本 之目標。而且相位平移後之輸出訊號〇u1> 1、〇ut_2將產生半個 周期之重疊部份，若應用於實際面板之驅動訊號，必須利用及 (AND)閘邏輯電路來加以分開。因此更增加移位暫存器之製作 成本。 【發明内容】 有鑑於此，本發明的目的就是在提供一種訊號產生器及其 移位暫存器，利用單一 PM0S電晶體或NMOS電晶體來製作開 關元件，可減少整個系統製程所使用之光罩數目，有效降低製 造成本，並可提高面板產出率（throughput)。 根據本發明的目的，提出一種移位暫存器，用以接收一輸 入訊號並據以輸出一輸出訊號。移位暫存器包括第一開關元 件、第二開關元件、升降壓元件以及電壓重置元件。第一開關 元件包括第一輸入端、第一控制端以及第一輸出端。第一輸入 端用以接收輸入訊號。第一控制端用以接收第一時脈訊號。第 二開關元件耦接第一開關元件。第二開關元件包括第二輸入 端、第二控制端以及第二輸出端。第二輸入端接收第二時脈訊 1263048 號。第二控制端麵接第一輸出端。第二輸出端用 號。升降壓（Step-up/step_d0wn)元件耗接第二控制端=说 端。電壓重置元件搞接第二開關元件。電a重置元件包 控制端以及第二輸出端。第三控制端用以接收重置訊號。 輸出端連接第二輸出端。 於第一時序周期中，輸入訊號為第一輸入準位，第一時脈 訊號為第-時脈準位且第二時脈訊號為第二時脈準位，第一開 關元件導通，且輸入訊號使第二開關元件導通，而重置訊號^ 控制電壓重置元件不導通，輸出訊號為第一輸出準位；於第二 時序周期中，輸人訊號為第二輸人準位，第—時脈訊號為第二 時脈準位且第二時脈訊號為第一時脈準位，第一開關元件不導 通’而升降Μ元件使第二開關元件導通，且重置訊號係控制電 壓重置元件不導通，輸出訊號為第二輸出準位；於第三時序周 期中，輸入訊號為第二輸入準位，第一時脈訊號為第一時脈準 位且第二時脈訊號為第二時脈準位，第一開關元件導通，輸入 訊號控制第一開關元件不導通，而重置訊號控制電壓重置元件 導通，使輸出訊號為第一輸出準位。 根據本發明的目的，提出一種訊號產生器，包括多個移位 暫存器，各用以接收一輸入訊號並據以輸出一輸出訊號。各移 位暫存器包括第一開關元件、第二開關元件、升降壓元件以及 電壓重置元件。第一開關元件包括第一輸入端、第一控制端以 及第一輸出端。第一輸入端用以接收前級移位暫存器之輸出訊 號。第一控制端用以接收第一時脈訊號。第二開關元件包括第 二輸入端、第二控制端以及第二輸出端。第二控制端耦接第一 輸出端。第二輸入端用以接收第二時脈訊號。第二輸出端用以 輸出此級移位暫存器之輸出訊號。升降壓元件耦接第二控制端 1263048 及第二輸入端。電壓重置元件耦接第二輸出端。電壓重置元件 包括第二控制端及第三輸出端。第三控制端接收重置訊號，且 第二輸出端搞接第二輸出端。 於第一時序周期中，此級移位暫存器中輸入訊號為第一輸 入準位，第一時脈訊號為第一時脈準位且第二時脈訊號為第二 牯脈準位，第一開關元件導通，且輸入訊號使第二開關元件導 通，而重置訊號係控制電壓重置元件不導通，輸出訊號為第一 輸出準位；於第二時序周期中，輸入訊號為第二輸入準位，第 一時脈訊號為第二時脈準位且第二時脈訊號為第一準位，第一 開關元件不導通，而升降壓元件使第二開關元件導通，且重置 訊號係控制電壓重置元件不導通，輸出訊號為第二輸出準位； 於第三時序周期中，輸入訊號為第二輸入準位，第一時脈訊號 為第一時脈準位且第二時脈訊號為第二時脈準位，第一開關元 件導通，輸入訊號控制第二開關元件不導通，而重置訊號控制 電壓重置元件導通，使輸出訊號為第一輸出準位。 為讓本發明之上述目的、特徵、和優點能更明顯易懂，下 文特舉兩較佳實施例，並配合所附圖式，作詳細說明如下： 【實施方式】 接下來，就以兩較佳實施例來說明本發明如何使用單一型 態之PMOS電晶體來製作訊號產生器及其移位暫存器。 第一實施例： 請參照第2圖’其緣示依照本發明第一實施例的一種訊號 產生益結構方塊圖。訊5虎產生2 0 0，例如是應用於平面顯示 器之掃描驅動器或資料驅動器，其包括相互串接之多級移位暫 存器210。第2圖僅顯示串接之第N級、第（N+1)級以及第（N+2) 1263048 級移位暫存器210。 第N級移位暫存器210包括第一 PMOS電晶體MPln、第 二PMOS電晶體MP2n、電容元件Cn以及第η電壓重置（Reset) 元件212。電晶體MPln之汲極係接收輸入訊號INPUT，亦即 第（N-1)級移位暫存器210(未顯示於圖中）之輸出訊號 OUI^N-l，且電晶體MPln之閘極接收時脈訊號XCK。電晶體 MP2n之閘極耦接電晶體MPln之源極，且電容元件Cn係跨接 於電晶體MP2n之源極以及閘極之間。電容元件Cn可以是一外 加電容，或者是電晶體MP2n閘源極之寄生電容。電晶體MP2n 之汲極則用以輸出訊號OUT_N，且電晶體MP2n之源極接收時 脈訊號CK。時脈訊號CK與XCK為反相訊號。 第N級移位暫存器210之電壓重置元件212包括第三 PMOS電晶體MP3n、第四PMOS電晶體ΜΡ4η以及第五PMOS 電晶體MP5n。電晶體ΜΡ3π之没極連接電晶體MP2n之没極， 且電晶體MP3n之閘極連接電晶體MP4n與電晶體MP5n之汲 極，電晶體MP3n之源極連接VDD。電晶體MP4n之閘極連接電 晶體MP3n之汲極，電晶體MP4n之源極連接VDD。電晶體MP5n 之汲極連接電晶體MP4n之汲極，電晶體MP5n之源極連接 GND。另外，電晶體MP5n之閘極則接收第（N+1)級移位暫存器 210之輸出訊號OUT_N+l作為一種重置訊號。 同樣地，第（N+1)級移位暫存器210包括第一 PMOS電晶 體 ΜΡ1(η+1)、第二 PMOS 電晶體 MP2(n+l)、電容元件 C(n+1) 以及第（n+1)電壓重置（Reset)元件212。電晶體ΜΡ1(η+1)之汲極 接收輸出訊號OUT—N，且電晶體ΜΡ1(η+1)之閘極接收時脈訊 號CK。電晶體MP2(n+l)之閘極耦接電晶體ΜΡ1(η+1)之源極， 且電容元件C(n+1)係跨接於電晶體MP2(n+l)之源極以及閘極 1263048 之間。電容元件C(n+1)例如是電晶體MP2(n+l)之寄生電容。電 晶體MP2(n+l)之汲極則用以輸出訊號OUTJM+1，且電晶體 MP2(n+l)之源極接收時脈訊號XCK。值得注意的是，訊號產生 器200中相鄰兩級移位暫存器210之兩第一 PMOS電晶體閘極 係接收反相之時脈訊號。 另外，第（n+1)電壓重置元件212包括第三PMOS電晶體 MP3(n+l)、第四PMOS電晶體MP4(n+l)以及第五PMOS電晶 體MP5(n+l)。各電晶體之連接關係與第η電壓重置元件212相 同，在此便不贅述。電晶體ΜΡ5(η+1)之閘極係接收第（Ν+2)級 移位暫存器210之輸出訊號〇UT_N+2作為一種重置訊號。 請參照第3圖，其繪示第2圖中第N級以及第（N+1)級移 位暫存器210之操作時序圖。於第一時序周期T1中，輸入訊號 INPUT為第一輸入準位（VIL)，例如是GND電位，時脈訊號XCK 為第一時脈準位（VCL)，例如是GND電位，且時脈訊號CK為第 二時脈準位（VCH)，例如是Vdd電位。於是電晶體MPln為導 通狀態。電位vx被拉至一相對低準位（VlL +Vth)，其中電壓Vth 為電晶體MPln之起始電壓（Threshold Voltage)。此時，電晶體 MP2n之閘極電位（VIL +Vth)低於源極電位VCH。因此，電晶體 MP2n亦導通，且訊號〇UT_N為一理想高準位VCH，並回饋至 第N級之電壓重置元件212中電晶體MP4n之閘極，使電晶體 MP4n不導通。 由於此時輸出訊號〇UT_N+l為高準位VCH。所以電晶體 MP5n不導通。此時電壓VY的準位為前一周期狀態，但不論vY 準位為何均不會影響訊號〇UT_N的輸出結果。亦即於第一周 期T1時，訊號OUT—N係輸出高準位VCH。 接著’於第二周期T2中，輸入訊號INPUT為第二輸入準 1263048 位（νΙΗ)。時脈訊號CK為第二時脈準位（VCH)，且時脈訊號XCK 為第一時脈準位（VCL)。由於電晶體MPln之閘極電位VIH高於 源極電位VCL，故電晶體MPln不導通。電晶體MP2n之源極電 位由VCH降為VCL。因此，節點Vx之電位會因降壓電容Cn 的作用而被降壓至準位（(VIL+VthHVCH-VCL))準位，此準位仍小 於MP2n之源極電位VCL，利用此降壓技術，可以解決習知移 位暫存器之PMOS電路無法創造一理想低準位之缺點。此時電 晶體MP2n仍為導通狀態，且訊號OUT_N係為一理想低準位 VCL，並回饋至電晶體MP4n之閘極，使電晶體MP4n為導通狀 態，此時節點VY電壓為VDD。由於電晶體MP3n之閘極電位 VDD等於源極電壓VDD，因此電晶體MP3n不導通。 此時，訊號OUT_N以低準位VCL輸入第（N+1)級移位暫存 器210中電晶體ΜΡ1(η+1)之汲極，且時脈訊號CK為低準位 VCL，此時第（N+1)級移位暫存器210各元件動作如同第一周期 T1之第N級移位暫存器210，電晶體ΜΡ1(η+1)及MP2(n+l)皆 導通，使輸出訊號OUT—N+1為高準位VCH。訊號OUT—N+1回 饋至第N電壓重置元件212中電晶體MP5n之閘極，使得電晶 體MP5n不導通。 於第三時序周期T3中，輸入訊號INPUT持續為高準位 VIH。時脈訊號CK為高準位VCH，且時脈訊號XCK為低準位 VCL。此時，第N級移位暫存器210之電晶體MPln為導通狀態， 使得節點Vx電位為高準位VIH，因此電晶體MP2n不導通。於 第（N+1)級移位暫存器210中，如同第二周期T2之第N級移位 暫存器210,電容元件C(n+1)降壓作用，使得電晶體ΜΡ2(η+1) 導通，且訊號OUT_N+l輸出訊號XCK之低準位VCL。訊號 OUT—N+1回饋至第N級之電壓重置元件212中電晶體MP5n之 1263048 閘極，使電晶體MP5n為導通狀態。此時，節點VY之電壓為一 相對低準位（GND+Vth)，使電晶體ΜΡ3η導通。因此，訊號 OUT—Ν輸出一理想高準位（=VCH)，並回饋至電晶體ΜΡ4η之閘 極，使得電晶體ΜΡ4η為不導通狀態。 如第3圖所示，第Ν級移位暫存器210之輸出訊號OUT_N 相位係相對於輸入訊號INPUT相位向右平移了半個周期T/2， 且第（N+1)級移位暫存器210之輸出訊號OUT_N+l相位係相對 於輸出訊號〇UT_N相位向右平移了半個周期T/2，因此並沒有 習知訊號重疊部份，因而節省了使用AND閘邏輯電路之成本。 第二實施例： 請參照第4圖，其繪示依照本發明第二實施例的一種訊號 產生器結構方塊圖。訊號產生器400,例如是應用於平面顯示 器之掃描驅動器或資料驅動器，其包括相互串接之多級移位暫 存器410。第4圖僅顯示串接之第N級、第（N+1)級以及第（N+2) 級移位暫存器410。 第N級移位暫存器410包括第一 PMOS電晶體MPln、第 二PMOS電晶體MP2n、電容元件Cn以及第N級之電壓重置元 件412。電晶體MP In之汲極係接收輸入訊號INPUT，且電晶 體MPln之閘極接收時脈訊號XCK。電晶體MPln、MP2n以及 電容元件Cn之連接關係與第一實施例之第N級移位暫存器210 相同，在此不贅述。電晶體MP2n之汲極係輸出訊號OUT_N， 且電晶體MP2n之源極接收時脈訊號CK。 另外，第N級之電壓重置元件412包括第三PMOS電晶體 MP3n、第四PMOS電晶體MP4n以及第五PMOS電晶體MP5n。 電晶體MP3n、MP4n以及MP5n之連接關係亦與第一實施例之 13 1263048 第N級之電壓重置元件212相同，在此亦不再多述。然而，第 二實施例中電晶體ΜΡ5η之閘極係接收時脈訊號XCK作為一種 重置訊號。 同樣地，第（Ν+1)級移位暫存器410包括第一 PMOS電晶 體 ΜΡ1(η+1)、第二 PMOS 電晶體 ΜΡ2(η+1)、電容元件 C(n+1) 以及第（n+1)電壓重置元件412。電晶體ΜΡ1(η+1)之汲極接收輸 出訊號OUT_N，且電晶體]\4?1(11+1)之閘極接收時脈訊號€{：。 電晶體MP2(n+l)之源極接收時脈訊號XCK。電晶體ΜΡ1(η+1) 與MP2(n+l)之連接關、係亦同第一實施例之第（N+1)級移位暫存 器210。而且訊號產生器400中相鄰兩級移位暫存器410之兩 第一 PMOS電晶體閘極係接收反相之時脈訊號。 另外，第（N+1)級之電壓重置元件412包括第三PMOS電 晶體MP3(n+l)、第四PMOS電晶體MP4(n+l)以及第五PMOS 電晶體MP5(n+l)。各電晶體之連接關係與第一實施例中第N級 之電壓重置元件212相同，在此便不贅述。電晶體MP5(n+1) 之閘極係接收時脈訊號CK作為一種重置訊號。 請參照第5圖，其繪示第4圖中第N級以及第（N+1)級移 位暫存器410之操作時序圖。如同第一實施例，於第一時序周 期T1中，輸入訊號INPUT為第一輸入準位VIL，時脈訊號XCK 為第一時脈準位VCL，且時脈訊號CK為第二時脈準位vch°電 晶體MPln為導通狀態。Vx電位被拉至一相對低準位 (VIL+Vth)。此時，電晶體MP2n亦導通，且訊號OUT一N輸出 一理想高準位VCH，並回饋至第N級之電壓重置元件412中電 晶體ΝΠΜη之閘極，使電晶體MP4n不導通。 由於輸入電晶體MP5n閘極之時脈訊號XCK為低準位 VCL，因此電晶體MP5n導通，使Vy電位為一相對低準位 14 1263048 (GND+Vth)，並輸出至電晶體MP3n之閘極，使電晶體MP3n 導通，且訊號OUT_N輸出高準位（VDD)。 接著，於第二周期T2中，輸入訊號INPUT為第二輸入準 位VIH。時脈訊號CK為第一時脈準位VCL，且時脈訊號XCK 為第二時脈準位VCH。電晶體MPln為不導通狀態。電晶體MP2n 之源極電位由VCH降為VCL。因此，Vx電位會因降壓電容Cn 的作用而被降壓（step-down)至準位（(VIL+Vth)-(VCH-VCL))，此準 位仍小於MP2n之源極電位VCL，利用此降壓技術，可以解決 習知移位暫存器之PMOS電路無法創造一理想低準位之缺點。 所以電晶體MP2n仍為導通狀態，且訊號OUT_N係輸出一理想 低準位VCL，並回饋至電晶體MP4n之閘極，使電晶體MP4n 為導通狀態，且節點VY電壓為VDD(高準位）。由於電晶體MP3n 之閘極電位（=VY電壓=VDD)等於源極電壓VDD，因此電晶體 MP3n不導通。由於電晶體MP5n閘極電位（=XCK=VCH)，因此 電晶體MP5n不導通。 此時，低準位之訊號〇UT_N輸入第（N+1)級移位暫存器410 中電晶體]\4?1(11+1)之汲極，且時脈訊號CK為低準位VCL，如 同第一周期T1之第N級移位暫存器410，電晶體ΜΡ1(η+1)及 MP2(n+l)皆導通，使輸出訊號OUT_N+l為高準位VCH。 於第三時序周期T3中，輸入訊號INPUT持續為第二輸入 準位VIH。時脈訊號CK為高準位VCH，且時脈訊號XCK為低 準位VCL。此時，電晶體MPln為導通狀態，使得Vx電位為高 準位VIH，因此電晶體MP2n不導通。於第（N+1)級移位暫存器 410中，如同第二周期T2之第N級移位暫存器410,電容元件 C(n+1)降壓作用，使得電晶體MP2(n+l)導通，且訊號OUT_N+l 輸出訊號XCK之低準位VCL。此時電晶體MP5n閘極電位等於 15 1263048 XCK為一低準位VCL，因此電晶體MP5n為導通狀態，且VY 電位為一相對低準位（GND+Vth)，並輸出至電晶體ΜΡ3η之閘 極，使電晶體ΜΡ3η導通。因此，訊號OUT_N輸出一理想高準 位（VDD)，並回饋至電晶體MP4n之閘極，使得電晶體MP4n為 不導通狀態。 如第5圖所示，第N級移位暫存器410之輸出訊號OUT_N 相位係相對於輸入訊號INPUT相位向右平移了半個周期T/2， 且第（N+1)級移位暫存器410之輸出訊號OUT_N+l相位係相對 於輸出訊號〇UT_N相位向右平移了半個周期172，因此並沒有 習知訊號重疊部份，因而節省了使用AND閘邏輯電路之成本。 如上所述，本發明雖以移位暫存器具有第一 PMOS電晶體 以及第二PMOS電晶體，且電壓重置元件具有第三PMOS電晶 體、第四PMOS電晶體以及第五PMOS電晶體為例作說明，然 本發明之移位暫存器亦可以是使用單一型態之NMOS電晶體， 或甚至其它之第一開關元件以及第二開關元件分別由第一時脈 訊號以及第二時脈訊號來控制，且電壓重置元件亦可以是僅使 用第三PMOS電晶體或第三開關元件，或甚至是其它電路，可 由重置訊號來控制其開或關，以提供所需之輸出訊號。只要在 第一時序周期，第一開關元件及第二開關元件導通而電壓重置 元件不導通，於第二時序周期，第一開關元件不導通，第二開 關元件導通且電壓重置元件不導通，並於第三時序周期，第一 開關元件導通，第二開關元件不導通，且電壓重置元件導通並 輸出所需之準位訊號，俾達到訊號相位平移之目的者，皆不脫 離本發明之技術範圍。 此外，移位暫存器之電容元件也可以其它之升降壓元件耦 接於第二PMOS電晶體之閘極，只要能於第二時序周期中達到 16 1263048 將第二PMOS電晶體閘極電位下拉之效果，亦不脫離本發明之 技術範圍。 本發明上述兩實施例所揭露之訊號產生器及其移位暫存 器之優點在於可利用LTPS PMOS或NMOS製程技術將移位暫 存器電路實現於玻璃基板上。由於單一 PMOS或單一 NMOS製 程所使用之光罩數較CMOS少，除了可以節省光罩成本，另可 以提高單位時間面板產生率（Throughput)。 綜上所述，雖然本發明已以兩較佳實施例揭露如上，然其 並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之 精神和範圍内，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 17 1263048 【圖式簡單說明】 第1A圖是習知多級互補式移位暫存器之電路結構圖。 第1B圖係繪示第1A圖中移位暫存器及之輸入訊號 input、輸出訊號out_ 1及out_2之時序圖。 第2圖繪示依照本發明第一實施例的一種訊號產生器結構 方塊圖。 第3圖繪示第2圖中第n級以及第（N+1)級移位暫存器之 操作時序圖。 第4圖緣示依照本發明第二實施例的一種訊號產生器結構 方塊圖。 第5圖繪示第4圖中第N級以及第（N+1)級移位暫存器之 操作時序圖。 【主要元件符號說明】 100、210、410:移位暫存器 102、112 :反相器 、 200、400 :訊號產生器 212、412 :電壓重置元件 13Metal Oxide Semiconductor's PMOS transistor or N-type MOS transistor signal generator and its shift register. [Prior Art] The conventional application of low temperature polysilicon (LTPS) technology to the glass substrate shift register is a complementary shift register, and the circuit often includes an N-type thin film transistor (Thin Film Transistor, TFT) and P-type thin film transistors. Figure 1A is a circuit diagram of a conventional multi-stage complementary shift register. Referring to FIG. 1A, the first stage shift register 100 has two PMOS transistors MP1 and MP2 and two NMOS transistors MN1 and MN2. The gate of the transistor MP2 is coupled to the gate of the transistor MN2 and receives the input signal input. The source of the transistor MP2 is coupled to the drain of the transistor MN2 and outputs a first signal S1. The first signal S1 outputs the first output signal out-Ι via the first inverter 102. The gate of the transistor MP1 receives the clock signal XCK, and the gate of the transistor MN1 receives the clock signal CK. The clock signals CK and XCK are inverted signals. In addition, the source of the transistor MP1 is coupled to the drain of the transistor MP2, and the drain of the transistor MN1 is coupled to the source of the transistor MN2. Similarly, the second stage shift register 11A includes PMOS transistors MP3 and MP4 and NMOS transistors MN3 and MN4. The gate of the transistor MP4 is coupled to the gate of the transistor MN4 and receives the first signal S1. The source of the transistor MP4 is coupled to the drain of the transistor MN4 and outputs a second signal S2. The second 1263048 signal S2 outputs the second output signal 〇ut_2 via the second inverter 112. The gate of the transistor MP3 receives the clock signal CK, and the gate of the transistor MN1 receives the 4-pulse signal XCK. In addition, the source of the transistor MP3 is coupled to the drain of the transistor MP4, and the drain of the transistor MN3 is coupled to the source of the transistor MN4. Fig. 1B is a timing chart showing the input signal input, output signals out-l and out_2 of the shift registers 1 and 11 in the Fig. As shown in Figure a, the phase of the output signal out-2 phase output signal outq is shifted to the right by a half cycle T/2. Since the complementary shift registers 100 and 11〇 contain ntft and the cost of the mask required for the P-TFT process is high, it does not meet the goal of lowering the cost of the ltps technology. Moreover, the phase-shifted output signals 〇u1> 1, 〇ut_2 will produce a half-cycle overlap. If applied to the actual panel drive signal, it must be separated by an AND gate logic circuit. Therefore, the manufacturing cost of the shift register is further increased. SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide a signal generator and a shift register thereof, which use a single PMOS transistor or an NMOS transistor to fabricate a switching element, thereby reducing the light used in the entire system process. The number of hoods effectively reduces manufacturing costs and increases panel throughput. In accordance with the purpose of the present invention, a shift register is provided for receiving an input signal and outputting an output signal accordingly. The shift register includes a first switching element, a second switching element, a buck-boost element, and a voltage reset element. The first switching element includes a first input, a first control, and a first output. The first input is for receiving an input signal. The first control terminal is configured to receive the first clock signal. The second switching element is coupled to the first switching element. The second switching element includes a second input terminal, a second control terminal, and a second output terminal. The second input receives the second time signal 1263048. The second control end is connected to the first output end. The second output is numbered. The step-up/step_d0wn component consumes the second control terminal = the terminal. The voltage reset component engages the second switching component. The electric a resets the component package control terminal and the second output terminal. The third control terminal is configured to receive a reset signal. The output is connected to the second output. In the first timing period, the input signal is the first input level, the first clock signal is the first-clock pulse level, and the second clock signal is the second clock level, the first switching element is turned on, and The input signal causes the second switching element to be turned on, and the reset signal ^ control voltage resetting component is not turned on, and the output signal is the first output level; in the second timing period, the input signal is the second input level, - the clock signal is the second clock level and the second clock signal is the first clock level, the first switching element is not conducting 'the lifting element is turned on, and the second switching element is turned on, and the signal control voltage is reset The reset component is not turned on, and the output signal is the second output level. In the third timing period, the input signal is the second input level, the first clock signal is the first clock level and the second clock signal is The second clock element is turned on, the first switching element is turned on, the input signal controls the first switching element to be non-conducting, and the reset signal control voltage resetting element is turned on, so that the output signal is at the first output level. According to an object of the present invention, a signal generator is provided, comprising a plurality of shift registers, each for receiving an input signal and outputting an output signal accordingly. Each of the shift registers includes a first switching element, a second switching element, a buck-boost element, and a voltage reset element. The first switching element includes a first input, a first control, and a first output. The first input is configured to receive an output signal of the pre-stage shift register. The first control terminal is configured to receive the first clock signal. The second switching element includes a second input, a second control, and a second output. The second control end is coupled to the first output end. The second input is configured to receive the second clock signal. The second output is used to output the output signal of the shift register of the stage. The bucking and lowering element is coupled to the second control end 1263048 and the second input end. The voltage reset component is coupled to the second output. The voltage reset component includes a second control terminal and a third output terminal. The third control terminal receives the reset signal, and the second output terminal is coupled to the second output terminal. In the first timing cycle, the input signal in the shift register is the first input level, the first clock signal is the first clock level and the second clock signal is the second pulse level. The first switching element is turned on, and the input signal turns on the second switching element, and the reset signal is controlled to be non-conducting, and the output signal is the first output level; in the second timing period, the input signal is Two input levels, the first clock signal is the second clock level and the second clock signal is the first level, the first switching element is non-conducting, and the buck-boost element turns the second switching element on and resets The signal control device is not turned on, and the output signal is the second output level. In the third timing period, the input signal is the second input level, the first clock signal is the first clock level and the second The clock signal is the second clock position, the first switching element is turned on, the input signal controls the second switching element to be non-conducting, and the reset signal control voltage resetting element is turned on, so that the output signal is the first output level. The above described objects, features, and advantages of the present invention will become more apparent and understood. The preferred embodiment illustrates how the present invention uses a single type of PMOS transistor to fabricate a signal generator and its shift register. First Embodiment: Referring to Figure 2, there is shown a block diagram of a signal generating structure according to a first embodiment of the present invention. The CPU 5 generates a scan driver or data driver for a flat panel display, which includes a multi-stage shift register 210 connected in series. Figure 2 shows only the Nth stage, the (N+1)th stage, and the (N+2) 1263048 level shift register 210 in series. The Nth stage shift register 210 includes a first PMOS transistor MPln, a second PMOS transistor MP2n, a capacitive element Cn, and an nth voltage reset element 212. The drain of the transistor MPln receives the input signal INPUT, that is, the output signal OUI^N1 of the (N-1)th stage shift register 210 (not shown), and the gate of the transistor MPln is received. Pulse signal XCK. The gate of the transistor MP2n is coupled to the source of the transistor MPln, and the capacitor Cn is connected across the source of the transistor MP2n and between the gates. The capacitive element Cn can be an external capacitor or a parasitic capacitance of the gate of the transistor MP2n. The drain of the transistor MP2n is used to output the signal OUT_N, and the source of the transistor MP2n receives the clock signal CK. The clock signals CK and XCK are inverted signals. The voltage reset element 212 of the Nth stage shift register 210 includes a third PMOS transistor MP3n, a fourth PMOS transistor ΜΡ4n, and a fifth PMOS transistor MP5n. The gate of the transistor ΜΡ3π is connected to the gate of the transistor MP2n, and the gate of the transistor MP3n is connected to the anode of the transistor MP4n and the transistor MP5n, and the source of the transistor MP3n is connected to VDD. The gate of the transistor MP4n is connected to the drain of the transistor MP3n, and the source of the transistor MP4n is connected to VDD. The drain of the transistor MP5n is connected to the drain of the transistor MP4n, and the source of the transistor MP5n is connected to GND. In addition, the gate of the transistor MP5n receives the output signal OUT_N+1 of the (N+1)th stage shift register 210 as a reset signal. Similarly, the (N+1)th stage shift register 210 includes a first PMOS transistor ΜΡ1 (n+1), a second PMOS transistor MP2 (n+1), a capacitive element C(n+1), and The (n+1)th voltage resets the component 212. The drain of the transistor ΜΡ1 (η+1) receives the output signal OUT-N, and the gate of the transistor ΜΡ1 (η+1) receives the clock signal CK. The gate of the transistor MP2(n+l) is coupled to the source of the transistor ΜΡ1(n+1), and the capacitive element C(n+1) is connected across the source of the transistor MP2(n+l) and Between the gates 1263048. The capacitive element C(n+1) is, for example, a parasitic capacitance of the transistor MP2 (n+1). The drain of the transistor MP2 (n+l) is used to output the signal OUTJM+1, and the source of the transistor MP2(n+l) receives the clock signal XCK. It should be noted that the two first PMOS transistor gates of the adjacent two-stage shift register 210 in the signal generator 200 receive the inverted clock signal. Further, the (n+1)th voltage resetting element 212 includes a third PMOS transistor MP3 (n+1), a fourth PMOS transistor MP4 (n+1), and a fifth PMOS transistor MP5 (n+1). The connection relationship of the transistors is the same as that of the nth voltage resetting element 212, and will not be described here. The gate of the transistor ΜΡ5 (n+1) receives the output signal 〇UT_N+2 of the (Ν+2) stage shift register 210 as a reset signal. Referring to FIG. 3, an operation timing chart of the Nth stage and the (N+1)th stage shift register 210 in FIG. 2 is shown. In the first timing period T1, the input signal INPUT is the first input level (VIL), for example, the GND potential, and the clock signal XCK is the first clock level (VCL), for example, the GND potential, and the clock. The signal CK is the second clock level (VCH), for example, the Vdd potential. Thus, the transistor MPln is in an on state. The potential vx is pulled to a relatively low level (VlL + Vth), wherein the voltage Vth is the threshold voltage of the transistor MPln. At this time, the gate potential (VIL + Vth) of the transistor MP2n is lower than the source potential VCH. Therefore, the transistor MP2n is also turned on, and the signal 〇UT_N is an ideal high level VCH, and is fed back to the gate of the transistor MP4n in the voltage resetting element 212 of the Nth stage, so that the transistor MP4n is not turned on. Because the output signal 〇UT_N+l is the high level VCH at this time. Therefore, the transistor MP5n is not turned on. At this time, the level of the voltage VY is the state of the previous cycle, but the output result of the signal 〇UT_N is not affected regardless of the vY level. That is, at the first cycle T1, the signal OUT-N outputs a high level VCH. Then, in the second period T2, the input signal INPUT is the second input level 1263048 bits (νΙΗ). The clock signal CK is the second clock level (VCH), and the clock signal XCK is the first clock level (VCL). Since the gate potential VIH of the transistor MPln is higher than the source potential VCL, the transistor MPln is not turned on. The source potential of transistor MP2n is reduced from VCH to VCL. Therefore, the potential of the node Vx is stepped down to the level ((VIL+VthHVCH-VCL)) level due to the action of the step-down capacitor Cn. This level is still smaller than the source potential VCL of MP2n, and the buck technique is utilized. It can solve the shortcoming that the PMOS circuit of the conventional shift register cannot create an ideal low level. At this time, the transistor MP2n is still in an on state, and the signal OUT_N is an ideal low level VCL, and is fed back to the gate of the transistor MP4n, so that the transistor MP4n is turned on, and the node VY voltage is VDD. Since the gate potential VDD of the transistor MP3n is equal to the source voltage VDD, the transistor MP3n is not turned on. At this time, the signal OUT_N is input to the drain of the transistor ΜΡ1 (n+1) in the (N+1)th stage shift register 210 at the low level VCL, and the clock signal CK is the low level VCL. Each element of the (N+1)th stage shift register 210 operates like the Nth stage shift register 210 of the first period T1, and the transistors ΜΡ1(n+1) and MP2(n+l) are both turned on. The output signal OUT_N+1 is made high level VCH. The signal OUT_N+1 is fed back to the gate of the transistor MP5n in the Nth voltage resetting element 212, so that the transistor MP5n is not turned on. In the third timing period T3, the input signal INPUT continues to be at the high level VIH. The clock signal CK is at a high level VCH, and the clock signal XCK is a low level VCL. At this time, the transistor MPln of the Nth stage shift register 210 is in an on state, so that the potential of the node Vx is at the high level VIH, and thus the transistor MP2n is not turned on. In the (N+1)th stage shift register 210, like the Nth stage shift register 210 of the second period T2, the capacitive element C(n+1) is stepped down, so that the transistor ΜΡ2(n) +1) is turned on, and the signal OUT_N+l outputs the low level VCL of the signal XCK. The signal OUT_N+1 is fed back to the 1263048 gate of the transistor MP5n in the voltage resetting element 212 of the Nth stage, so that the transistor MP5n is turned on. At this time, the voltage of the node VY is a relatively low level (GND + Vth), turning on the transistor ΜΡ 3η. Therefore, the signal OUT-Ν outputs an ideal high level (=VCH) and is fed back to the gate of the transistor η4η, so that the transistor ΜΡ4η is in a non-conducting state. As shown in FIG. 3, the output signal OUT_N phase of the second stage shift register 210 is shifted to the right by a half period T/2 with respect to the input signal INPUT phase, and the (N+1)th shift is temporarily suspended. The output signal OUT_N+1 phase of the memory 210 is shifted to the right by a half period T/2 with respect to the phase of the output signal 〇UT_N, so that there is no conventional signal overlap, thereby saving the cost of using the AND gate logic circuit. Second Embodiment: Referring to Figure 4, there is shown a block diagram of a signal generator in accordance with a second embodiment of the present invention. The signal generator 400 is, for example, a scan driver or a data driver applied to a flat display, and includes a multi-stage shift register 410 connected in series with each other. FIG. 4 shows only the Nth stage, the (N+1)th stage, and the (N+2)th stage shift register 410 in series. The Nth stage shift register 410 includes a first PMOS transistor MPln, a second PMOS transistor MP2n, a capacitive element Cn, and a voltage reset element 412 of the Nth stage. The drain of the transistor MP In receives the input signal INPUT, and the gate of the transistor MPln receives the clock signal XCK. The connection relationship between the transistors MPln, MP2n and the capacitive element Cn is the same as that of the Nth stage shift register 210 of the first embodiment, and will not be described herein. The drain of the transistor MP2n outputs the signal OUT_N, and the source of the transistor MP2n receives the clock signal CK. In addition, the voltage resetting element 412 of the Nth stage includes a third PMOS transistor MP3n, a fourth PMOS transistor MP4n, and a fifth PMOS transistor MP5n. The connection relationship of the transistors MP3n, MP4n, and MP5n is also the same as that of the voltage resetting element 212 of the Nth stage of 13 1263048 of the first embodiment, and will not be described here. However, in the second embodiment, the gate of the transistor η5η receives the clock signal XCK as a reset signal. Similarly, the (Ν+1)th stage shift register 410 includes a first PMOS transistor ΜΡ1 (n+1), a second PMOS transistor ΜΡ2 (n+1), a capacitive element C(n+1), and The (n+1)th voltage reset element 412. The drain of the transistor ΜΡ1 (η+1) receives the output signal OUT_N, and the gate of the transistor]\4?1 (11+1) receives the clock signal €{:. The source of the transistor MP2 (n+1) receives the clock signal XCK. The connection between the transistor ΜΡ1 (n+1) and the MP2(n+l) is also the same as the (N+1)th stage shift register 210 of the first embodiment. Moreover, the two first PMOS transistor gates of the adjacent two-stage shift register 410 in the signal generator 400 receive the inverted clock signal. In addition, the voltage resetting element 412 of the (N+1)th stage includes a third PMOS transistor MP3 (n+1), a fourth PMOS transistor MP4 (n+1), and a fifth PMOS transistor MP5 (n+l). ). The connection relationship of the respective transistors is the same as that of the voltage resetting element 212 of the Nth stage in the first embodiment, and will not be described herein. The gate of the transistor MP5(n+1) receives the clock signal CK as a reset signal. Referring to FIG. 5, an operation timing chart of the Nth stage and the (N+1)th stage shift register 410 in FIG. 4 is shown. As in the first embodiment, in the first timing period T1, the input signal INPUT is the first input level VIL, the clock signal XCK is the first clock level VCL, and the clock signal CK is the second clock pulse. The bit vch° transistor MPln is in an on state. The Vx potential is pulled to a relatively low level (VIL + Vth). At this time, the transistor MP2n is also turned on, and the signal OUT_N is outputted to an ideal high level VCH, and is fed back to the gate of the transistor Mn in the voltage resetting element 412 of the Nth stage, so that the transistor MP4n is not turned on. Since the clock signal XCK of the gate of the input transistor MP5n is the low level VCL, the transistor MP5n is turned on, so that the potential of Vy is a relatively low level 14 1263048 (GND+Vth), and is output to the gate of the transistor MP3n. , the transistor MP3n is turned on, and the signal OUT_N outputs a high level (VDD). Then, in the second period T2, the input signal INPUT is the second input level VIH. The clock signal CK is the first clock level VCL, and the clock signal XCK is the second clock level VCH. The transistor MPln is in a non-conducting state. The source potential of transistor MP2n is reduced from VCH to VCL. Therefore, the Vx potential is step-down to the level ((VIL+Vth)-(VCH-VCL)) due to the action of the step-down capacitor Cn, which is still less than the source potential VCL of MP2n. By using this step-down technique, the disadvantage that the PMOS circuit of the conventional shift register cannot create an ideal low level can be solved. Therefore, the transistor MP2n is still in an on state, and the signal OUT_N outputs an ideal low level VCL, and is fed back to the gate of the transistor MP4n, so that the transistor MP4n is turned on, and the node VY voltage is VDD (high level). . Since the gate potential of the transistor MP3n (=VY voltage = VDD) is equal to the source voltage VDD, the transistor MP3n is not turned on. Due to the gate potential of the transistor MP5n (=XCK = VCH), the transistor MP5n is not turned on. At this time, the low level signal 〇UT_N is input to the drain of the transistor [\4?1 (11+1) in the (N+1)th stage shift register 410, and the clock signal CK is at the low level. VCL, like the Nth stage shift register 410 of the first period T1, the transistors ΜΡ1(n+1) and MP2(n+1) are both turned on, so that the output signal OUT_N+l is at the high level VCH. In the third timing period T3, the input signal INPUT continues to be the second input level VIH. The clock signal CK is at the high level VCH, and the clock signal XCK is at the low level VCL. At this time, the transistor MPln is in an on state, so that the Vx potential is at the high level VIH, so the transistor MP2n is not turned on. In the (N+1)th stage shift register 410, like the Nth stage shift register 410 of the second period T2, the capacitive element C(n+1) is stepped down, so that the transistor MP2(n) +l) is turned on, and the signal OUT_N+l outputs the low level VCL of the signal XCK. At this time, the gate potential of the transistor MP5n is equal to 15 1263048 XCK is a low level VCL, so the transistor MP5n is in an on state, and the VY potential is a relatively low level (GND+Vth), and is output to the gate of the transistor ΜΡ3η. The pole turns on the transistor ΜΡ3η. Therefore, the signal OUT_N outputs an ideal high level (VDD) and is fed back to the gate of the transistor MP4n, so that the transistor MP4n is in a non-conducting state. As shown in FIG. 5, the output signal OUT_N phase of the Nth stage shift register 410 is shifted to the right by a half period T/2 with respect to the input signal INPUT phase, and the (N+1)th shift is temporarily suspended. The output signal OUT_N+1 phase of the memory 410 is shifted to the right by half a period 172 with respect to the phase of the output signal 〇UT_N, so that there is no conventional signal overlap, thereby saving the cost of using the AND gate logic circuit. As described above, the present invention has a first PMOS transistor and a second PMOS transistor in a shift register, and the voltage reset element has a third PMOS transistor, a fourth PMOS transistor, and a fifth PMOS transistor. For example, the shift register of the present invention may also be a single-mode NMOS transistor, or even the other first switching element and the second switching element respectively have a first clock signal and a second clock. The signal is controlled, and the voltage reset element can also be a third PMOS transistor or a third switching element, or even other circuits, which can be controlled to be turned on or off by a reset signal to provide a desired output signal. As long as the first switching element and the second switching element are turned on and the voltage resetting element is not turned on during the first timing cycle, the first switching element is not turned on, the second switching element is turned on, and the voltage resetting element is not turned on in the second timing cycle. Turned on, and in the third timing cycle, the first switching element is turned on, the second switching element is not turned on, and the voltage resetting element is turned on and outputs the required level signal, and the purpose of the signal phase shifting is not deviated from the present The technical scope of the invention. In addition, the capacitive component of the shift register can also be coupled to the gate of the second PMOS transistor by other buck-boost components, as long as the second PMOS transistor gate potential can be pulled down in the second timing cycle to reach 16 1263048. The effect is also not deviated from the technical scope of the present invention. The signal generator and its shift register disclosed in the above two embodiments of the present invention have the advantage that the shift register circuit can be implemented on a glass substrate by using LTPS PMOS or NMOS process technology. Since the number of masks used in a single PMOS or single NMOS process is less than that of CMOS, in addition to saving mask costs, it is possible to increase the panel throughput per unit time (Throughput). In the above, although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and various modifications may be made without departing from the spirit and scope of the invention. And the scope of the present invention is defined by the scope of the appended claims. 17 1263048 [Simple description of the diagram] Figure 1A is a circuit diagram of a conventional multi-stage complementary shift register. Fig. 1B is a timing chart showing the shift register and the input signal input, output signals out_1 and out_2 in Fig. 1A. Fig. 2 is a block diagram showing the structure of a signal generator in accordance with a first embodiment of the present invention. Fig. 3 is a timing chart showing the operation of the nth stage and the (N+1)th stage shift register in Fig. 2. Fig. 4 is a block diagram showing the structure of a signal generator in accordance with a second embodiment of the present invention. Fig. 5 is a timing chart showing the operation of the Nth stage and the (N+1)th stage shift register in Fig. 4. [Description of main component symbols] 100, 210, 410: Shift register 102, 112: Inverter, 200, 400: Signal generator 212, 412: Voltage reset element 13