TWI251395B - Pulse width modulation apparatus by using output voltage feedback delay circuit to automatically change the output frequency - Google Patents

Abstract

A kind of pulse width modulation (PWM) apparatus by using output-voltage-feedback-delay circuit to automatically change the output frequency is revealed in the present invention. A delay comparison circuit is used to extract a feedback voltage, a high threshold voltage and a low threshold voltage. After conducting comparison operation and delay operation onto these voltages, a frequency conversion signal is outputted to a signal synchronization circuit which is used to receive the frequency conversion signal such that the output terminal outputs a power-saving enable signal to a dual-frequency oscillator for respectively changing the oscillation frequency of two band sections, i.e., one high frequency band (40Khz to 100Khz) and one low frequency band (18Khz to 27Khz), of the dual-frequency oscillator so as to provide it to a PWM controller. After the PWM controller receives the oscillation frequency, a driving signal is outputted according to the oscillation frequency such that the power supply is capable of appropriately reacting to the instantaneously-varied operation environment to reach even better efficiency or more stable output for obtaining the power-saving effect.

Description

1251395 IX. Description of the Invention: [Technical Field] The invention relates to a pulse width modulation device which automatically changes an output frequency by using an output voltage feedback hysteresis circuit, in particular, a power supply device for following a load change and thereby changing A pulse width modulation device that outputs a switching frequency. [Prior Art] In many low-power output applications, such as mobile phones, wireless phones, digital cameras, PDA chargers, as well as printers, TV game consoles and handheld walkman AC voltage regulators, etc. The power saving requirements are quite high. According to the currently known DC power supply devices, such as AC To DC SWliixhing Power Supply, in order to reduce the size of the transformer, high frequency pulse width modulation (PWM) is often used to control the DC output voltage. As shown in the first figure, it is a schematic circuit diagram of a conventional flyback power supply device. The transformer T1 divides the circuit into a primary side prior stage circuit 101 and a secondary side subsequent stage circuit 102. The primary side 101 and the The secondary side 102 separates the electrical signals of the primary side 101 and the secondary side 102 by a photoelectric crystal 111 and a photodiode 112, but can use the optical signal to feedback the voltage or current output change of the secondary side 102. The signal is applied to the primary side 101 to synchronously adjust the voltage and current variations of the primary side 101 and the secondary side 102, or as a feedback signal for overcurrent and short circuit protection. Referring to the first figure, an AC voltage VAC is input to the primary side 101. The AC voltage VAC is passed through an EMI filter 1010, a bridge rectifier BD1, and a high voltage filter capacitor C1 to become a DC voltage Vin. The DC voltage Vin is controlled by a pulse wave adjustment control unit U1 to control the conduction period of the power electronic opening 1251395 to the Q1, and then to the primary winding of the transformer T1. On the same day, the secondary side winding of the transformer is transformed into an induced output voltage. The output voltage is rectified and filtered by the diode D1 and the electrolytic capacitor C2 to generate a stable DC voltage Vout output. The DC voltage Vout is converted into a voltage signal Vfb and fed back to the pulse width adjustment control unit 一次 of the primary side through a feedback regulator D3 and an optical coupler u. At the same time, when the power electronic switch Q/1 is turned on, a current feedback signal Ves is obtained through the resistor R2, and the current return signal Vu is transmitted to the pulse width adjustment control unit U1, and the pulse width adjustment control unit 取得ι obtains the current. The feedback signal Ves and the voltage signal Vfb are used to calculate an output pulse wave pWM to the power electronic switch for stabilizing the output DC voltage Vout. The optical coupler n is composed of the photo-crystal 111 and the photodiode 112. Please refer to the second figure, which is the block diagram of the internal circuit of the conventional pulse width adjustment control unit. The pulse width adjustment control unit is composed of a pwM comparator 14, an overcurrent comparator 16, a flip-flop 18, and a (〇R) gate circuit. The pulse width modulation (PWM) technique works by providing a fixed frequency pwMclock to the pulse width adjustment control unit U1 by the oscillation circuit 12. And the PWM comparator 14 in the pulse width adjustment control unit ui is responsible for detecting the voltage signal Vfb fed back by the output DC voltage v〇ut, and detecting the current feedback signal vcs for comparison operation, Output a modulated output signal PWMout. The overcurrent comparator 16 further compares the current feedback signal Vcs with a current limit level IV to output an overcurrent enable signal 0CPEN. After the modulation output signal pwMout and the overcurrent enable signal 0CPEN are ORed (OR), a reset signal R is output to the R pin of the flip-flop 18. The S pin of the flip-flop 18 is connected to the 1251395 to the oscillating circuit 12 for obtaining a fixed frequency pWMcl〇ck as a rate, and through the logical operation of the (0R) and the inverse (NOT), the rear wheel is used as the frequency signal Drv to Power switch (not shown) ◦ (9) out ~% With the second picture, please refer to the third picture, which is a schematic diagram of the internal signal waveform of the conventional pulse control unit. As shown in the third figure, the 楱 is followed by the time axis t, and the vertical axis is represented as each waveform. When the time is cut to the $ axis, the voltage signal Vfb is a heavy load. At this time, the current enable signal 〇 cpEN 舆 time 吼唬PWMoui: After the logical operation of (R), the output repeats: 蚤 蚤 用以 浓 浓 浓 浓 18 18 18 18 18 18 18 18 18 ^ ^ ^ ^ ^ , , , , , , , , , , , , , , , , , Cycle) ^Width, this can provide the power required by the load.跫 长, 知士同理, at time t12-12, is in the normal working history negative, when the positive and negative device 18 output driving signal!)" output square wave will be old, this = the width of the power. Furthermore, in time ΐ 2-13 load becomes lighter than usual 致 = = 致 〇 EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN The electric (OR) message has a fixed frequency. The PWM clock is simultaneously subjected to the operation of the flip-flop 18 to take 12 rounds, so that the output of the driving signal Drv outputted by the flip-flop 18 can be provided to provide the power required for the light load. Here, the power switch (not shown) driven by the drive signal Drv does not change its operating frequency due to the change of the duty cycle of the output square wave. In other words, the working frequency of the turtle path is always It is fixed, so under the light planting, the driver #b Drv will follow the frequency PWMclock to fix the short working period, which will cause the power loss under light load. In the above, the time is the broadcast state. No drive signal Drv output, this segment is skipped Cycle (SKIPPED CYCLE). 丄 251395 When the electronic product is in full #.10a often, the system is operated under the load condition of the pulse heart circumference ^ 4, the work loss is controlled by technology (PWM) to control the switching. When the switch is switched, the product has a loss and switching loss at the light load. However, the switch 4 of the electronic switch is still controlled by the pulse modulation technology (PWM) to control the switching on and off, but because the d conduction loss will be due to the electronic product. At light load, the switching loss is not the same as ": the working frequency of the change is fixed, so the switching pulse width modulation technology is reduced, so when it is lightly loaded, the use of the system has the overall efficiency system." Will decrease. To stop the drive to drive to:: Coffee (PWM), which can be switched at light load. ^ Tiger to switch, to stop switching switch to reach! The role of the electric mode. Referring to the fourth figure, it is a conventional knowledge: "The pulse of the formula is shown in the circuit block diagram of the modulator. As shown in the fourth figure, the system is obtained from the load - feedback voltage signal Vfb and - = technology The current signal ves, the feedback voltage signal Vfb is transmitted to the - period mask/comparison 22 and is compared with a threshold voltage value vthlf for outputting a power-saving enable signal GreenEN. The feedback voltage signal VFB is transmitted through one cent

The voltage circuit 21 is a feedback error voltage VE, and the feedback error voltage VE and the feedback current signal Vcs are simultaneously transmitted to a comparator 24 for comparison operation to output a modulated output signal pWM〇ut . The feedback current signal Ves is compared with a current limit level IV through an overcurrent comparator 23 to output an overcurrent enable signal 0CPEN. The power-saving signal GreenEN, the modulated output signal PWMout and the overcurrent enable signal 0CPEN are subjected to a logic operation of OR or OR to output a reset signal R, the reset signal R It is transmitted to the reset terminal (R) of the RS flip-flop 28 and is processed by the frequency PWM clock transmitted to the RS (reverse-rectifier 28) set terminal (S). At the same time, the RS flip-flop! 251395 28-channel transmission or (OR And the logical operation of the inverse (NOT) to output the _ drive signal Drv to control the switching action of the power switch (not shown). With reference to the fourth figure, referring to the fifth figure, it is a circuit waveform diagram of a pulse width modulator having a conventional power saving mode. As shown in the fifth figure, the horizontal axis is represented as the time t, and the vertical axis is not the waveform. During the time 10 to 11 time, the voltage signal Vfb is in a normal load state. At this time, the current enable signal 0CPEN, the modulated output signal PWMout, and the power-saving enable signal GreenEN are processed by the OR gate 26 or (OR), and the output is heavy. The signal R is used to cause the driver of the flip-flop 28 to output a power switch (not shown) to provide the power required by the load. In the case of Bu J, in the time team, the corpse is released, and the voltage signal VFB is compared with the threshold voltage value Vthli, and the high voltage is obtained when the voltage signal VFB is less than the threshold voltage vthlf. ^ Enable the signal GreenEN, the power-saving signal GreenEN is used to drive the generation of the signal Drv, and then achieve power-saving effect under light load. a 凊 Referring to the sixth figure, the internal circuit oscillating circuit 12 of the 知 电路 电路 circuit uses the voltage source VDD to supply power 22 R1, R2, R3 to obtain the threshold voltages VH, VL, and compares α to obtain the threshold voltages VH, VL At the same time, the comparison operation is performed on: 1, 12^. After the calculation, the charge/discharge t is used to adjust the charge and discharge operation of the control current source II and the control terminal, the ☆, and the flip-flop. Furthermore, the oscillating circuit 12 performs a capacitor on the terminal to generate a frequency ambiguity _ providing a pulse width two == a complex reference fourth picture, the power saving ~ adjusting the threshold voltage value Vthlf and the current limiting circuit IV' makes the load normal, I251395 = to drive the drive signal Drv according to the frequency PWMclQck to stop and drive the drive signal Drv to the power gate when I or no load: Coordination: to meet the power mode requirement. However, this kind of power-saving mode will make the sleep state after the negative load or no load, and may even enter the machine to cause undesired control of the IG_ or the instability of the output. SUMMARY OF THE INVENTION The present invention is a pulse width modulation device that utilizes an output voltage feedback hysteresis circuit from a source two frequency, the main purpose of which is to use the electrical rate to follow the load change. And changing the switching frequency of the output to achieve the above purpose, the present invention utilizes a hysteresis comparison circuit for intercepting,,,,: a high threshold voltage and a low threshold voltage, and outputting the second-order differential hysteresis operation - Variable frequency signal. The frequency conversion is transmitted to the output of the signal-synchronous circuit connected to the hysteresis comparison circuit, the output of the power-saving signal is transmitted, and the dual-frequency oscillator is received by the dual-frequency oscillator. Signal, use two, 钿 phase = oscillation frequency. The oscillating frequency is transmitted to a PWM controller connected to the 颂 颂 oscillating state, and the PWM controller receives the oscillating rate, and the port is based on the oscillating frequency comparison operation to feedback the voltage signal and the feedback packet " The nickname takes a driving signal. The pulse width modulation device of the invention receives the voltage of the voltage at the load end of the power supply, and uses a certain power, the source transmits power to the two series connected resistors, and the knife of the source is transmitted through the two resistors connected in series. Pressing to provide the high threshold voltage and the low threshold voltage to the second comparison, respectively, after comparing the two comparators, respectively outputting two comparison apostrophes to a flip-flop. After the comparison signal is operated by the flip-flop, the frequency conversion signal is outputted to the simple synchronization circuit, and the signal-side circuit is transmitted according to the frequency conversion signal I251395 := electro-energy signal and transmitted to the dual-frequency oscillation crying, 雔j vibration state system After receiving the power-saving enable signal, the button is deducted.忒 and then to the PWM controller, the controller: according to the rate of input and output signals. In the above description, _ Kang Qian Meng frequency follows the light and heavy changes of the load, and then changes the oscillator system to the PWM controller, so that the power supply can be provided to the line, thereby achieving better efficiency or more stable. The effect of the operation. Rebellion from achieving power saving [Embodiment] A ^ S test seventh figure, is a schematic diagram of the pulse width modulation band of the present invention. The pulse width modulation of the present invention is set to 3, and the load change of the two-way blocker 'and the output drive nano source supply - hysteresis comparison circuit 32, fresh material' includes: 34 and a PWM controller 36. The third embodiment of the present invention is applied to the power supply feedback voltage Vfb, and the power is transmitted by the line current source as the resistor R1 and the second resistor R2. The voltage division of the power is performed through the string resistor Rb R2 to obtain _high [VH and - low threshold voltage VL, respectively. Furthermore, the hysteresis comparison circuit (10)

The feedback voltage VFB, the high threshold voltage VH, and the low threshold voltage output a variable frequency signal QS after the father and the ice carrier are transported. The variable frequency signal is transmitted to the signal synchronizing circuit 33 connected to the hysteresis comparison circuit 32. The signal synchronizing circuit 33 is configured to output and transmit the green signal ENEN to the dual-frequency oscillator 34 according to the variable frequency signal QS. The dual-frequency dual-disc 34 receives the power-saving enable signal Gre enEN, and the tether Correspondingly, the oscillation frequency is connected to the PWM controller 36c) pwM 11 !251395 controller 36 connected to the dual-frequency oscillator 34, and the comparison operation between the feedback voltage signal Vfb and the feedback current signal Vcs is performed according to the oscillation frequency. To output a drive signal Drv. The driving signal Drv is simultaneously performed with an over-voltage signal 0Vp or (OR) 4 logic operation and inverse gate (Ν〇τ) calculation for controlling the switching action 0 of the power switch 5 in the hysteresis comparison circuit 32. The non-inverting input terminal (+) of the first comparator 320 is connected to the power supply load terminal (not labeled) for receiving the feedback voltage Vfb, and the inverting input terminal (1) is connected to the predetermined

A current source CIS' is used to receive the high threshold voltage vh. Furthermore, the hysteresis comparison circuit 32 is connected to the power supply negative terminal by using the inverting input terminal (1) of a second comparator 322 for receiving the feedback voltage Vfb and its non-inverting input terminal (+ The first resistor R1 is connected to the constant current source CIS while the second power is connected to the ground reference G to receive the low 63⁄4 boundary voltage VL. In the hysteresis comparison circuit, there is a flip-flop 324, which is an RS flip-flop, and one reset terminal (R) of the Rs flip-flop is connected to the round output end of the second comparison state 320, and a set terminal (s) Connected to the output of the second comparator 322, and one of the RS flip-flops Q is connected to the signal

The number synchronizing circuit 33 outputs the variable frequency signal QS to the signal synchronizing circuit 33, and the signal synchronizing circuit 33 is an anti-reactor. Please refer to the eighth figure for the purpose of the circuit block of the dual-frequency oscillator of the present invention. The dual frequency oscillator 34 is connected by the -vibration generating unit 34Q through the selecting unit 342. The first charging and discharging unit 344 is a unit 346 for outputting two different oscillation frequencies. The 振340 is formed by the three resistors R3, R4, and R5 passing through the two comparators 34, and the material is connected to an RS flip-flop 3404. Three power _R3, R4 source VDD to obtain a first reference ink by partial pressure 働 ^ 妾 12 1251395

^Vthlow, and the round-trip Q of the RS flip-flop 34〇4

Cycle §fl number output. The frequency selection unit 342 is connected to the current and the power saving from the hysteresis comparison circuit 32::::GreenEN ' is used to selectively drive the first charging/discharging unit 344 or the = signal soaping unit 346 for charging and discharging. The action. The first charge and discharge. . The younger brother has a first-charge control current source Iclf and a -first -^^ ▲ source 'Idclf. By adjusting the two control current sources, different first charge and discharge signal outputs can be generated on the electric switch. The second charging and discharging unit includes a second charging control current source Ichf and a second discharging control band U original I dchf, which can be different in the capacitor crying by adjusting the current source system. Charge and discharge signal output. ~

The charge and discharge signals are sent back to the wheel terminals of the two comparators 34〇〇 and 34〇2, and are respectively compared with the first reference voltage vthhigh and the second reference voltage Vth^= through the two comparators 3400 and 3402. Operation & through: RS is positive and negative for the output terminal Q and ρ of the 3404 output one cycle signal. 'The 雔 frequency vibration i is 34 series according to the power saving enable signal GreenEN used to change the output of the charge and discharge signal or the second charge and discharge signal, and after the feedback comparison, at the output of the RS positive and negative 3404 The oscillation frequency of a low frequency band (MKhz to 27Khz) or a high frequency band (40Khz to lOOKhz) is output. Please refer to the ninth figure, which is a schematic diagram of the internal circuit block of the P-controller of the present invention. The PWM controller 36 is composed of a comparator 360, or gate circuits 362, 361, an RS flip-flop 364, and a voltage dividing circuit 366. The voltage dividing circuit 366 receives the feedback voltage signal Vfb for outputting an error voltage signal vE, and the comparator 360 receives the error voltage signal VE and the feedback current signal Vcs to perform a comparison operation for a rounding Change the output signal PWMout. The t-cycle output signal PWMout and an over-current enable signal 0CPEN pass or gate 13 1251395 circuit 362 perform OR operation (OR), and output a reset signal R to the R pin of the RS flip-flop 364. The S pin of the RS flip-flop 364 is connected to the dual-frequency oscillator 34 shown in FIG. 7 to obtain the oscillation frequency PWMclock as the operating frequency, and is rotated by the OR circuit 361 and a reverse gate (NOT). The drive signal is here. With reference to the seventh figure, please refer to the tenth figure, which is a schematic diagram of the circuit signal waveform of the present invention. As shown in the tenth figure, the vertical axis represents voltage (V) and the horizontal axis represents time (t). In conjunction with the seventh figure, the hysteresis comparison circuit 32 receives the high threshold voltage VH and the feedback voltage VFB by using the first comparator 320, and further compares and outputs a first comparison signal CS1. The second comparator 322 receives the low Sa boundary voltage VL and the feedback voltage Vfb, and compares and outputs a second comparison signal CS2. The first comparison signal CS1 and the second comparison signal CS2 are respectively transmitted to the reset end (R) and the set end (S) of the RS flip-flop 324, and are operated by the RS flip-flop 324 to output the Frequency conversion signal QS. The variable frequency signal QS is transmitted to the signal synchronizing circuit 33, and the signal synchronizing circuit 33 outputs the power saving enable signal GreenEN to the dual frequency vibrator 34 according to the oscillation frequency PWMclock. The power-saving enable signal GreenEN is used to select the oscillation frequency PWMclock output from the dual-frequency oscillator 32. The oscillating frequency PWMclock is transmitted to the PWM controller 36. After receiving the oscillating frequency P volt clock, the PWM controller 36 outputs a driving signal according to the oscillating frequency PWMclock. The oscillation frequency PWMclock shown in the tenth figure is 22KHZ under light load (low) means cycle time is 45 # s, and under heavy load (high) is 65KHZ means cycle time is 15 // s. Referring to the tenth figure, during the time to-tl, the circuit is in a light load state, at this time, the power-saving enable signal GreenEN is high, and the high-potential power-saving signal GreenEN is transmitted to the dual-frequency oscillator 34. To adjust the charge and discharge signal on the 14 1251395 internal capacitor ct to output a low oscillation frequency, the PWM clock is used by the PWM controller 36. In the above, the power-saving enable signal GreenEN drops from a high potential to a low potential at a time ,, and the drop is synchronized with the oscillation frequency PWMclock. Moreover, during the time period, the circuit system is in a heavy load state, at which time the power-saving enable signal GreenEN is a low power bit, and the low-level power-saving enable signal GreenEN is transmitted to the dual-frequency vibration converter 34 for The charge and discharge signal on the internal capacitor CT is adjusted to output a high oscillation frequency PWM clock to the PWM controller 36. In the above, the power-saving enable signal GreenEN rises from a low potential to a high potential at time t2, and its level rise is synchronized with the second comparison signal CS2. Then, during the time t2-13 _, the light load state is returned again. At this time, the dual frequency oscillator 34 outputs the low oscillation frequency PWM clock to the PWM controller 36. Furthermore, please refer to the signal synchronization circuit 33 of the seventh figure. At time 1:3-t4, the frequency conversion signal is high, the oscillation frequency PWMclock is low, and the frequency conversion signal qs is transmitted to the signal synchronization circuit 33. The reset terminal (R), the burst frequency PWM clock is transmitted to the set terminal (s) of the signal synchronizing circuit 33. Since the reset end (R) of the signal synchronizing circuit 33 has a higher signal priority than the set end (S), the power-saving enable signal GreenEN remains high during this electrical time and is not due to the vibrating frequency PWMc 1 ock The bit changes and changes. ^: Lu oscillation frequency PWMclock, which is an oscillation frequency of 65KHZ, and the low extension frequency PWMclock is an oscillation frequency of 22KHZ. - In the above description, the hysteresis comparison circuit 32 compares the feedback power Vp with the high threshold voltage VH and the low threshold voltage v1, and controls the variable frequency signal QS to delay the operation of the dual frequency oscillator 34. The dual-frequency oscillator 34 is caused by interference signals or noise generated when the load changes - causing the switching of the output oscillation frequency to be too frequent or causing the switching when the ★ Wu 151251395 is performed. Please refer to the eleventh figure, which is a waveform diagram for comparing the relationship between the output power, the frequency modulation signal, the feedback voltage and the oscillation frequency when there is no hysteresis in the present invention, wherein during the time t1 - t2, the load of the output power pout changes. The output voltage Vout will be affected, which will cause the noise of the feedback voltage Vfb to generate noise, which will affect the waveform output of the power-saving enable signal GreenEN. If there is no hysteresis in the circuit, the power-saving enable signal GreenEN output is the waveform of S1. At this time, because the power-saving enable signal GreenEN is not %, 疋, the oscillation frequency of the dual-frequency oscillator % output shown in the seventh figure is made. PWMclock will repeatedly switch the output low oscillation frequency and high oscillation frequency, which will lead to circuit power loss and work efficiency. If there is hysteresis in the circuit, the stable power-saving enable signal GreenEN output system is the waveform of S2. At this time, the oscillation frequency PWMcl〇ck output by the dual-frequency oscillator 34 shown in the seventh figure will be stable. Low Frequency is used to prevent noise (n〇ise) interference. In addition, during the period of the day-to-day ΐ3-ΐ4, when the load of the output power p〇ut changes, the output voltage V〇ut will be affected. Similarly, the feedback voltage VFB will generate noise (n〇1Se). The interference, which in turn affects the power-saving enable signal #GreenEN, waveform output. If there is no hysteresis in the circuit, as shown in the seventh figure, the dual-frequency oscillation of the 34-series will repeatedly switch the output low-vibration frequency and high-oscillation frequency, resulting in circuit power loss and reduced working efficiency. If it is, there is a delay of π in the Xun road. As shown in the seventh figure, the dual-frequency oscillator material will be stable and the oscillation frequency (Hlgh FreqUenCy) will be used to prevent the interference of noise (n〇ise). The present invention utilizes a hysteresis comparison circuit for taking a feedback voltage, a south-level voltage, and a low threshold voltage, and delivering the voltages to the 16 1251395 vehicle for the first time. After the operation, a frequency conversion signal is outputted to the signal synchronization circuit '%u fB> ^ 乂^ 夕 pen line output power-saving signal GreenEN to the dual-frequency oscillation two-degree remote dual-frequency oscillator receives the power-saving signal GreenEN is used to output the phase _ > γ , which is the oscillation frequency of the crying day. The oscillation frequency is transmitted to the brilliant control ^ / the PWM controller receives the oscillation frequency, according to the oscillation frequency 4 Order a drive signal. The dual-frequency oscillator will follow the light load and change the output frequency of two bands, namely a high frequency band (40Khz 1〇〇Khz) and a low frequency band (18Khz to 27Khz), ... PWM controller' Allowing the power supply to react at any time

The environment is designed to achieve better efficiency or more stable output to achieve power saving. ^Hai dual-frequency vibrator will output high frequency band when heavy load (4〇Khz

The vibration frequency I of μ 97〇KhZ) is output to the vibration frequency of the low frequency band (18Khz Khz) under light load to provide, to the p dragon controller. In this way, the present invention can reduce the frequency delay function of the circuit of the hysteresis circuit, and improve the switching situation necessary for the frequency material generated by the conventional power-saving technology, thereby reducing unnecessary switching loss and preventing noise (%). The interference phenomenon to achieve power saving effect. Where the king pays for the patent application, the application is based on the patent law, please read the details of the patent, and I will be able to guarantee the benefits of the inventor if Platinum A +Main + + soil. + > — The Beacons of the Spoon Board has any doubts. Please do not hesitate to give instructions. _ However, the above, i is the best embodiment of the present invention - the details of the brothers 14®;, 'It's the characteristics of the sun and the moon is not limited to this, not to limit the month, All the scopes of this patent shall be subject to the following patents, and the spirit of the patent application scope and the similar changes of the scope of this patent shall be included in the scope of the invention. Those skilled in the art are susceptible to variations or modifications within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS The first figure is a circuit diagram of a conventional flyback power supply device; the second figure is a block diagram of the internal circuit of the conventional pulse width adjustment control unit; the third figure is a conventional pulse width adjustment control The schematic diagram of the internal signal waveform of the unit; the fourth figure is a schematic diagram of the circuit block of the pulse width modulator with the power saving mode; the fifth figure is the circuit waveform diagram of the pulse width modulator with the power saving mode, the sixth The figure is a block diagram of the internal circuit of the conventional oscillating circuit; the seventh figure is a circuit block diagram of the pulse width modulation device of the present invention; the eighth figure is a circuit block diagram of the dual frequency oscillator of the present invention; The internal circuit block diagram of the device; the tenth figure is a schematic diagram of the circuit signal waveform of the present invention; and the eleventh figure is a schematic waveform diagram of the relationship between the output power, the frequency modulation signal, the feedback voltage and the oscillation frequency with or without hysteresis in the present invention. [Main component symbol description] Convention: T1 transformer 101 pre-stage circuit 1010 EMI filter 18 1251395 102 rear stage circuit VAC AC voltage 11 optical coupler 12 oscillation circuit 121, 122 comparator 123 flip-flop 111 photoelectric crystal 112 photodiode Body U1 pulse width adjustment control unit 14 PWM controller 16 over current comparator 18 forward and reverse 20 pulse width modulator 21 voltage divider circuit 22 period blanking comparator 23 over current comparator 24 PWM controller 26 or gate 28 RS forward and reverse device The present invention: 3 pulse width modulation device 32 hysteresis comparison circuit 320 first comparator 322 second comparator 1251395 3 2 4 flip-flop · 33 signal synchronization circuit _ 34 dual-frequency oscillator _ 340 oscillation generated Unit 3400, 3402 comparator 3404 RS flip-flop 342 frequency selection unit 344 first charge and discharge unit 346 second charge and discharge unit 10 36 PWM controller 360 comparator 361, 362 or gate circuit 364 RS forward and reverse 366 divided piezoelectric Road 4 or gate 5 power switch 20

Claims (1)

1251395 X. Patent application scope: 1. A pulse width modulation device that automatically changes the output frequency by using an output voltage feedback hysteresis circuit, which can follow the load change of the power supply, thereby changing the frequency of the output driving signal, including: The hysteresis comparison circuit intercepts a feedback voltage, a high threshold voltage and a low threshold voltage. After the comparison operation and the hysteresis operation, the voltages output an inverter signal; a signal synchronization circuit is connected to the hysteresis comparison circuit. Receiving the frequency conversion signal and an oscillation frequency, and outputting a power-saving enable signal at the output end; a dual-frequency oscillator connected to the signal synchronization circuit, receiving the power-saving enable signal for outputting a corresponding one of the oscillations And a P-controller connected to the dual-frequency oscillator, receiving the oscillation frequency, and outputting a driving signal according to the oscillation frequency. 2. The pulse width modulation device of claim 1, wherein the hysteresis comparison circuit comprises: a first comparator receiving the high threshold voltage; And comparing the output voltage to the first comparison signal; the second comparator receives the low threshold voltage and the feedback voltage, and then outputs a second comparison signal; and a flip-flop is connected to The first comparator and the second comparator receive the first comparison signal and the second comparison signal, and then calculate and output the frequency modulation signal. 3. As described in the second paragraph of the patent application, the output voltage feedback hysteresis 21 1251395 is used to automatically change the rim and the 百 、 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The voltage is fed back and its inverting wheel input is connected to "two π" to receive the high threshold voltage. Straight-level package source, use 4. For example, the second-line automatic change of the patent application range (four) round read-back feedback hysteresis, its reverse-phase modulation device, which is the second comparative DC power supply, and fine--- Electricity _ connected to - 5 such as Shen, special resistance series (four) - reference ground. • The use of the two-way automatic change of the rim of the ninth method of the patented squadron of the ninth patent is a RS positive and negative frequency modulating device, wherein the positive and negative device is The output terminal, ^定^:; (1) is connected to the first comparator 6. As claimed in the patent | Γ ^ the output of the second comparator. The road automatically changes the output Μ ί using the wheel-out voltage feedback hysteresis electrical system can output - high frequency band or - low frequency band #, = fM oscillation 7. As claimed in the scope of claim 6 use the wheel power = Second, the road automatically changes the pulse width modulation device of the wheel frequency, and its oscillation frequency ranges from 40Khz to lOOKhz. ^Before the band 8. As described in the scope of claim 7, the pulse width modulation device that automatically changes the frequency of the wheel by the wheel, the frequency of the vibration of the hair = delayed printing is in the range of z to 27 Khz. ~Low-frequency band 9. The pulse width modulation device that automatically changes the output frequency by using the wheel as described in item i of the patent application scope is widely used. Where the signal is synchronized 22