591670 五、發明說明（1) 本發明係有關於一種記憶裝置，特別是有關於一種以 錯誤校正編碼ECC (error correcting coding)型態儲存 主記憶區錯誤資訊之記憶裝置。 在目前要求高密度記憶體如非揮發記憶體的趨勢下， 唯有依賴冗餘陣列（redundancy array)的設計，方能對有 瑕疯之3己憶裝置進行修補以提高良率。冗餘陣列一般包括 備用行（spare columns)與備用列（Spare rows)。由記憶 裝置接收之多個行位址信號（c〇lumn address signals)， 經行碼器解碼以選擇對應之行位元線。 當行解碼器對行位址信號進行解碼而定址到一正常行 位元線時，致能信號會致能行解碼器以驅動此正常行位元 線；當2解碼器對行位址信號進行解碼而定址到一瑕疵行 位元線時，行取代信號會致能列備用解碼器以驅動備用行 而取代瑕疵行，士σ此一來，即可將所有需要存取道這些錯 誤位π之存取請求，導向到備用記憶區，藉此取代原本的 缺陷的記憶單元。 參閱第1圖，第1圖係顯示傳統記憶裝置之結構圖，一 般2裝置可分成多個記憶區，個別記憶區具有對應之備 用行*用以在s己憶區發生錯誤時取代上述記憶區發生錯 此即為前述之冗餘陣列。如第1圖所示，主記 :、:°!嚐：敌：應之備用打區i 2 5當記憶體製作完成後，藉 件主記憶區11之錯誤資訊，也就是主記憶區11 主4二之位址，並將之儲存於資訊區13。當系統致能 時，貝讯區13内部之錯誤資訊將由讀取電路14所讀取，並591670 V. Description of the invention (1) The present invention relates to a memory device, and more particularly to a memory device that stores error information of the main memory area in an error correcting coding (ECC) type. In the current trend that requires high-density memory such as non-volatile memory, only the design of redundant arrays can be used to repair the defective 3D memory device to improve the yield. Redundant arrays generally include spare columns and spare columns. A plurality of row address signals (column address signals) received by the memory device are decoded by the row encoder to select corresponding row bit lines. When the row decoder decodes the row address signal and addresses it to a normal row bit line, the enable signal enables the row decoder to drive the normal row bit line; when the 2 decoder performs the row address signal When decoding and addressing a defective row bit line, the row replacement signal will enable the column spare decoder to drive the spare row instead of the defective row. In this way, all the error bits π that need to be accessed can be accessed. The access request is directed to the spare memory area, thereby replacing the original defective memory unit. Refer to Figure 1. Figure 1 shows the structure of a traditional memory device. Generally, 2 devices can be divided into multiple memory areas, and each memory area has a corresponding spare line * to replace the memory area when an error occurs in the memory area. If something goes wrong, this is the aforementioned redundant array. As shown in Figure 1, the master ::: °! Taste: the enemy: should be used in the spare area i 2 5 After the memory is completed, borrow the error information of the main memory area 11, which is the main memory area 11 main The address of 4 2 is stored in the information area 13. When the system is enabled, the error information in the Besun area 13 will be read by the reading circuit 14, and
$ 5頁 C503-5812TW·pid 591670 I五、發明說明（2) |傳送至捏發性 時，將揮發性 1 6。比較器1 6 吻合，則代表 I 此以位7C線上 I解碼器17以備 I線，藉此以順 區1 1、備用行 力時仍可儲存 然而，為 主記憶區1 1設 路。此舉雖然 !主§己憶區11使 資訊係藉由主 此時位元線損 比較器1 6，當 址信號作比對 11錯誤位元線 電路複雜性而 同樣的位元線 法讀取主記憶 進行修補之動 有鑑於此 丨提供一種記憶 暫存器1 5，當讀寫位址信號輸入至比較器1 6 暫存器1 5所儲存之錯誤資訊輸入至比較器 將上述錯誤資訊及讀寫位址做比對，若兩者 主記憶區11中所欲讀取之位址已經失效，在 之單元或位元線指壞為例，因此藉由行/列 j 用行區1 2取代主§己憶區1 1中發生錯誤之位元 利進行資料讀寫之動作。在此，上述主記憶 區1 2及資訊區1 3為非揮發記憶體，當失去電 相關資料。 了減少面積及電路複雜性，可將資訊區1 3與 _ 置在一起，並共用同樣的位元線以及周邊電j _ j 可以提南電路之集積度，但由於資訊區13與 | 罔同樣的位元線，而儲存於資訊區13之錯誤I 記憶區11之位元線而傳送至讀取電路1 4，若 壞，則錯誤資訊將無法順利及正確的傳送至 然因此而無法與輸入至比較器之1 6之讀寫位 ’更遑論爾後之以備用行區1 2置換主記憶區 的動作。故若為了要減少記憶裝置之面積及 將資訊區1 3與主記憶區11設置在一起並共用 以及周邊電路，將會發生因為讀取電路14無 區11之錯誤資訊而無法對有瑕疵之記憶裝置 作’導致產品之良率大幅降低。 ，為了解決上述問題，本發明主要目的在於 裝置’將資訊區及主記憶區設置在一起而共 五、發明說明（3) ^相同之位TL線及周邊電路，藉以達到減少 的，並以錯誤矯正編碼ECC (err〇]r⑶厂u 積的目 處理儲存於資訊區之錯誤資訊。葬 C〇dlng ) ‘：所共用之位元線或其單元損€，仍可以Ecc°的方主記 使得正確之錯誤資訊得以藉由暫二:方式橋 °。與外部輸入之讀寫位址信號作比較，最後根c較 而以=行區取代主記憶區中錯誤的位元i比較結果 為獲致上述之目的，本發 括：-記憶體，4有 、 5己憶衣置’包 訊區，上述資訊區係用以迎一備兩記憶區，及—資 之主記憶區錯誤資訊：=錯誤校正編碼方式所處理 用以讀取包括上述：記；=二輕接於上述記憶體， 碼電路，搞接於上述讀取電二、；：m 一錯誤校正 貨訊以錯誤校正解碼程 將上述主記憶區錯誤 一暫存器，耦接於上、+、。二為圮憶區錯誤位址資訊； 記憶區錯誤位址資訊u二鍈扠^碼電路，用以暫存上述主 上述主記憶區錯誤位址次比車又=，用以比較一讀寫位址及 憶區錯誤位址資訊相貝士汛趴：上述讀寫位址與上述主記 碼器，耦接於上述比=i翰出—致能信號；及一位址解 用記憶區置換上琉&仓。根據上述致能信號而以上述備 、<5買罵位址。 圖式之簡單說明： 為使本發明之上述 下文特舉一較佳者☆二的、特徵和優點能更明顯易懂， “列，並配合所附圖式，作詳細說明如 591670 五、發明說明（4) 下： 圖示說明： 第1圖係顯示傳統記憶裝置之結構圖。 第2圖係顯示根據本發明實施例所述之結構圖。 符號說明： 11〜主記憶區 i 2〜備用行區 1 3〜資訊區 1 4〜讀取電路 1 5〜發性暫存器 1 6〜比較器 17〜行/列解碼器 2 1〜主記憶區 22〜備用記憶區 23〜資訊區 24〜讀取電路 25〜錯誤校正碼電路 26〜暫存器 2 7〜比較器 28〜行/列解碼器 實施例： 參閱第2圖，第2圖係顯示根據本發明實施例所述之結$ 5 pages C503-5812TW · pid 591670 I V. Description of the invention (2) | When transmitting to pinch, it will be volatile 16. Comparator 16 coincides, which means that I uses bit 7C and I decoder 17 to prepare I line, so that it can be stored in parallel zone 1 and reserve power. However, the main memory zone 11 is set as a circuit. Although this! The main § self-remembered area 11 enables the information to be read by the main bit line loss comparator 16 at this time, and the current bit signal is compared with the 11 bit line circuit complexity and the same bit line method is read In view of this, the main memory is repaired. A memory register 15 is provided. When the read / write address signal is input to the comparator 16, the error information stored in the register 15 is input to the comparator. The above error information and The read and write addresses are compared. If the address to be read in the main memory area 11 of the two has become invalid, the cell or bit line is pointed as an example. Therefore, the row area 1 2 is used for row / column j. It replaces the bit digit error occurred in the main § self-memory area 11 to read and write data. Here, the above-mentioned main memory area 12 and information area 13 are non-volatile memory, and when power loss related data is lost. In order to reduce the area and the complexity of the circuit, the information area 13 and _ can be placed together and share the same bit line and peripheral electrical j _ j can increase the integration degree of the South circuit, but because the information area 13 and | 罔 are the same The bit line stored in the error area I of the information area 13 and the bit line stored in the memory area 11 is transmitted to the reading circuit 1 4; if it is broken, the error information will not be transmitted smoothly and correctly. The read / write bit 16 of the comparator 16 is not to mention the operation of replacing the main memory area with the spare row area 12 thereafter. Therefore, in order to reduce the area of the memory device and set the information area 13 and the main memory area 11 together and share and peripheral circuits, it will happen that the faulty memory cannot be stored because the reading circuit 14 has no area 11 error information. The operation of the device causes the yield of the product to be greatly reduced. In order to solve the above problems, the main purpose of the present invention is to install the information area and the main memory area together. A total of five, description of the invention (3) ^ the same bit TL line and peripheral circuits, so as to achieve a reduction and error Correction code ECC (err0) rCD factory u product error information stored in the information area. Funeral C0dlng): The shared bit line or its unit is damaged, can still be made by Ecc ° The correct error information can be bridged by the second method. Compared with the externally input read and write address signals, the final root c is compared with the = row area instead of the wrong bit i in the main memory area. The comparison result is to achieve the above purpose, this post includes:-Memory, 4 Yes, 5 Jiyi Yizhi 'Baoxun area, the above information area is used to welcome one memory area and two memory areas, and-the main memory area of the error information: = error correction encoding method is used to read including the above: note; = Secondly, it is connected to the above memory and code circuit, and it is connected to the above-mentioned reading. Second, m: Error correction The cargo message uses the error correction decoding process to connect the above main memory area to a temporary register, which is connected to the above, + . The second is the memory address error address information; the memory area error address information u two-pronged ^ code circuit is used to temporarily store the main address of the above main memory area error address next to the car and =, to compare a read and write bit Address and memory area error address information: The above-mentioned read-write address and the above-mentioned master coder are coupled to the above-mentioned ratio = i-hanout-enable signal; and an address solution is replaced with a memory area Lau & Warehouse. According to the enabling signal, the above-mentioned preparation < 5 is used to buy the address. Brief description of the drawings: In order to make the features and advantages of the above-mentioned one of the present invention more obvious and understandable, "column, and in conjunction with the drawings, make a detailed description such as 591670 V. Invention Explanation (4) Below: Illustration: Figure 1 shows the structure of a traditional memory device. Figure 2 shows the structure according to the embodiment of the present invention. Symbol description: 11 ~ main memory area i 2 ~ spare Row area 1 3 ~ Information area 1 4 ~ Reading circuit 1 5 ~ Generic register 16 ~ Comparator 17 ~ Row / column decoder 2 1 ~ Main memory area 22 ~ Spare memory area 23 ~ Information area 24 ~ Reading circuit 25 ~ error correction code circuit 26 ~ register 2 7 ~ comparator 28 ~ row / column decoder embodiment: Please refer to FIG. 2, which shows the structure according to the embodiment of the present invention.
0503-5812TW-ptd 第8頁 591670 五、發明說明（5) b 構圖。如第2圖所示，根據本發明實施例包括以下結構·· έ己憶體，具有主記憶區2 1，備用記憶區2 2及資訊區 23 °當記憶體製作完成後，藉由儀器測試而取得主記憶區 2 1之錯誤資訊，也就是主記憶區2 1中具有缺陷之位址，益 以的編碼方式將之儲存於資訊區23，藉由對於每個資 "斗、；加入E C C編瑪及增加備用位元（s p a r e — b丨t )的方式 而達，所儲存資料之可靠度。備用記憶區2 2，用以取代主 圮憶，21中具有缺陷之位址，在此備用記憶區22主要是以 備用=為例，用以取代主記憶區2 1中損壞的位元線。 。貝取電路24，耦接於上述記憶體，用以讀取上 憶區21、備用記憶區22及資訊區2 ; 記憶區21錯誤資訊之資料。 Μ疋有關主 錯块校正碼電路25，耦接於讀取電路24，用以 於貝汛區23之主記憶區2 j錯誤資 、儲存 Γ ΡΤΓ、絲成达丄 日成貝也以錯决才父正解碼程庠 (ECC )解碼為主記憶區錯誤位址資訊。 亨斤 暫存器26，耦接於上述錯誤校正 主記憶區錯誤位址資訊。扁+ ^ ^电路U用以暫存 哭 a么& 在此’暫存器26為揮發性智左 為，當糸、统電源關閉時，其内部所暫】 在，* -旦系統電源開啟時，暫=:枓即不復存 正碼電路25之±記憶區錯誤位址P暫#來至錯誤校 比較器2 7，用以比較外部 料之讀寫位址及主記憶、區21之㈣=表存取位址之資 與主記憶區錯誤位址資訊相同時，、此日士貝T，當讀寫位址 中將要存取之位址已損壞，在此以位-二代表主記憶區21 位70線上之單元或位元 591670 此比較器2 7輸出代表比對結果為相同之致 五、發明說明（6) 線損壞為例，因 能信號。 行/列解碼器28，耦接於比較器27，其根據致能信號 而以備用記憶區22置換上述讀寫位址，藉此以順利進行: 料讀寫之動作。 貝 ,藉由上述實施例的設計，當設計者為了減少單元面積 的目的而將資訊區及主記憶區設置在—起並共用相同之位 二線及周邊電$，即使主記憶區的位元線損壞，由於先前 編碼ECC (error C0rrecting coding)處理 j :: 區之錯誤資訊’因此’仍然可以藉由ECC解碼 :式：：誤育訊矯正回來，並不會因為主記憶區的 知壞而W成修補資訊以及錯誤位址資訊:冓 正確之條補資邙以乃辑戈而·'次 、 谷失^ ’使得 比較器與外部輸入之讀寫位址信 較，=子；”至 結果而以備用行區取代主記憶區中二最J根據比較 資料存取的動作。#此一來，；摅6^ 完成了 誤育訊而進行以備用區取代的動作/ + ，士纪憶區錯 良率。 ’大幅的提高了產品之 本發明雖以較佳實施例揭露 本發明的範圍，任何熟習此項技蓺t，ί其並非用以限定 精神和範圍内，當可做些許的更二者，在不脫離本發明之 保護範圍當視後附之申請專利：與潤飾，因此本發明之0503-5812TW-ptd Page 8 591670 V. Description of Invention (5) b. As shown in FIG. 2, the embodiment according to the present invention includes the following structure: The memory body has a main memory area 21, a spare memory area 22, and an information area 23 °. After the memory is completed, it is tested by an instrument. Then, the error information of the main memory area 21 is obtained, that is, the defective address in the main memory area 21 is stored in the information area 23 in an encoding manner. By adding ECC coding and adding spare bits (spare — b 丨 t) are achieved by the reliability of the stored data. The spare memory area 22 is used to replace the defective address in the main memory 21. Here, the spare memory area 22 mainly uses spare = as an example to replace the damaged bit line in the main memory area 21. . The fetch circuit 24 is coupled to the above-mentioned memory, and is used to read the data of the upper memory area 21, the spare memory area 22 and the information area 2; the memory area 21 contains error information. Μ 错 The main error block correction code circuit 25 is coupled to the read circuit 24, and is used in the main memory area 2 of the Beixun area 23 to store error data, store Γ ΡΤΓ, Si Chengda and Nicheng Chengbei. The father is decoding ECC (ECC) to decode the wrong address information in the main memory area. The huge register 26 is coupled to the error correction information of the main memory area. Flat + ^ ^ Circuit U is used to temporarily store crying & Here, the register 26 is volatile and intelligent. When the power of the system is turned off, its internal contents are temporarily] In, *-once the system power is on Temporary =: that is, the memory address of the positive code circuit 25 + the error address P temporarily # is not restored to the error comparator 2 7 to compare the read / write address of the external material with the main memory, the area 21 ㈣ = When the information of the table access address is the same as the error address information of the main memory area, the current day Shibei T, when the address to be accessed in the read and write address is damaged, here the bit-two represents the main Unit or bit 591670 on line 21 of memory area 591670 The output of this comparator 2 7 indicates that the comparison result is the same. V. Description of the invention (6) The line is damaged as an example. The row / column decoder 28 is coupled to the comparator 27, and replaces the above-mentioned read-write address with the spare memory area 22 according to the enable signal, thereby smoothly performing the operation of reading and writing the material. With the design of the above embodiment, when the designer sets the information area and the main memory area together for the purpose of reducing the unit area, and shares the same second line and peripheral electricity, even if the bits of the main memory area The line is damaged, because the previous error ECC (error C0rrecting coding) processed the error information of the j :: area, so it can still be decoded by the ECC: type :: misinformation is corrected, and it will not be caused by the bad knowledge of the main memory area. W into repair information and incorrect address information: 冓 the correct article replenishment 邙 is a series of 而 and 次 times, valley miss ^ 'makes the comparator and external input read and write address comparison, = child; "to the result And the spare line area replaces the action of the second most J access according to the comparison data in the main memory area. # 此 来 ，， 摅 6 ^ Completed the misinformation and replaced the spare area. / +, Shiji memory area The yield is wrong. 'Although the invention of the product has been greatly improved, although the scope of the present invention is disclosed in a preferred embodiment, anyone familiar with this technique is not intended to limit the spirit and scope, and it can be done a little bit more. Both without departing from the protection of the present invention When the enclosed patent view the attachment: and variations of the present invention therefore
Τ月开』靶圍所界定者為準。"T Yuekai" as defined by the target circle shall prevail.