589661 經濟部智慧財產局員工消費合作社印製 A7 ___B7五、發明説明（1 ) 本發明係關於一種以丘克拉斯基法（Czochralski氏法 ，以下簡稱為”CZ法”）養成之矽晶圓，更詳細而言，偽關 於提供下列用途之矽晶圓：諸如DRAM (動態隨機存取記億 體）等作為LSI裝置，閃現記億體，FRAM (鐵電隨機存取 記億體）等之記億裝置：CCD (電荷耦合裝置）；及主要為 微處理器之邏輯裝置。 一般上在製造各種矽裝置時，普遍僳採用由CZ方法從 石英坩堝中之矽熔體内提拉出矽單結晶晶塊之方式製成之 CZ矽晶圓。 在該CZ矽晶圓之中，從石英坩堝中洗提出之過量氧原 子像出現在矽單結晶晶塊之格子間，而該高濃度之格子間 氯原子將導致諸如從矽晶圓中析出氧氣，有損半導體積成 電路之栅氧化層薄膜，及增加P-η匯接洩漏電流。於是， 在CZ矽晶圓之主面上形成半導體積成電路時，藉由降低矽 晶圓之氧濃度而使矽晶圓表面近處之氧析出量減少。 然而，習知在CZ矽晶圓中，原子空隙之聚結將導致結 晶體内産生空穴缺陷（D缺陷），而矽晶圓表面出現該缺陷 將形成所謂”C0P(結晶起源粒子）”之凹坑。該COP僳一種 具有深底之蝕刻坑，僳在RCA洗淨過程中以SC-1液清洗時 被激光粒子計數器當作粒子計算之結晶體所造成。包括該 COP在内在矽晶圔表面形成氧化物薄膜將有損其電子特性 ，包括時間相關介電故障（TDDB)特性，零時間介電故障（ TZDB),及栅氧化物完整特性（以下簡稱為”G0I”）；既使在 矽晶圓表面近處之氧析出之濃度很低。此外，在矽晶圓表 -4- (請七閎讀背面之、注意事填· 填寫本頁) .裝· 訂 k 本紙張尺度適用中.國國家標準（CNS ) A4g ( 2!0X297公釐） 589661 A7 _B7____ 五、發明說明（2 ) (請先閱讀背面之注意事項再填寫本頁) 面存在之COP將致使裝置之配線程序産生不同階段，而此 不同階段將造成斷線而減低産品之生産率。再者，習知COP 存在下，表面凹坑將産生分離氧化物薄膜之缺陷，導致裝 置之隔離失敗。 為了改良上述缺點，習知可在CZ晶圓表面上形成晶膜 層而取得之外延片。有別於CZ晶圓，該晶膜層在成長過程 中不會捕集氧原子。此外，在外延片中，經當出現在CZ晶 圓中之内生缺陷將會減少，而COP係被晶膜層所被覆，故 諸如COP等之凹坑將從晶膜層表面中排斥出來。再者，晶 膜層表面經過熱氧化作用而取得之栅氧化物薄膜比由CZ晶 圓表面經過熱氧化作用而取得者更為可靠，因此促成GO I 特徵之改良。 經濟部智慧財產局員工消費合作社印製 然而，顯而易知，雖然在CZ矽晶圓上形成之晶膜層具 有較少之内生缺陷及氧沉積，例如該晶膜層具有沿襲之晶 格内原子排列缺陷及所諝”低阜（mound) ”之突起部，因此 比COP對裝置所引起損壞性更為嚴重。另一方面，在CZ矽 晶圓上形成晶膜層時，必需在介於950 ¾至1100¾之溫度 範圍内進行數十分鐘之氫退火處理，藉以預先去除CZ矽晶 圓表面上之天然之氧化物。然而，此項處理作業將導致CZ 矽晶圓之内生缺陷之分解及消失，同時亦限制氧沉積，使 CZ矽晶圓本身之吸氣能力受損。 沒有形成晶膜層時，前述在CZ矽晶圓上産生之空穴缺 陷將出現在一般取決於結晶之提拉條件而發生之”氧化引 發性晶格内原子排列缺陷（以下簡稱為”〇SF”）”之環狀生成 • -5- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 589661 A7 B7 五、發明說明（3 ) 領域。於是，具有直徑減小之OSF環之結晶體近來比較普 遍被採用，藉以降低空穴缺陷之生成領域與整個矽晶圓之 比率。利用此種方法，在大幅度減低提拉速度之下，可作 成一種不含空穴缺陷之低速提拉結晶體。 然而，對具有直徑減小之OSF環之矽晶圓之GO I特性 及P-rr匯接洩漏電流特性之詳細研究發現，G0I特性不僅 在0SF璟内之處造成損壞，同時亦在0SF璟外造成損壞， 而P-η匯接洩漏電流特性亦將損壤在0SF璟上，使0SF環 内部及外部無法呈現均勻數值。此外，低速提拉結晶體之 空穴缺陷可獲摒除，但在該種結晶體上會産生錯位璟，有 損P-η匯接洩漏電流。 因此本發明之一目的在於提供一種與純粹晶膜層製成 之矽晶圓相比較之下具備半導體裝置之高性能，高産率及 特徽均勻等優點之矽晶圓，同時無損矽晶圓之吸氣性能。 為達至上述目的，本發明首先著手於一種不含空孔燒 結塊及格子間燒結塊之矽晶圓；其中當晶圓表面形成厚度 為5至25nm之氧化物薄膜及通過該氧化物薄膜施加lOMV/cm 之DC電壓為時100秒時，該矽晶圓之氧化物薄膜之缺陷密 度為每平方公分為0.1個/(：1112或以下，其中該矽晶圓之平 面内分散度為當Ρ-η匯接部份像形成於矽晶圓表面上時， 在p-ri匯接部份之Ρ-η匯接面積為lmin2或以上之P-η匯接 區上之P-η匯接洩漏電流之20%或以下。 其次，本發明之著手於一種不含空孔燒結塊及格子間 燒結塊之矽晶圓；其中當晶圓表面形成厚度為5至25n m之 -6- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) .裝 !!·訂---------·_ 經濟部智慧財產局員工消費合作社印製 589661 A7 _ B7_ 五、發明說明（4 ) 請 先 閱 讀 背 之 注589661 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 ___B7 V. Description of the Invention (1) The present invention relates to a silicon wafer developed by the Czochralski method (hereinafter referred to as "CZ method"). In more detail, it is about silicon wafers that provide the following uses: DRAM (Dynamic Random Access Memory) as LSI devices, flash memory, FRAM (Ferroelectric Random Access Memory), etc. Million devices: CCD (Charge Coupled Device); and logic devices mainly microprocessors. Generally, when manufacturing various silicon devices, CZ silicon wafers made by pulling the silicon single crystal ingot from the silicon melt in the quartz crucible by the CZ method are generally used. In this CZ silicon wafer, the image of excess oxygen atoms eluted from the quartz crucible appears between the cells of the silicon single crystal block, and the high concentration of chlorine atoms between the cells will cause, for example, the precipitation of oxygen from the silicon wafer. , Which can damage the gate oxide film of the semiconductor integrated circuit, and increase the P-η junction leakage current. Therefore, when a semiconductor integrated circuit is formed on the main surface of a CZ silicon wafer, the oxygen concentration near the surface of the silicon wafer is reduced by reducing the oxygen concentration of the silicon wafer. However, it is known that in CZ silicon wafers, the agglomeration of atomic voids will cause hole defects (D defects) in the crystal, and the appearance of such defects on the silicon wafer surface will form the so-called "C0P (crystal origin particles)" depression pit. The COP is an etch pit with a deep bottom, which is caused by a laser particle counter as a crystal when it is cleaned with SC-1 solution during RCA cleaning. The formation of oxide films on the surface of silicon wafers including this COP will damage its electronic characteristics, including time-dependent dielectric failure (TDDB) characteristics, zero-time dielectric failure (TZDB), and complete characteristics of gate oxides (hereinafter referred to as "G0I"); even if the concentration of oxygen precipitation near the surface of the silicon wafer is very low. In addition, in the silicon wafer form -4- (please read the notes on the back, fill in this page, fill in this page). Binding and ordering the paper size is applicable. National Standard (CNS) A4g (2! 0X297 mm ) 589661 A7 _B7____ 5. Description of the invention (2) (Please read the precautions on the back before filling this page) The existing COP will cause different stages of the device's wiring process, and this different stage will cause disconnection and reduce the product's productivity. Furthermore, in the presence of the conventional COP, the surface pits will cause defects in the separation oxide film, which will cause the isolation failure of the device. In order to improve the above disadvantages, it is conventionally known that epitaxial wafers can be obtained by forming a crystal film layer on the surface of a CZ wafer. Unlike CZ wafers, this crystal film layer does not trap oxygen atoms during growth. In addition, in epitaxial wafers, endogenous defects that appear in the CZ crystal circle will be reduced, and COP is covered by the crystal film layer, so pits such as COP will be repelled from the surface of the crystal film layer. Furthermore, the gate oxide film obtained by thermal oxidation on the surface of the crystal film layer is more reliable than the one obtained by thermal oxidation on the surface of the CZ crystal circle, which has contributed to the improvement of GO I characteristics. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. However, it is obvious that although the crystal film layer formed on the CZ silicon wafer has fewer endogenous defects and oxygen deposition, for example, the crystal film layer has a inherited lattice Defects in the arrangement of the internal atoms and the protruding portions of the “mound” are more severe than the damage caused by the COP to the device. On the other hand, when forming a crystal film layer on a CZ silicon wafer, it is necessary to perform a hydrogen annealing treatment in a temperature range of 950 ¾ to 1100¾ for tens of minutes, so as to remove the natural oxidation on the surface of the CZ silicon wafer in advance. Thing. However, this processing operation will lead to the decomposition and disappearance of the endogenous defects of the CZ silicon wafer, and also limit the oxygen deposition, which will damage the gettering ability of the CZ silicon wafer itself. When the crystal film layer is not formed, the aforementioned hole defects generated on the CZ silicon wafer will appear in the "oxidation-initiated atomic array defect (hereinafter referred to as" 〇SF ") which generally depends on the pulling conditions of the crystal. ”)” Ring generation • -5- This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 589661 A7 B7 V. Field of invention description (3). As a result, crystals with OSF rings with reduced diameters have recently been more commonly used, thereby reducing the ratio of the generation area of hole defects to the entire silicon wafer. With this method, a low-speed pulling crystal without void defects can be produced while the pulling speed is greatly reduced. However, a detailed study of the GO I characteristics and P-rr junction leakage current characteristics of a silicon wafer with a reduced diameter OSF ring found that the G0I characteristics not only cause damage within 0SF, but also outside 0SF. It will cause damage, and the leakage current characteristic of the P-η junction will also damage the soil at 0SF 璟, so that the internal and external of the 0SF ring cannot show a uniform value. In addition, the hole defects of the low-speed pulling crystal can be eliminated, but dislocations will be generated in the crystal, which will damage the P-η junction leakage current. Therefore, it is an object of the present invention to provide a silicon wafer which has the advantages of high performance, high yield, and uniformity of a semiconductor device compared with a silicon wafer made of a pure crystal film layer, and a non-destructive silicon wafer. Its suction performance. In order to achieve the above-mentioned object, the present invention first focuses on a silicon wafer without void sintered blocks and inter-lattice sintered blocks; wherein when an oxide film having a thickness of 5 to 25 nm is formed on the wafer surface and applied through the oxide film When the DC voltage of lOMV / cm is 100 seconds, the defect density of the oxide film of the silicon wafer is 0.1 per square centimeter / (: 1112 or less, where the in-plane dispersion of the silicon wafer is equivalent to P When the -η junction part is formed on the surface of the silicon wafer, the P-η junction leak on the P-η junction area where the P-η junction area of the p-ri junction is lmin2 or more 20% or less of the electric current. Second, the present invention works on a silicon wafer without void sintered blocks and inter-grid sintered blocks; wherein when the surface of the wafer forms a thickness of 5 to 25 nm -6-this paper size Applicable to China National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling out this page). Install !! · Order --------- · _ Intellectual Property of the Ministry of Economic Affairs Printed by the Bureau ’s Consumer Cooperatives 589661 A7 _ B7_ V. Description of Invention (4) Please read the back note first
氧化物薄膜及通過該氧化物薄膜施加lOMV/cm之DC電壓為 時100秒時，該矽晶圓之氧化物薄膜之缺陷密度為每平方 公分為0.1個/cm2或以下，其中該矽晶圓之平面内分散度 為以下兩種方法中之20%或以下：即以光電導衰減法取得 之重組壽命；及以M0S電容器構成之MOS C-t法測出之生 産壽命。 訂 其中，用以測定矽裝置特性之矽因素之基本特性係GO I 特性及ί>-η匯接洩漏電流特性。當氧化物薄膜之缺陷密度 超逾0.1 H/cm2時，或當ρ-η匯接洩漏電流之平面内分散 度超過在Ρ-η匯接部份面積之lmro2,或重組壽命及生産壽 命之平面内分散度超逾20¾時，將無法取得上述特性。氧 化物薄膜之缺陷密度最好在Ο.ΟδΗ/cffl2以下，而p-n匯接 洩漏電流之平面内分散度超過在P-η匯接部份面積之lmia2 ,或重組壽命及生産壽命之平面内分散度最好傺在10¾以 下。 峰 根據本發明著手之上述第一及第二方式製成之矽晶圓 可符合上述特性，故可確保各項半導體裝置具備高度可靠 性。此外，不含該晶膜層將可促成吸氣性能之保留。 經濟部智慧財產局員工消費合作社印製 首先將說明空孔燒結塊及格子間燒結塊。當利用CZ方 法從熱區堝爐之矽熔體中提拉出矽單結晶晶塊時，在矽單 結晶體上出現之缺陷一般包括點缺陷及燒結塊（三向度缺 陷）。點缺陷偽分成兩種類型，即空孔點缺陷及格子間矽 點缺陷。空孔點缺陷係在一矽原子從矽結晶格之正常位置 中略去之類型。該空孔將導致空孔點缺陷。同時，在非晶 一Ί 一 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 589661 A7 B7 五、發明說明（5 ) 格點（格子間位址）上出現之矽原子將導致格子間矽點缺陷。 再者，點缺陷一般係形成於矽溶體（溶融矽）與晶塊 (固體矽）之間之介面上。然而，當晶塊被拉上時，曽經為 介面之部份開始冷卻。在冷卻過程中，空孔點缺陷或格子 間矽點缺陷將彼此合併而分別形成空孔燒結塊或格子間燒 結塊。換言之，燒結塊傜由點缺陷合併而形成之三向度結 構體。 除了前述之COP之外，空孔燒結塊包括所謂” LSTD (激 光散射斷層照相缺陷）”或”FPD (流動形態缺陷）”等之缺陷， 同時格子間燒結塊包括所諝ML/D (大/錯位）燒結塊”或”錯 .位燒結塊”之缺陷。LSTD係具有與矽不同之反射指數之來 源，並在紅外線照射至矽單結晶時可産生散射光。此外， FPD偽呈現獨待流動形態之軌跡之來源，卽利用Secco蝕 刻劑對矽晶圓進行30分鐘之化學蝕刻時，出現在由晶塊切 Η而成之矽晶圖上之形態。 本發明之矽晶圓係根據CZ方法由熱區鍋爐内之矽熔體 中提拉出晶塊而製成，其中係依照Voronkov氏理論之預定 提拉速度，及利用晶塊切Η而成。該晶塊之預定提拉速度 (請先閱讀背面之注意事項再填寫本頁) 裝 ——訂---------AW.. 經濟部智慧財產局員工消費合作社印製 空純結 止為燒 防成間 以將子 足圓格 至晶及 低矽塊 及之結 , 成燒 成製孔 形：1C 空 之切含 塊塊不 結晶但 UtMl 燒種陷 間該缺 子由點 格。有 止成具 防形 ， 以之圓 足塊晶 至結矽 高燒之 應孔淨 塊 少而 較 rf5— , 成度 促速 而拉 例提 比之 G 携 πν 曰ΗΒ 制像 控 V 以中 用其 係 , 論長 理成 氏之 OV塊 nk晶 ΓΟ度 VO純 述高 前之 陷 缺 (CN 準 標 家 國 國 中 用 適 度 尺 張 紙 本 « 公 97 2 X 10 (2 規 589661 Α7 Β7 五、發明說明（6 ) G傺介於晶塊與矽熔體在熱區結構之介面之溫度梯度。如 第1圖所示，該理論圖示作為V/G比例之函數之空孔密度 及格子間矽密度，並闡明在矽晶圓中出現之空孔/格子間 混合物偽由V/G比例所取決。更詳細而言，當v/G比例超 過一臨界點時將形成空孔領域晶塊，而V/G比例低於該臨 界點時則形成格子間矽領域晶塊。 用以取得本發明之矽晶圓之預定提拉速度傺取決於該 提拉速度與溫度梯度之比例（V/G)係超過第一臨界比例 ((V/G)i)以防止格子間燒結，同時低於第二臨界比例（（V/ G)2)以限制空孔燒結至晶塊中比之空孔優勢領域，其中該 晶塊傜從處在熱區鍋爐内之矽熔體中提拉而出。 此項提拉速度偽根據Voronkov氏理論模擬而测出，諸 如憑經驗沿著軸向將供參考之晶塊進行切Η ,及憑經驗將 供參考之晶塊切片成矽晶圓，或上述方式之組合。由模擬 後之軸向切Η及切Η矽晶圓之確定而予以測出，然後再重 覆模擬作業。從多種預定範圍之提拉速度中測定，並成長 多種供參考之晶塊。如第2圖所示，模擬用之提拉速度係 經過調整至諸如1.2iam/分鐘（a)之較高提拉速度，諸如 0.5mm/分鐘（c)之較低提拉速度，然後再為0.5mm/分鐘（d) 之高提拉速度。前述較低提拉速度為0.4mm/分鐘或以下， 而提拉速度（b)及（d)最好偽作成線性。 以不同速度提拉之多個參考用晶塊像分別進行軸向切 Η。根據軸向切Η ,矽晶圓之確認，及模擬結果之相互關 偽測得最適之V/G比例，然後再測出最適之提拉速度，並 -9- 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事^|^填寫本頁) 丨裝 . 經濟部智慧財產局員工消費合作社印製 589661 A7 B7 五、發明說明（7 ) 依此製成晶塊。實際之提拉速度傜取決於諸如預期晶塊之 直徑，所使用之特定熱區鍋爐，及矽熔體之品質等多項參 數而不在其限。 第3圖顯示利用模擬作業與經驗技術之組合長成長度 為100cm及直徑為200mm之晶塊之提拉速度。其中係使用 由 Mitsubishi Material Silicon Co·, Ltd.之 IKUN0 工 廠製成之编號為Q41之熱區鍋爐，根據CZ方法製成。 第4圖顯示遞減提拉速率以連續降低V/G比例，然後 再增加提拉速度以提高V/G比例之方式取得之晶塊之斷面 圖。在第4圖中，符號[V], [I]及[P]分別僳代表空孔 優勢領域，格子間優勢領域及不含空孔燒結塊與格子間燒 結塊之完美領域。如圖所示，軸向位置Pi及h之中心包含 空孔優勢領域。位置P 3及P 4則包括格子間矽優勢璟及中央 完美領域。另外，軸向位置P2及P5僳完全完美領域，因該 位置不包括中央空孔優勢領域及周邊格子間矽優勢領域。 如第4圖所示，矽晶圓ih及W6對應於中央包含空孔優 勢領域之位置P i及P S。矽晶圓W 3及W 4包括格子間矽優勢環 及中央完美領域。另外，矽晶圓及^偽完全完美領域， 不包含中央空孔優勢領域及周邊格子間矽優勢領域。矽晶 圓^及W5偽由經過設定之提拉速度以製成如第5圖所示之 完全完美領域之晶塊經過切片而成。第6圖傺該矽晶圓之 平面圖。第7圖顯示以另一種提拉速度長成之晶塊製成之 矽晶圓^及I以供參考用。第8圖係該矽晶圓之平面圖。 如第8圖所示，在中央空孔優勢領域與周邊完美領域之間 ^紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） (請先閱讀背面之注意事項再填寫本頁) 裝 I ^---訂---- 經濟部智慧財產局員工消費合作社印製 589661 A7 B7__ 五、發明說明（8 ) 形成OSF環。本發明之砂晶圓#屬砂晶圓W2及Ws。 本發明之矽晶圓完全由完美領域加上進一步控制氧濃 度，將所取得者經過搭接，切角及鏡磨矽晶圓而構成。 本發明中用以測定氧化物薄膜之缺陷密度之測量方法 係先進行矽晶圓之RCA洗淨以去除矽晶圓表面之天然氧化 物，粒子及金屬雜質，然後利用高溫氧化作用在矽晶圓表 面上形成5至25ηπι厚度之氧化物薄膜。整個矽晶圓前側面 依照設計分成50或更多片斷，以化學蒸氣澱積法（CVD)在 矽晶圓前側面之氧化物薄膜之各點上形成具有聚矽之電極 體，再去除背面之氧化物薄膜，在各電極與背面之間施予 100秒之10MV/cia之DC電壓。通電後以相同方式施加電壓 ,根據通過各電極之電流量撿査各點之氧化物薄膜之受損 性之存在與否，藉以計算相對於點總數之受損點數之缺陷 密度。 再者，本發明中用以測量P - η匯接洩漏電流之測量步 驟傺以下列方式進行：首先按照前述用以測量氧化物薄膜 之缺陷密度之類似方式進行Ρ-型矽晶圓之RCA洗淨作業。 繼之，如第9圖所示，利用濕氣化作用在矽晶圓1 〇之前側 面形成現場氧化物薄膜11 ,然後將該氧化物薄膜11設計成 擴散窗。然後擴散磷以取得η層面12,再在η +層面12之區 域形成接觸孔。此外，利用真空噴鍍法將A 1 (1 % S i )層澱積 在此面積即可形成一電極13,同時在電極13周圍形成一護 璟電極15,而在背面之氧化物薄膜最終將被去除。在n♦層 1 2與矽晶圓前側面之間施加0 V至2 0 V之逆向偏壓，同時在 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) --裝 • n n 1 9Γ i_l n 1% 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 589661 A7 B7______ 五、發明說明（9 ) 護環電極15施加-20V之偏壓。利用電流錶測出所通過之電 流量。第9圖顯示單一電極13作為簡化說明用。實際上整 個矽晶圓前側面僳割分成50個以上之片斷，在各相對點部 位形成電極，並測出各點之洩漏電流量。從所有點取得之 洩漏電流量卽可取得矽晶圓之面内分散度。· 目前，應用於實際裝置上之P-n匯接偽用於利用L0C0S (矽局部氧化作用）結構及硼植入法之元素分離作業。然而 最好僳施加負護環偏壓以限制P-型表面逆向作用以進行測 量作業作為結晶評估，因該偏壓過程較為簡單及不採用可 能污染該離子植入作用之程序。 另外，本發明中用以測定重組壽命之測量步驟僳依據 標準光導衰變（a -PCD)法反射徼波而測出少數光植入載體 之重組，並由衰變之時間偽數中取得重組壽命。再者，本 發明中用以測定生産壽命之測量步驟像形成M0S電容器， 施加電壓至電容器後進行Zerbst分析時間變化之C-t特性。 [實施例] 以下將說明本發明之實施例及比較例。 〈實施例1> 由第5圖所示之晶塊經過磨光及削角後予以切Η而成 第6圖所示之單結晶矽晶圓（第4圖所示之晶圓W2)，再經 過鏡面拋光製成二片不含空孔燒結塊及格子間燒結塊之晶 圓。各該單結晶矽晶圓係8时長，p -型摻硼之（1〇〇)定向 ，並具有低於1 , 15 X 101 8/cra3 (以舊式ASTM計）之較低之氧 濃度。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---------^--------^-------- (請先閱讀背面之注意事項再填寫本頁) 589661 經濟部智慧財產局員工消費合作社印製 A7 _B7___ 五、發明說明（10 ) 〈比較例1 > 作為比較用途，由第7圖所示之晶塊經過磨光及削角 後予以切Η而成第8圖所示之單結晶矽晶圓（第4圖所示 之晶圓h),再經過鏡面拋光製成二Η各具有〇SF環，中央 空孔優勢領域，及周邊完美領域之晶圓。與實施例1類似 各該單結晶矽晶圓傜8吋長，Ρ-型摻硼之（1〇〇)定向，並 具有低於1.15Χ 1018/cm3之較低之氯濃度。 〈比較測試及評估〉 U)氧化物薄膜及電極之形成 首先，其中一個實施例1及比較例1之單結晶矽晶圓 僳以 SC-1 洗滌液（ΝΗ4〇Η:Η2〇2:Η2〇 = 1:1:5)洗滌，再以 SC -2洗滌液（HCl:H2〇2:H2〇 = l:l:5)洗滌。繼之，在下列標 準條件下於各該晶圓之前側面形成氧化物薄膜。即經過洗 淨之各單結晶矽晶圓在900 °C溫度下經過高溫氣化而在晶 圓前側表面形成厚度為9nm之氧化物薄膜。此外，在下列 標準條件下於氧化物薄膜上形成電極。即以CVD方法在640 ΐ：溫度下，矽烷（SiH4)經過72分鐘之熱分解作用，在氧化 物薄膜上生成厚度約為500nm之聚烷薄膜。在聚烷薄膜上 澱積磷醒氯後，在濕氧圍氛之1 000 °C下進行60分鐘之熱分 解作用。然後以光刻蝕法形成面積為20mm2之電極圖騰。 (b )氧化物薄膜缺陷密度之測量 首先將lOMV/cm之電壓應力施加於氧化物薄膜，再以 相同電壓再次施加後檢視損壞之M0S電容器數目。當電流 密度到達100 a A/c in2時，氧化物薄膜之損毀被視同電介質 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝 tr---------Μ0Ί. 589661 A7 B7__ 五、發明說明（11 ) (請先閱讀背面之注意事項再填寫本頁) 失效。此項測量作業係針對晶圓整値表面之1 8 1個點進行 。第10 U)圖顯示實施例1之氧化物薄膜缺陷之平面内分 佈情形，而第10(b)圖顯示比較例1之氧化物薄膜缺陷之 平面内分佈情形。完全塗黑部份代表介電質失效部份。 (c) p-γι匯接部之形成 首先，剩餘之前述單結晶矽晶圓偽以SC-1洗滌液 (ΝΗ4〇Η:Η2〇2··Η2〇 = 1:1:5)洗滌，再以 SC-2 洗滌液（HC1: Η2〇2:Η2〇 = 1:1:5)洗滌。繼之，於1100Τ：溫度下經過110 分鐘之濕氧化作用於各該晶圓之前側面形成厚度為600nm 之氧化物薄膜。然後此氧化物薄膜經過光刻蝕法予以設計 形成一擴散窗，使用磷醯氯（P0C13)之固相擴散形成n +層 面。磷擴散之條件傺，在900 1C溫度下經過20分鐘蝕刻去 除PSG (矽酸磷玻璃），然後在該磷在ιοοου溫度下經過60 分鐘之熱擴散。η +層面之擴散深度為2^ια,濃度為1Χ1013 /cm3。形成接觸孔後，以噴鍍方式將含有1.5%Si之Α1予以 澱積。經過電極圖騰後，在450 10含有N2圍氛下進行退火 處理，最終去除背面之氧化物薄膜。選擇1.8niinXl.8inm之 設計樣式形成匯接部。 經濟部智慧財產局員工消費合作社印製 (d) p-n匯接洩漏電流之均勻性之測量 在各晶圓之P-η匯接部施加電壓，以HP4140(pA)錶 測量該匯接部之洩漏電流。其時，利用HP4141B (電流-電 壓源）在護環上施加偏壓以限制P-型之表面逆向作用。採 用-20V作為負護環偏壓。此項測量作業係在晶圓整個表面 之272個點上進行。第11(a)圖顯不實施例1之p-n匯接 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 589661 A7 B7 五、發明說明（12 ) 經濟部智慧財產局員工消費合作社印製 洩漏電流之平面内分佈情形，而第11 ( b )圖顯示比較例1 之P - η匯接洩漏電流之平面内分佈情形。 (e)評估 由第1 0圖顯而易知，實施例1之晶圓上沒有發現氧化 物薄膜缺陷，而在比較例1之晶圓之零時介電質失效特性 之平面内分佈之OSF環内部（181點之其中25點）發現氧化 物薄膜缺陷。 此外，如第11圖所示，關於p - η匯接洩漏電流之測量 方面，在比較例1之晶圓之OSF璟上之電流洩漏量較高， 即此晶圓之總數272個點中，有3値點（圖中黑色部份）之 洩電量高達ΙΟρΑ以上，1値點（圖中灰色部份）之洩電量介 於6至7pA, 34個點（圖中”X”部份）之洩電量介於5至6pA, 218個點（圖中留空部份）之洩電量為4至5pA,及16個點 (圖中”/”部份）之洩電量為2至3pA。結果發現平面内分散 度為50%。相比之下，實施例1之晶圓所有點之洩電量（圖 中留空部份）為4至5pA ,平面内分散度僅為3¾，故提供優 異之平面内分佈性。 如上所述，本發明之晶圓之G0I特徵之完整性及p-n 匯接洩漏電流之均勻性可獲保證。因此在DRAM,可減少氣 化物薄膜可靠性方面及更新失序方面之缺陷。此外，在諸 如CCD等成像器材，可解決諸如清晰度缺陷方面之問題。 於是，與純粹晶膜層製成之矽晶圓相比較之下，本發明之 砂晶圓具備半導體裝置之高性能，高産率及特徵均勻等優 點。再者，該矽晶圓之另一項優在於其吸氣性能與純粹晶 -15 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） (請先閱讀背面之注意事項再填寫本頁) __ -裝 ----訂---- 經濟部智慧財產局員工消費合作社印製 589661 A7 B7 _ 五、發明說明（13 ) 膜層製成之矽晶圓者並没有不同之劣化作用。 圖式之簡單説明 第1圖顯示本發明之一實施例中，根據Voronkov氏理 論，空孔優勢晶塊像形成於臨界點之V/G比率或以上，而 格子間矽優勢晶塊僳形成於臨界點之V/G比率或以下。 第2圖像顯示用以測定預期提拉速度簡況之提拉速度 變化之特性圖。 第3圖僳顯示本發明之空孔優勢矽晶圓及完美矽晶圓 之成長之提拉速度之示意特性圖。 第4圖偽顯示本發明之一參考晶塊之空孔優勢領域， 格子間矽優勢領域及完美領域之以斷層X-光照相法取得之 示意圖。 第5圖偽本發明之不含空孔燒結塊及格子間燒結塊之 晶塊之透視圖。 第6圖偽第5圔之矽晶圓之平面圖。 第7圖顯示在中心具有空孔優勢領域之晶塊，及在空 孔優勢領域及周圍部份之間具有無缺陷領域之矽晶圓。 第8圖係第7圖之矽晶圓之平面圖。 第9圖傺用以測定p-n匯接洩漏電流之構成圖。 第10 U)圖係本發明之第一實施例之氧化物薄膜缺陷 之面内分佈，而第1 0 ( b)圖像比較例1之氧化物薄膜缺陷 之面内分佈。 第11(a)圖像第1實施例之P-n匯接洩漏電流之面内 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） —·—.—U裝--------訂--------- (請先閱讀背面之注意事項再填寫本頁) 589661 A7 __B7 五、發明說明（14 ) 分佈，而第11 (b)圖偽比較例1之p - η匯接洩漏電流之面 内分佈。 經濟部智慧財產局員工消費合作社印製 -17- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）When the oxide film and a DC voltage of lOMV / cm applied through the oxide film are 100 seconds, the defect density of the oxide film of the silicon wafer is 0.1 per cm 2 / cm 2 or less, in which the silicon wafer The in-plane dispersion is 20% or less of the following two methods: the recombination life obtained by the photoconductive attenuation method; and the production life measured by the MOS Ct method composed of M0S capacitors. Among them, the basic characteristics of the silicon factor used to determine the characteristics of the silicon device are the GO I characteristics and the > -η junction leakage current characteristics. When the defect density of the oxide film exceeds 0.1 H / cm2, or when the dispersion of the leakage current in the ρ-η junction exceeds the lmro2 in the area of the P-η junction, or the plane of the reorganization life and production life When the internal dispersion exceeds 20¾, the above characteristics cannot be obtained. The defect density of the oxide film is preferably below 0.0δΗ / cffl2, and the in-plane dispersion of the pn junction leakage current exceeds the lmia2 in the area of the P-η junction portion, or the in-plane dispersion of the reorganization life and production life. The best degree is below 10¾. The silicon wafers manufactured according to the first and second methods described above according to the present invention can meet the above-mentioned characteristics, so that various semiconductor devices can be highly reliable. In addition, the absence of the crystal film layer can promote retention of gettering performance. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs First, the sintered block with holes and the sintered block between cells will be explained. When the silicon single crystal ingot is pulled out of the silicon melt in the hot zone furnace by the CZ method, the defects appearing on the silicon single crystal generally include point defects and sintered blocks (three-dimensional defects). Point defects are categorized into two types, namely hole point defects and inter-lattice silicon point defects. Hole point defects are of the type where a silicon atom is omitted from the normal position of the silicon crystal lattice. The voids will cause void point defects. At the same time, the silicon atom on the grid of one amorphous and one paper applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 589661 A7 B7 V. Description of the invention (5) Silicon atoms appearing on the grid points (inter-lattice addresses) Will cause silicon dot defects between grids. Furthermore, point defects are generally formed on the interface between a silicon solution (fused silicon) and a crystal block (solid silicon). However, when the ingot is pulled up, the part of the interface that begins to cool begins to cool. During the cooling process, void point defects or inter-lattice silicon point defects will merge with each other to form void sintered blocks or inter-lattice sintered blocks, respectively. In other words, the sintered block is a three-dimensional structure formed by the combination of point defects. In addition to the aforementioned COP, the void sintered block includes defects such as "LSTD (Laser Scattering Tomography Defect)" or "FPD (Flow Form Defect)", and the inter-lattice sintered block includes the ML / D (large / Dislocation) Defects of "sintered block" or "displaced sintered block". LSTD has a source of reflection index different from that of silicon, and can generate scattered light when infrared rays are irradiated to the silicon single crystal. In addition, FPD pseudo-renders only to flow The origin of the morphological trajectory, when the silicon wafer is chemically etched with a Secco etchant for 30 minutes, it appears on the silicon crystal pattern cut from the crystal block. The silicon wafer of the present invention is based on the CZ method It is made by pulling out crystal ingots from the silicon melt in the hot zone boiler, which is a predetermined pulling speed according to Voronkov's theory, and cut by using the crystal ingots. The predetermined pulling speed of the crystal ingots (please (Please read the precautions on the back before filling this page.) Binding——Order --------- AW .. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, the pure and pure junctions are closed to prevent fires to prevent children Round lattice to crystals and low silicon blocks and junctions, sintered Hole shape: 1C empty cuts containing blocks that do not crystallize, but the gap between UtMl burnt seeds should be latticed. There is only a shape-proof, so round foot crystals to the high temperature of silicon should have fewer net holes and more rf5—, the speed promotes the speed, and the G of the pull example mentions πν (Ην), the image control V, which is used in the system, on the OV block of Changlicheng ’s nk crystal, Γ °, and VO. The quasi-standard home country and the middle school use a moderate ruled paper «public 97 2 X 10 (2 gauge 589661 Α7 B7) V. Description of the invention (6) G 傺 is a temperature gradient between the interface between the crystal block and the silicon melt in the hot zone structure. As shown in Figure 1, the theory illustrates the pore density and the inter-lattice silicon density as a function of the V / G ratio, and clarifies that the void / inter-lattice mixture appearing in the silicon wafer is pseudo-indicated by V / G ratio It depends. In more detail, when the v / G ratio exceeds a critical point, crystal blocks in the pore area will be formed, and when the V / G ratio is lower than the critical point, crystal blocks in the inter-lattice silicon field will be formed. The predetermined pulling speed of the silicon wafer depends on the ratio of the pulling speed to the temperature gradient (V / G) exceeding the first The critical ratio ((V / G) i) to prevent inter-lattice sintering, and at the same time lower than the second critical ratio ((V / G) 2) to limit the sintering of voids to the dominant area of void ratio in the crystal block, where the crystals The lump is pulled out of the silicon melt in the hot zone boiler. This pull speed is pseudo-measured according to Voronkov's theoretical simulation, such as cutting the lump for reference along the axis based on experience. Based on experience, slice the reference crystal block into a silicon wafer, or a combination of the above methods. Measure it from the axial cut and silicon cut after the simulation, and then repeat the simulation operation. Measure from a variety of pull speeds in a predetermined range, and grow a variety of crystal blocks for reference. As shown in Figure 2, the pulling speed for simulation is adjusted to a higher pulling speed such as 1.2iam / minute (a), a lower pulling speed such as 0.5mm / minute (c), and then High pull speed of 0.5mm / min (d). The aforementioned lower pulling speed is 0.4 mm / min or less, and the pulling speeds (b) and (d) are preferably pseudo-linear. A plurality of reference crystal blocks pulled at different speeds were cut axially. Measure the optimal V / G ratio according to the axial cut, the confirmation of the silicon wafer, and the correlation between the simulation results, and then measure the optimal pulling speed, and -9- This paper size applies Chinese national standards (CNS) A4 specification (210 X 297 mm) (Please read the notes on the back ^ | ^ Fill this page first) 丨 Installation. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 589661 A7 B7 V. Description of Invention (7) Thus, a crystal block was produced. The actual pulling speed depends on a number of parameters such as the expected diameter of the ingot, the specific hot zone boiler used, and the quality of the silicon melt. Fig. 3 shows the pulling speed of a crystal block having a length of 100 cm and a diameter of 200 mm by using a combination of simulation work and empirical technology. Among them, the hot zone boiler No. Q41 made by IKUN0 factory of Mitsubishi Material Silicon Co., Ltd. is used, and it is made according to CZ method. Figure 4 shows a cross-section of a crystal block obtained by decreasing the pulling rate to continuously reduce the V / G ratio, and then increasing the pulling speed to increase the V / G ratio. In Figure 4, the symbols [V], [I], and [P] respectively represent the area of superiority of voids, the area of superiority between lattices, and the perfect area without sintered blocks and voids. As shown in the figure, the centers of the axial positions Pi and h include the dominant area of voids. Positions P 3 and P 4 include the inter-lattice silicon advantage and the central perfect area. In addition, the axial positions P2 and P5 are completely perfect fields, because this position does not include the center hole advantage field and the peripheral inter-cell silicon advantage field. As shown in Fig. 4, the silicon wafers ih and W6 correspond to the positions P i and P S in the center of the hole containing the advantageous area. The silicon wafers W 3 and W 4 include the inter-lattice silicon dominance ring and the central perfect area. In addition, the silicon wafer and the pseudo-perfect area are not perfect, and do not include the central hole advantage area and the peripheral inter-silicon advantage area. The silicon circle and the W5 pseudo are formed by slicing a crystal block with a perfect pulling speed set to a completely perfect area as shown in FIG. 5. Figure 6: A plan view of the silicon wafer. Figure 7 shows a silicon wafer ^ and I made from a crystal block grown at another pulling speed for reference. Figure 8 is a plan view of the silicon wafer. As shown in Figure 8, between the central hollow area of superiority and the surrounding perfect area ^ The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 public love) (Please read the precautions on the back before filling this page ) Equipment I ^ --- Order ---- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 589661 A7 B7__ 5. Description of Invention (8) Form an OSF ring. The sand wafer # of the present invention is a sand wafer W2 and Ws. The silicon wafer of the present invention is completely composed of a perfect field and further controlling the oxygen concentration, and the obtained wafer is overlapped, cut, and mirror-polished. The measurement method for determining the defect density of an oxide film in the present invention is to perform RCA cleaning of a silicon wafer to remove natural oxides, particles, and metal impurities on the surface of the silicon wafer, and then use high temperature oxidation on the silicon wafer An oxide film with a thickness of 5 to 25 ηm is formed on the surface. The entire front side of the silicon wafer is divided into 50 or more pieces according to the design. Chemical vapor deposition (CVD) is used to form an electrode body with polysilicon at each point of the oxide film on the front side of the silicon wafer. For the oxide thin film, a DC voltage of 10 MV / cia was applied between each electrode and the back surface for 100 seconds. After the voltage is applied in the same manner, the presence or absence of damage to the oxide film at each point is checked according to the amount of current passing through each electrode, so as to calculate the defect density of the damaged points relative to the total number of points. Furthermore, the measurement steps for measuring the P-η junction leakage current in the present invention are performed in the following manner: First, the RCA washing of the P-type silicon wafer is performed in a similar manner to the defect density measurement of the oxide film described above. Net work. Next, as shown in FIG. 9, a field oxide film 11 is formed on the front side of the silicon wafer 10 by moisture vaporization, and the oxide film 11 is designed as a diffusion window. Phosphorus is then diffused to obtain η plane 12, and contact holes are formed in the region of η + plane 12. In addition, an electrode 13 is formed by depositing an A 1 (1% S i) layer on this area by a vacuum sputtering method. At the same time, a guard electrode 15 is formed around the electrode 13, and an oxide film on the back surface is finally formed. Was removed. A reverse bias voltage of 0 V to 20 V is applied between the n1 layer 12 and the front side of the silicon wafer. At the same time, the Chinese National Standard (CNS) A4 specification (210 X 297 mm) is applied to this paper size (please first (Please read the notes on the back and fill in this page) --Installation • nn 1 9Γ i_l n 1% Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 589661 A7 B7______ 5. Description of the invention (9 ) The guard ring electrode 15 is biased at -20V. Use an ammeter to measure the current flow. FIG. 9 shows the single electrode 13 as a simplified explanation. In fact, the entire front side of the silicon wafer was castrated into more than 50 pieces, electrodes were formed at opposite points, and the amount of leakage current at each point was measured. The amount of leakage current obtained from all points can obtain the in-plane dispersion of the silicon wafer. · At present, the P-n junction pseudo-device used in actual devices is used for element separation operation using L0C0S (Silicon Local Oxidation) structure and boron implantation method. However, it is best to apply a negative guard ring bias to limit the P-type surface inverse action for the measurement operation as a crystallization assessment because the bias process is simpler and does not use procedures that may contaminate the ion implantation. In addition, the measurement steps used in the present invention to measure the recombination lifetime are based on the standard light guide decay (a-PCD) method to reflect the chirp wave to measure the recombination of a few light-implanted carriers, and the recombination lifetime is obtained from the pseudo-number of the decay time. Furthermore, the measurement steps used to determine the production life in the present invention are like forming a MOS capacitor, and performing Zerbst analysis on the time-varying C-t characteristics after applying a voltage to the capacitor. [Examples] Examples and comparative examples of the present invention will be described below. <Example 1> A single crystal silicon wafer (wafer W2 shown in FIG. 4) shown in FIG. 6 was cut from the crystal block shown in FIG. 5 after being polished and chamfered, and then cut. After mirror polishing, two wafers without void sintered blocks and inter-lattice sintered blocks were prepared. Each of the single crystal silicon wafers was 8 hours long, (100) orientation of the p-type boron doped, and had a lower oxygen concentration than 1, 15 X 101 8 / cra3 (based on old ASTM). This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) --------- ^ -------- ^ -------- (Please read first Note on the back, please fill out this page again) 589661 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 _B7___ V. Invention Description (10) <Comparative Example 1> For comparison, the crystal block shown in Figure 7 is ground After light and chamfering, it was cut into a single crystal silicon wafer as shown in Figure 8 (wafer h as shown in Figure 4), and then mirror-polished to form two silicon wafers each with a 0SF ring and a central hollow hole. Wafers in areas of strength and peripheral perfection. Similar to Example 1, each of the single crystalline silicon wafers was 8 inches long, (100) oriented with P-type boron doped, and had a lower chlorine concentration than 1.15 × 1018 / cm3. <Comparative test and evaluation> U) Formation of oxide film and electrode First, one of the single crystal silicon wafers of Example 1 and Comparative Example 1 was washed with SC-1 washing solution (NΗ4〇Η: Η2〇2: Η2〇). = 1: 1: 5), and then washed with SC-2 washing solution (HCl: H2O2: H2O = 1: 1: 5). Next, an oxide film is formed on the front side of each of the wafers under the following standard conditions. That is, each of the cleaned single crystal silicon wafers was vaporized at a high temperature at 900 ° C to form an oxide film with a thickness of 9 nm on the front surface of the wafer. In addition, an electrode was formed on the oxide film under the following standard conditions. That is, by CVD method at 640 ΐ: temperature, silane (SiH4) was thermally decomposed for 72 minutes, and a polyalkane film having a thickness of about 500 nm was formed on the oxide film. After depositing phosphorous chloride on the polyalkane film, thermal decomposition was performed at 1,000 ° C in a wet oxygen atmosphere for 60 minutes. Then an electrode totem with an area of 20 mm 2 is formed by photolithography. (b) Measurement of oxide film defect density Firstly, a voltage stress of lOMV / cm was applied to the oxide film, and then the same voltage was applied again to inspect the number of damaged MOS capacitors. When the current density reaches 100 a A / c in2, the damage of the oxide film is regarded as a dielectric. The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling This page) Install tr --------- Μ0Ί. 589661 A7 B7__ V. The description of the invention (11) (Please read the precautions on the back before filling this page) is invalid. This measurement is performed on 181 points on the surface of the wafer. Figure 10 U) shows the in-plane distribution of the oxide film defects of Example 1, and Figure 10 (b) shows the in-plane distribution of the oxide film defects of Comparative Example 1. The fully blacked-out part represents the dielectric failure part. (c) Formation of p-gamma junction First, the remaining single crystal silicon wafers described above are pseudo-washed with SC-1 washing solution (NΗ4〇Η: Η2〇2 ·· Η2〇 = 1: 1: 5), and then Wash with SC-2 washing solution (HC1: Η202: 220 = 1: 1: 5). Then, at 1100T: 110 minutes of wet oxidation, an oxide film with a thickness of 600 nm was formed on the front side of each wafer. This oxide thin film is then designed by photolithography to form a diffusion window, and solid phase diffusion using phosphorophosphonium chloride (P0C13) is used to form the n + layer surface. Conditions for phosphorus diffusion: PSG (phosphorus silicate glass) was removed by etching at 900 1C for 20 minutes, and then the phosphorus was thermally diffused at ιοοου for 60 minutes. The diffusion depth at the η + plane is 2 ^ ια, and the concentration is 1 × 1013 / cm3. After the contact holes were formed, A1 containing 1.5% Si was deposited by sputtering. After the electrode totem, annealing is performed under the atmosphere of 450-10 containing N2, and finally the oxide film on the back is removed. Choose 1.8niinXl.8inm design style to form the junction. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs (d) Measurement of the uniformity of the pn junction leakage current. A voltage was applied to the P-η junction of each wafer, and the leakage of the junction was measured with the HP4140 (pA) meter. Current. At this time, HP4141B (current-voltage source) was used to apply a bias to the guard ring to limit the P-type surface reverse action. Use -20V as the negative guard ring bias. This measurement was performed at 272 points on the entire surface of the wafer. Figure 11 (a) shows the pn tandem of Example 1. The paper size of this paper applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 589661 A7 B7 V. Description of the invention (12) Intellectual Property Bureau of the Ministry of Economic Affairs The employee consumer cooperative printed the in-plane distribution of leakage current, and Figure 11 (b) shows the in-plane distribution of P-η junction leakage current in Comparative Example 1. (e) Assessed from Figure 10, it is easy to know that the oxide film defect was not found on the wafer of Example 1, and the OSF of the dielectric failure characteristics of the wafer of Comparative Example 1 was distributed in the plane at zero time. Oxide film defects were found inside the ring (25 of 181 points). In addition, as shown in FIG. 11, regarding the measurement of the p-η junction leakage current, the amount of current leakage on the OSF 璟 of the wafer of Comparative Example 1 is high, that is, among the total of 272 points of this wafer, There are 3 points (black part in the figure) with a leakage current of more than 10ρΑ, and 1 point (the gray part in the figure) has a leakage power between 6 and 7 pA, 34 points (the "X" part in the figure). The leakage current is between 5 and 6 pA, the leakage current of 218 points (the blank part in the figure) is 4 to 5 pA, and the leakage power of 16 points (the "/" part in the figure) is 2 to 3 pA. It was found that the in-plane dispersion was 50%. In comparison, the leakage currents at all points of the wafer in Example 1 (the blank portions in the figure) are 4 to 5 pA, and the in-plane dispersion is only 3¾, so it provides excellent in-plane distribution. As described above, the integrity of the G0I characteristics and the uniformity of the p-n junction leakage current of the wafer of the present invention can be guaranteed. Therefore, in the DRAM, the defects in the reliability of the gas film and the update disorder can be reduced. In addition, in imaging equipment such as a CCD, problems such as sharpness defects can be solved. Therefore, compared with a silicon wafer made of a pure crystal film layer, the sand wafer of the present invention has the advantages of high performance, high yield, and uniform characteristics of a semiconductor device. In addition, another advantage of this silicon wafer is its gettering performance and pure crystal -15-This paper size applies to China National Standard (CNS) A4 specification (210 X 297 public love) (Please read the precautions on the back first (Fill in this page again) __-Mounting-ordering-printed by the Intellectual Property Bureau of the Ministry of Economic Affairs's consumer cooperative 589661 A7 B7 _ V. Description of the invention (13) There is no difference between silicon wafers made of film Deteriorating effect. Brief Description of the Drawings Figure 1 shows that in one embodiment of the present invention, according to Voronkov's theory, a dominant hole crystal block image is formed at a critical point V / G ratio or higher, and an interlattice silicon block crystal is formed at V / G ratio at or below the critical point. The second image shows a characteristic diagram for measuring the change in the pulling speed for the profile of the expected pulling speed. FIG. 3 僳 shows a schematic characteristic drawing of the pulling speed of the growth of the hole-dominant silicon wafer and the perfect silicon wafer of the present invention. FIG. 4 is a schematic diagram obtained by tomography of one of the present invention's reference holes, the interstitial silicon superiority area, and the perfect area, which are obtained by tomography. Fig. 5 is a perspective view of a crystal block containing no void sintered block and inter-lattice sintered block of the present invention. FIG. 6 is a plan view of a pseudo 5th silicon wafer. Figure 7 shows a silicon wafer with a hole-dominant area in the center, and a silicon wafer with a defect-free area between the hole-dominant area and the surrounding part. Figure 8 is a plan view of the silicon wafer of Figure 7. Fig. 9 is a structural diagram for measuring p-n junction leakage current. Figure 10 U) shows the in-plane distribution of the oxide film defects of the first embodiment of the present invention, and Figure 10 (b) shows the in-plane distribution of the oxide film defects of Comparative Example 1. The 11th (a) image of the first embodiment of the Pn tandem leakage current in the plane of this paper is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) — · —.— U pack ---- ---- Order --------- (Please read the precautions on the back before filling this page) 589661 A7 __B7 V. Description of the invention (14) Distribution, and Figure 11 (b) False Comparative Example 1 The in-plane distribution of p-η junction leakage current. Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -17- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)