574724 五、發明説明（1 ) 發明背景 發明領域 本發明有關一種利用防衛環（Guard Ring)連接技術以達 成功率半導體元件積體電路化之方法及裝置，且更特別地 有關一種利用防衛環（Guard Ring)連接技術來連接功率場 效電晶體元件的汲極與其相關連之電晶體元件的接點而使 該等電晶體元件能單一晶片積體電路化之方法及其裝置。 相關技術說明 目前，諸如功率MOSFET(金屬氧化物半導體場效電晶體） 之功率半導體元件大多爲分離式之複數個單一的電晶體元 件所構成，並無法有效地完成積體電路化，因此，對於曰 趨複雜的電路，必須在電路板上外加許多其他的電子組件 ，致使體積變大且製造成本及工時均大幅地增加。 也就是說，習知之功率半導體元件在封裝完成之後必須 在電路板上焊接其他相關連之電子組件，因而造成電路的 體積大增。近年來，如第1圖中所示之習知技術功率半導 體元件積體電路化裝置，半導體製造業者將功率半導.體元 件11之晶片與相關連之諸如用於控制之小信號電晶體元件 12之晶片黏著於同一引線架13之上而以焊線15接合於兩 晶片間以製作於同一 1C(積體電路）封裝（package)內，且亦 有業者利用多晶片模組（MCM)，例如覆晶之方式（未圖示）， 透過晶粒接合（Die Bonding)方式將功率電晶體元件與控制 電晶體元件予以打線（亦稱，焊線）連接並封裝於同一 1C封 裝內，雖在外觀上係一單一之1C，但內部仍然可分爲多顆. 574724 五、發明説明（2 ) 晶片，亦即，多個ic，而非實際之單晶片積體電路，也就 是說，雖上述習知技術之方式可減少體積，但封裝時仍須 具有在兩晶片間之1 5焊線（bonding wire)，由於打線品質不 易控制，將使成本提高，且將導致封裝後之功率半導體元 件之導通電阻値 RDS(on)會比單一顆裸晶時更高。 因此，如何使功率半導體元件及相關連之元件製作於同 一晶片之上，使呈完全的積體電路化而減少體積及去除焊 線，以便降低生產成本以及提高功率半導體元件之性能， 即成爲本項技術之業者所追求的目標。 熟知地，如國內之電力電子技術雙月刊2000.2之第59， 60頁中所專題硏討之”高壓元件Temination之模擬與設計 中’’所述，略以，一個元件的大小不可能是無限大的，它必 有終止的時候，而一個元件終止地方的結構必定與其內部 不相同，所以其特性也會不一樣。對於一個大面積的P-N 接面（N基板）而言，其內部是兩種平行的半導體，可看成是 兩個平行板電極，在周圍的地方，由於接面的終止，所以P 形半導體會形成一個圓弧，使得曲率增加。由電學得知， 曲率增加（曲率半徑減小）會使電場增強（電場oc電荷/半徑2) ，所以元件周圍地方的電場會變得比內部大，因此崩潰電 壓（breakdown volt age)比較低。爲了要降低此處的電場， 我們要加上一些額外的結構，而這些結構就稱爲終止 (Termination)，終止（Termination)最常見的應用是在高 壓元件上，一般最常用的終止（Termination)結構是浮動 環（floating ring)與場氧化物板（field plate)的混合結構 冬 574724 五、發明説明（3 ) 。此結構最大的優點是結構簡單，不增加額外的製程步 驟及光罩，同時也不需特殊的製程技術，只需用到簡單的 PN接面，是一般高壓元件較常使用的方式。所謂浮動環 (floating ring)，亦稱爲防衛環（Guard Ring)，就是在兀件周 圍圍上一圈或數圈的阱（well)，但是這些阱並不接任何的電 源，所以稱爲浮動（floating)，惟因這些環是浮動的，所以 其上的電壓會受到外加電壓的影響。在IGBT(絕緣閘極雙 極性電晶體）中，這些電壓就是VE(—般是0V，加在主接 面（main junction)或（內阴^(internal well)上）與 VC(—般是最 大耐壓，加在晶圓的底部）。靠內阱越近的環，受VE的影 響越大，所以電壓較低。相對的，越遠離內阱的環，受VE 影響越小，受VC影響越大，其電壓越高。所以電壓會由內 阱向外漸漸升高。最後到達VC。如第2圖中之多個防衛環 之終止結構中之所示，其中參考符號1 6爲主接面，亦即， 內阱，以及參考符號1 7爲場氧化物板，亦即，場氧化物， 而參考符號1 8，1 9及20則分別表示第一防衛環，第二防 衛環，及第三防衛環（其中防衛環之數目並未受限於上述3 個）。如上述地，在第三防衛環處之電壓幾乎與晶圓底部， 亦即，在垂直式功率元件中之汲極處之電壓（VC)相等。 發明槪沭 因此，本發明之目的即在於揭示一種利用防衛環（Guard Ring)連接技術來連接功率場效電晶體元件的汲極與其相關 連之電晶體元件的端子而使該等電晶體元件以單一晶片來 積體電路化之方法及其裝置，使整個體積減少而特性增加。 574724 五、發明説明（4 ) 爲達成上述目的，根據本發明之一觀點，提供有一種利 用防衛環連接技術以達成功率半導體元件積體電路化之方 法，包含下列步驟： 1 ·形成一垂直式功率半導體元件及至少一電晶體元件於 一砂基板之同一晶片之上； 2.利用離子佈植技術形成複數個防衛環於該功率半導體 元件與該至少一電晶體元件之間，其中該等防衛環具有相 反極性於該垂直式功率半導體元件之基板上之汲極的摻雜 物之極性，及利用熱氧化法形成相對應且鄰接於該複數個 防衛環之複數個場氧化物層；以及 3 .利用化學氣相沈積（CVD)技術或濺鍍技術形成導電性金 屬互連跨越該複數個場氧化物層之最外側的一個場氧化物 層而電性地連接該複數個防衛環之最外側的一個防衛環與 該至少一電晶體元件之相對應接點。 根據本發明之另一觀點，提供有一種利用防衛環連接技 術以達成功率半導體元件積體電路化之裝置，包含·· 一垂直式功率半導體元件及至少一電晶體元件，形成於 一矽基板之同一晶片之上； 複數個防衛環，利用離子佈植技術形成於該功率半導體 元件與至少一電晶體元件，其中該等防衛環具有相反極性 於該垂直式功率半導體元件之基板上之汲極的摻雜物之極 性； 複數個場氧化物層，利用熱氧化法形成，相對應且鄰接 於該複數個防衛環；以及 574724 五、發明説明（5 ) 導電性金屬互連，利用化學氣相沈積（CVD)技術或濺鍍技 術形成，跨越該複數個場氧化物層之最外側的一個場氧化 物層而電性地連接該複數個防衛環之最外側的一個防衛環 與該至少一電晶體元件之相對應接點。 根據上述觀點，其中該功率半導體元件可包含垂直式功 率金屬氧化物半導體場效電晶體（MOSFET)，及絕緣閘極雙 極性電晶體（IGBT);以及其中該至少一電晶體元件係一小 信號電晶體，用於控制該功率半導體元件之開啓/關閉。 又，根據上述觀點，其中該導電性金屬互連可包含鋁， 銅或上述兩材料所組成之合金。 圖式簡單說明 本發明之上述及其他目的，特性及優點將從下文結合附 圖之詳細說明中呈更明顯，其中相同之元件，將以相同的 參考符號表示，其中 第1圖係描繪習知技術之功率半導體元件積體電路化之 裝置的示意圖； 第2圖係描繪多個防衛環之終止結構的示意圖； 第3圖係描繪根據本發明之功率半導體元件積體電路化 之裝置的示意圖；以及 第4圖係剖視圖，描繪第3圖中之該功率半導體元件積 體電路化之裝置的結構。 發明詳細說明 請參閱第3及4圖，其中第3圖係描繪根據本發明之功 率半導體元件積體電路化之裝置的示意圖，以及第4圖係 574724 五、發明説明（6 ) 描繪第3圖中之該功率半導體元件積體電路化之裝置之結 構的剖視圖。 如第3圖中所示，根據本發明，首先在一晶片4之中利 用熟知之半導體製造過程形成：一功率半導體元件1區’ 諸如垂直式功率金屬氧化物半導體場效電晶體（MOSFET)， 或絕緣閘極雙極性電晶體（IGBT)之功率半導體元件1 ;以及 至少一電晶體元件2區，其中形成至少一電晶體元件2，用 以控制該功率半導體元件1之諸如開啓/關閉之動作，也 就是說，利用傳統之半導體製造方法形成一功率元件1及 至少一電晶體元件2於一矽基板（例如矽晶圓（未圖示））之各 複數個晶片4中；然後，利用離子佈植技術形成複數個防 衛環5(Guard Ring)於該功率半導體元件1與該至少一電晶 體元件2之間，圍繞該功率半導體元件1，雖在第3圖中僅 繪製3個呈方形配置之防衛環5，但該等防衛環5之數目及 形狀並未因此受限，而可視需要予以增加/減少及變化， 其中該等防衛環係佈植枏反於該垂直式功率半導體元件1 之基板上之汲極的摻雜物之極性，以及利用熱氧化法在相 對應於且鄰接於該複數個防衛環之毗鄰處形成複數個場氧 化物層7之絕緣物；然後，利用化學氣相沈積（CVD)法或濺 鍍法形成諸如鋁，銅，或該兩金屬材料之合金之導電性金 屬互連（未圖示）跨接該複數個場氧化物層7之最外側的一個 場氧化物層而電性地連接該複數個防衛環5之最外側的一 個防衛環與該至少一電晶體元件2之相對應接點。 如上述，根據本發明，利用防衛環5之連接技術可直接 574724 五、發明説明（7 ) 地將功率半導體元件之汲極電壓連接到其他電路的接點之 上，而獲得如下述之功效： 一、 降低功率場效電晶體之電阻’因其省略晶粒接合時之 接腳引線的電阻，約可降低百分之二十至三十的電阻 値； 二、 減少積體電路之體積，若直接將功率電晶體與其相關 連之電晶體製作於同一晶片上之時，可有效減少積體電 路之體積；以及 三、 達成實際之功率元件積體電路化之結果，可有效地提 昇功率元件之附加價値。 在第4圖中，顯示根據本發明裝置之剖面結構圖，其中 爲使圖式簡明起見，僅繪製一個防衛環5，但本發明並未受 限於此。在該圖中，參考符號1表示功率半導體元件部分 ，其中汲極32，亦即，基板係顯示爲N +摻雜物，在該基板 上分別地形成有熟知之一具有N·磊晶層31，P·阱30，N +源 極28，以及多晶矽閘極29及閘極氧化物絕緣物27及諸如 BPSG(硼磷矽酸鹽玻璃）之閘極絕緣物21之垂直式功率場效 電晶體，以及一具有平面式配置之小信號控制 電晶體兀件2 ，其中參考符號9表示該小信號電晶體元件2之汲極，參 考符號29爲多晶矽閘極，27爲閘極氧化物，28爲源極及 21爲諸如BPSG，上述該功率半導體元件1及至少一小信 號電晶體元件2係以熟知之半導體製造技術形成於一矽基 板之同一晶片4之上。 574724 五、發明説明（8 ) 接著，利用離子佈植技術形成一防衛環5於該功率半導 體元件1與該至少一小信號電晶體元件2之間，以及利用 熱氧化處理形成相對應且鄰接於該防衛環之場氧化物7，其 中該防衛環5之數目爲大於1之複數個且數目將依據該功 率半導體元件1之耐壓以及場氧化物7之厚度及寬度而有 所變化，以及其中該防衛環具有相反極性於該垂直式功率 半導體元件之汲極摻雜物的極性。如本文之序言中所述， 由於防衛環5係浮動（floating)，所以其上之電壓會受到外 加電壓（VC)影響，其中愈靠近內部阱（即，第4圖中之P·阱 3 0)之防衛環5受到VC影響最小，所以電壓較低，相對地 ，越遠離內部阱之防衛環則受VC影響越大。最後，該防衛 環5之電壓會由內部阱向外地漸漸升高，最後到達VC，亦 即，到達外加於晶片底部（即，汲極32)之最大電壓。 然後，利用化學氣相沈積（CVD)技術或濺鍍技術形成諸如 鋁，銅，或其合金之導電性金屬互連6，跨越該場氧化物7 或該複數個場氧化物層之最外側的一個場氧化物而電性地 連接該防衛環5或該複數個防衛環之最外側的一個防衛環 與該至少一電晶體元件2之諸如汲極9之相對應接點，使 得該功率半導體元件1之汲極32可連接至該至少一電晶體 元件2之汲極9。 如上述，根據本發明所建構之裝置可利用防衛環（Guard Ring)5之連接技術來連接一功率場效電晶體元件1之汲極 32與其相關連之小信號控制電晶體元件2的接點（如汲極 9)，而使該等電晶體元件1，2能單一晶片積體電路化。 -10- 574724 五、發明説明（9 ) 熟習於本項技術者將理解的是，本發明並未受限於上述 說明，而是可允許不同的變化及修正。然而，本發明將以 所附錄之申請專利範圍之對的意義及範疇來加以闡釋。 符號之說明 1.. ...功率半導體元件 2.. ...小信號電晶體元件 3.. ...引線架 4.. ...晶片 5.. ...防衛環 6.. ...導電性金屬互連 ’ 7.. ...場氧化物 9•.…汲極（小信號電晶體） Π·...功率半導體元件 12. …小信號電晶體元件 13. …引線架 15.. ..焊線 16.. ..主接面 17.…場氧化物 18 —第一防衛環 19.…第二防衛環 2 0 —第三防衛環 21.. ..BPSG(硼磷矽酸鹽玻璃） 27····閘極氧化物 2 8....源極 -11- 574724 五、發明説明（1G ) 29.…多晶矽閘極 30…·Ρ1 井 3 1 —Ν嘉晶層 32....汲極（Ν +矽基板）（功率半導體元件） -12-574724 V. Description of the invention (1) Background of the invention The present invention relates to a method and a device for achieving circuitization of a power semiconductor element integrated circuit by using a guard ring connection technology, and more particularly to a method using a guard ring ( Guard ring (connection technology) method and device for connecting the drain of a power field effect transistor element and its associated transistor element so that the transistor elements can be circuitized on a single chip. Description of related technology At present, power semiconductor devices such as power MOSFETs (metal oxide semiconductor field effect transistors) are mostly composed of a plurality of separate single transistor devices and cannot effectively complete integrated circuitization. For more complicated circuits, many other electronic components must be added to the circuit board, resulting in a larger volume and a large increase in manufacturing costs and man-hours. That is to say, the conventional power semiconductor components must be soldered with other related electronic components on the circuit board after the packaging is completed, thus causing the circuit to increase in size. In recent years, as shown in FIG. 1, a conventional technology power semiconductor device integrated circuit device has been used by semiconductor manufacturers to integrate power semiconductor semiconductor chip 11 with related small signal transistor devices such as those used for control. The chip of 12 is adhered to the same lead frame 13 and is bonded between the two chips with a bonding wire 15 to make it in the same 1C (integrated circuit) package, and some companies use multi-chip modules (MCM). For example, the flip-chip method (not shown) connects the power transistor element and the control transistor element by die bonding (also known as bonding wires) and is packaged in the same 1C package. Appearance is a single 1C, but the interior can still be divided into multiple pieces. 574724 V. Description of the Invention (2) Chips, that is, multiple ICs, rather than actual single-chip integrated circuits, that is, although the above The conventional technology can reduce the volume, but the package must still have a 15 bonding wire between the two chips. Because the quality of the wire is not easy to control, it will increase the cost and lead to power semiconductors after packaging. Zhi the on-resistance RDS (on) greater than a single grain when naked. Therefore, how to make power semiconductor components and related components on the same wafer, make a complete integrated circuit, reduce the volume and remove the bonding wires, so as to reduce production costs and improve the performance of power semiconductor components, becomes the current Goals pursued by technology practitioners. As is well known, as described in the topic of "Simulation and Design of High-Voltage Components Temination" in the domestic Power Electronics Technology Bimonthly 2000.2 pages 59, 60, it is mentioned that the size of a component cannot be infinite. , It must be terminated, and the structure of a component's termination must be different from its interior, so its characteristics will also be different. For a large-area PN junction (N substrate), its interior is two parallel The semiconductor can be seen as two parallel plate electrodes. In the surrounding area, due to the termination of the junction, the P-shaped semiconductor will form an arc, which will increase the curvature. According to electrical knowledge, the curvature increases (the radius of curvature decreases) ) Will increase the electric field (electric field oc charge / radius 2), so the electric field around the element will become larger than the internal, so the breakdown volt age is lower. To reduce the electric field here, we need to add Some additional structures, and these structures are called terminations. Terminations are most commonly used in high-voltage components, and are most commonly used. Termination structure is a mixed structure of floating ring and field oxide plate. Winter 574724 V. Description of the invention (3). The biggest advantage of this structure is that the structure is simple, without additional process steps and Photomasks do not require special process technology at the same time, only simple PN junctions are used, which is a commonly used method for general high-voltage components. The so-called floating ring, also known as the Guard Ring, It is a well or wells around the element, but these wells are not connected to any power source, so they are called floating, but because these rings are floating, the voltage on them will be Affected by the applied voltage. In IGBT (Insulated Gate Bipolar Transistor), these voltages are VE (usually 0V, which is applied to the main junction or (internal well) and (internal well)) and VC (generally the maximum withstand voltage, added at the bottom of the wafer). The ring closer to the inner well is more affected by VE, so the voltage is lower. Relatively, the ring farther from the inner well is affected by VE The smaller, the more affected by VC, its voltage The higher the voltage, the higher the voltage will gradually increase from the inner well to the VC. As shown in the termination structure of the multiple defense rings in Figure 2, the reference symbol 16 is the main interface, that is, The inner well and reference symbol 17 are field oxide plates, that is, field oxide, and reference symbols 18, 19, and 20 represent the first defense ring, the second defense ring, and the third defense ring ( The number of guard rings is not limited to the above 3). As mentioned above, the voltage at the third guard ring is almost the same as the bottom of the wafer, that is, the voltage at the drain of the vertical power element (VC )equal. Therefore, the purpose of the present invention is to disclose a method for connecting the drain of a power field effect transistor element and the terminal of an associated transistor element by using a guard ring connection technology, so that the transistor elements are connected to each other. A method and a device for integrating a single chip into a circuit, reducing the overall volume and increasing the characteristics. 574724 V. Description of the invention (4) In order to achieve the above-mentioned object, according to one aspect of the present invention, a method for achieving circuitization of a power semiconductor element integrated circuit by using a guard ring connection technology is provided, including the following steps: 1. Forming a vertical Power semiconductor element and at least one transistor element on the same wafer of a sand substrate; 2. Use ion implantation technology to form a plurality of defense rings between the power semiconductor element and the at least one transistor element, where The guard ring has polarities of dopants of opposite polarity to the drain on the substrate of the vertical power semiconductor element, and a plurality of field oxide layers corresponding to and adjacent to the guard rings are formed by a thermal oxidation method; and 3. Use chemical vapor deposition (CVD) technology or sputtering technology to form a conductive metal interconnect that spans the outermost field oxide layer of the plurality of field oxide layers and electrically connects the most of the plurality of guard rings. A guard ring on the outer side corresponds to a corresponding contact point of the at least one transistor element. According to another aspect of the present invention, there is provided a device for achieving circuitization of a power semiconductor element integrated circuit using a guard ring connection technology, including a vertical power semiconductor element and at least one transistor element formed on a silicon substrate On the same wafer; a plurality of guard rings are formed on the power semiconductor element and at least one transistor element using ion implantation technology, wherein the guard rings have drain electrodes of opposite polarities on the substrate of the vertical power semiconductor element The polarity of the dopants; a plurality of field oxide layers formed by a thermal oxidation method, corresponding to and adjacent to the plurality of guard rings; and 574724 V. Description of the invention (5) Conductive metal interconnection, using a chemical vapor phase It is formed by a deposition (CVD) technique or a sputtering technique, and electrically connects an outermost guard ring of the plurality of guard rings with the at least one electrical bridge across the outermost field oxide layer of the plurality of field oxide layers. Corresponding contacts of crystal elements. According to the above viewpoint, the power semiconductor element may include a vertical power metal oxide semiconductor field effect transistor (MOSFET) and an insulated gate bipolar transistor (IGBT); and wherein the at least one transistor element is a small signal A transistor is used to control the power semiconductor element on / off. In addition, according to the above viewpoint, the conductive metal interconnect may include aluminum, copper, or an alloy composed of the two materials. The drawings briefly explain the above and other objects of the present invention. The characteristics and advantages will be more apparent from the following detailed description in conjunction with the drawings. The same elements will be represented by the same reference symbols, and the first diagram depicts the conventional art. Schematic diagram of a power semiconductor device integrated circuit technology device; Figure 2 is a schematic diagram depicting the termination structure of a plurality of defense rings; Figure 3 is a schematic diagram illustrating a power semiconductor element integrated circuit circuitization device according to the present invention; And FIG. 4 is a cross-sectional view depicting the structure of the device for circuitizing the power semiconductor element integrated body in FIG. 3. For a detailed description of the invention, please refer to Figs. 3 and 4, wherein Fig. 3 is a schematic diagram depicting a circuit device of a power semiconductor element integrated circuit according to the present invention, and Fig. 4 is 574724. 5. Description of the invention (6) depicts Fig. 3 The sectional view of the structure of the power semiconductor element integrated circuitized device. As shown in FIG. 3, according to the present invention, first, a wafer 4 is formed using a well-known semiconductor manufacturing process: a power semiconductor element 1 region such as a vertical power metal oxide semiconductor field effect transistor (MOSFET), Or insulated gate bipolar transistor (IGBT) power semiconductor element 1; and at least one transistor element 2 area, in which at least one transistor element 2 is formed to control such actions as turning on / off of the power semiconductor element 1 That is, a conventional semiconductor manufacturing method is used to form a power element 1 and at least one transistor element 2 in a plurality of wafers 4 of a silicon substrate (such as a silicon wafer (not shown)); then, using ions The implantation technology forms a plurality of Guard Rings 5 between the power semiconductor element 1 and the at least one transistor element 2 to surround the power semiconductor element 1, although only three square configurations are drawn in the third figure Defense ring 5, but the number and shape of these defense rings 5 are not limited by this, and can be increased / decreased and changed as necessary, where the defense rings are planted instead of The polarity of the dopant of the drain electrode on the substrate of the vertical power semiconductor element 1 and an insulator in which a plurality of field oxide layers 7 are formed adjacent to and adjacent to the plurality of guard rings by a thermal oxidation method ; Then, a chemical vapor deposition (CVD) method or a sputtering method is used to form a conductive metal interconnect (not shown) such as aluminum, copper, or an alloy of the two metal materials across the plurality of field oxide layers 7. A field oxide layer on the outermost side of the plurality of guard rings 5 is electrically connected to corresponding contacts of the outermost guard ring 5 and the at least one transistor element 2. As mentioned above, according to the present invention, the connection technology of the guard ring 5 can be used directly to 574724. V. Description of the invention (7) The drain voltage of the power semiconductor element is connected to the contacts of other circuits to obtain the following effects: First, reduce the resistance of the power field effect transistor 'because it omits the resistance of the pin leads when the die bonding is omitted, which can reduce the resistance by about 20% to 30%; 2. Reduce the volume of the integrated circuit. When the power transistor and its associated transistor are directly fabricated on the same wafer, the volume of the integrated circuit can be effectively reduced; and 3. The actual circuitization of the integrated circuit of the power component can effectively improve the power component. Additional price 値. In Fig. 4, a sectional structural view of the device according to the present invention is shown, in which only one guard ring 5 is drawn for the sake of brevity, but the present invention is not limited thereto. In the figure, reference numeral 1 denotes a power semiconductor element portion, in which a drain electrode 32, that is, a substrate system is shown as an N + dopant, and a well-known one having an N · epitaxial layer 31 is formed on the substrate, respectively. , P · Well 30, N + Source 28, and Polycrystalline Silicon Gate 29 and Gate Oxide Insulator 27 and Vertical Power Field Effect Transistor 21 such as BPSG (borophosphosilicate glass) gate insulator 21 And a small-signal control transistor element 2 having a planar configuration, wherein reference numeral 9 denotes the drain of the small-signal transistor element 2, reference numeral 29 is a polysilicon gate, 27 is a gate oxide, and 28 is The source and 21 are, for example, BPSG. The power semiconductor element 1 and at least one small-signal transistor element 2 are formed on the same wafer 4 of a silicon substrate using well-known semiconductor manufacturing techniques. 574724 V. Description of the invention (8) Next, a defense ring 5 is formed between the power semiconductor element 1 and the at least one small-signal transistor element 2 by using ion implantation technology, and corresponding and adjacent to each other are formed by thermal oxidation treatment. The field oxide 7 of the guard ring, wherein the number of the guard ring 5 is a plurality of more than 1 and the number will vary depending on the withstand voltage of the power semiconductor element 1 and the thickness and width of the field oxide 7, and among which The guard ring has a polarity opposite to that of a drain dopant of the vertical power semiconductor device. As described in the preface of this article, because the defense ring 5 is floating, the voltage on it will be affected by the applied voltage (VC), which is closer to the internal well (ie, P · well 3 0 in Figure 4). The guard ring 5 is the least affected by VC, so the voltage is lower. Relatively, the farther away the guard ring from the internal well is, the greater the influence of VC is. Finally, the voltage of the guard ring 5 will gradually increase from the internal well to the outside, and finally reach VC, that is, the maximum voltage applied to the bottom of the chip (ie, the drain 32). Then, a chemical vapor deposition (CVD) technique or a sputtering technique is used to form a conductive metal interconnect 6, such as aluminum, copper, or an alloy thereof, across the outermost portion of the field oxide 7 or the plurality of field oxide layers. A field oxide is electrically connected to the guard ring 5 or the outermost guard ring of the plurality of guard rings and the corresponding contact point of the at least one transistor element 2 such as the drain electrode 9 so that the power semiconductor element The drain 32 of 1 can be connected to the drain 9 of the at least one transistor element 2. As described above, the device constructed according to the present invention can use the connection technology of the Guard Ring 5 to connect the drain 32 of a power field effect transistor element 1 and the contact point of the small signal control transistor element 2 associated with it (Such as the drain electrode 9), so that these transistor elements 1, 2 can be single-chip integrated circuit. -10- 574724 V. Description of the invention (9) Those skilled in the art will understand that the present invention is not limited to the above description, but allows different changes and modifications. However, the present invention will be explained in terms of the meaning and scope of the appended patent application scope. Explanation of Symbols 1 ..... Power semiconductor components 2 ..... Small-signal transistor components 3 ..... Lead frame 4 ..... Chip 5 ..... Guard ring 6 ... .. Conductive Metal Interconnects' 7 .... Field Oxide 9 • .... Drain (Small Signal Transistor) Π ... Power Semiconductor Element 12. Small Signal Transistor Element 13. Lead Frame 15 ... Welding wire 16 ... Main interface 17. Field oxide 18 — First defense ring 19. Second defense ring 2 0 — Third defense ring 21. .. BPSG (borophosphorus Silicate glass) 27 ··· Gate oxide 2 8 .... Source-11- 574724 V. Description of the invention (1G) 29 .... Polycrystalline silicon gate 30… · P1 Well 3 1—Ν 嘉 晶Layer 32 .... Drain (N + silicon substrate) (power semiconductor element) -12-