TW544877B - Method for electroplating IC encapsulated substrate - Google Patents
Method for electroplating IC encapsulated substrate Download PDFInfo
- Publication number
- TW544877B TW544877B TW091104213A TW91104213A TW544877B TW 544877 B TW544877 B TW 544877B TW 091104213 A TW091104213 A TW 091104213A TW 91104213 A TW91104213 A TW 91104213A TW 544877 B TW544877 B TW 544877B
- Authority
- TW
- Taiwan
- Prior art keywords
- substrate
- resist
- circuit
- electroplating
- circuitry
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/243—Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0352—Differences between the conductors of different layers of a multilayer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/14—Related to the order of processing steps
- H05K2203/1476—Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
- H05K3/061—Etching masks
- H05K3/064—Photoresists
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/282—Applying non-metallic protective coatings for inhibiting the corrosion of the circuit, e.g. for preserving the solderability
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
- H05K3/427—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in metal-clad substrates
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Electroplating Methods And Accessories (AREA)
Abstract
Description
544877 修正544877 Fix
1 號 91104213 五、發明說明(1) 本發明係一種在積體電路封裝基板上製作電路 用無電鍍導線的電鍍金屬方式來製作電路線,使 ^ 全沒,有自鍍金棒切除後餘留的電鍍導線,可大為古== 基板之電路品質。 〃攸间封裝 請參照第-圖所示,-般來說,在雙面封裝電路 的型式中,常採用以導線連接雙面板或圈孔釘合雙面"· 型態,但在近年來穿孔電鍍技術發展逐漸成熟後,以 電鍍雙面的封裝基板的型態’已成為大量生產高品質 路板的主要方式。而在封裝基板丨,表層的電路製作方 然使用傳統的方式:在電路主圖上之適當位置處(如金"手 指)拉一條電鍍導線3’伸展到板外的鍍金棒4,(puting Bar),接上電極後作出電鍍電路2’ ,待電鍍電路2,势作士 畢後再予以由載斷處5,切除,此時會在封裝基板丨,^留$ 殘,的電鍍導線3’ ,此殘餘的導線亦會在電流經過時產生 熱量,亦容易引發雜訊影響電路品質,這對集積密度偏高 的封裝基板Γ來說’無疑是一大缺失,因此極待業界提出 對此因應之道(業界尚有一種無電鍍法electr〇Uss platlng又稱化學鑛法chemical deposit,係一種利用所 添力H的還原劑使金屬離子還原成金屬而況積附著在被鍍物 士 = f應,此法亦可不需電鍍導線即可形成鑛層,惟該化 = 不易控制,失敗率居高不下,且其鍍層生長速度緩 杈,目前並不適用大量生產之生產線上應用)。 本發明之首要目的係提供一封裝基板之金屬電鍍方 法利用雙面封裝基板之通孔電鍍後銅膜電性導通兩面的 _特^ j妙地利用底層之銅膜層充當鍍金棒,使封裝基板 Λ 修正 曰 魅 91104213 五、發明說明〇 :表:U不需設置電鍍導線’使其電路線不會殘留導 路品質。必要的熱量及雜訊產生,以提升封裴基板之電 層可本於發線日1之次要目的係在於本發明所電鑛之錢金(金屬) 加工推:頂面與側立面皆可覆蓋住,®而不會在後續 劣气仃蝕刻的過程中側蝕,而不致造成電路線品質低、 =配合圖式將本發明較佳實施例詳細說明如下。 a、雔睛/興第二圖所*,本發明主要之製作方法係: 出)面舖設鋼膜1 1之封裝基板i穿孔形成柱孔4(第二圖A示 修正 處(第二圖G示出)。 二圖Η所 hi餘刻後留下封裝基板1背面線路32(請參照第 I)於線路(32)部分以外的ρ认、面 焊液mux)在塗上阻劑2,並以前處理助 份报Λ仅嗜B- C , 今欢基板ί背面部分線路(3 2 )部 伤形成保護膜6(請參照第二圖1所示)。 依據上述製程即可作φ 土 P J作出封裝基板表層之無導線之電鍍 金屬路線,且此製程可伟i制 Μ餘+ h A 使其製品之電鍍金屬完美地覆蓋於 新鮮的鋼電路線之了f|彳 貝面,、側立面,能杜絕該銅電路線遭側 I虫而造成短路。 :1、上所述,當知本案所發明之積體電路封裝基板之金 屬電錢方法已具有產業利用性、進步性,符合發明專利要 件准以上所述者,僅為本發明之較佳實施例而已,並非 用來限定本發明實施之範圍。即凡依本發明申請專利範圍 戶斤做的均等變化與修飾,皆為本發明專利範圍所涵蓋。No. 1 91104213 V. Description of the invention (1) The present invention is a method of making circuit wires by using electroless metal plating on the circuit board substrate for integrated circuits to make circuit wires, so that ^ is completely absent. Electroplated wires can be as old as the circuit quality of the substrate. Please refer to the figure-for general package.-Generally speaking, in the type of double-sided package circuit, the double-sided board is connected by wires or the double-sided pin is double-circle type. However, in recent years, After the development of perforated electroplating technology has gradually matured, the form of plated double-sided packaging substrates has become the main way to mass-produce high-quality road boards. On the package substrate, the surface circuit is made using the traditional method: at a suitable position on the main circuit diagram (such as gold " finger), pull a plated wire 3 'to the gold-plated rod 4 outside the board, (puting Bar), connect the electrode to make a plated circuit 2 ', wait for the plated circuit 2, and cut it off from the load 5 after the master is finished. At this time, the plated wire 3 will be left on the package substrate. ', This residual wire will also generate heat when the current passes, and it will also easily cause noise to affect the circuit quality. This is undoubtedly a big loss for the packaging substrate Γ with a high accumulation density, so it is highly anticipated by the industry Correspondence (the industry still has an electroless plating method electr0Uss platlng, also known as chemical deposit method chemical deposit, which uses a reducing agent H added to reduce the metal ions to metal and deposits on the object to be plated = fying This method can also form a ore layer without the need for electroplated wires, but this conversion = is not easy to control, the failure rate is high, and its plating growth rate is slow, which is currently not suitable for mass production production line applications). The primary object of the present invention is to provide a metal plating method for a packaging substrate. The copper film is electrically conductive on both sides after the plating of the through holes of the double-sided packaging substrate. Specially, the bottom copper film layer is used as a gold plating rod to make the packaging substrate. Λ Correction charm 91104213 V. Description of the invention 0: Table: U does not need to be provided with electroplated wires, so that the circuit wires do not leave the quality of the conductive path. The necessary heat and noise are generated to enhance the electrical layer of the sealing substrate. The secondary purpose of this layer is on the day of the launch. The secondary purpose is to process the gold (metal) of the power mine of the present invention. It can be covered without any side etching during the subsequent process of inferior gas etching, without causing low circuit line quality. The preferred embodiment of the present invention will be described in detail with reference to the drawings. a. Eyes / Xing second picture *, the main manufacturing method of the present invention is: the packaging substrate i with steel film 1 1 on the surface is perforated to form column holes 4 (the second picture A shows the correction (the second picture G (Shown in the figure). After a few moments in the second figure, the back surface of the package substrate 1 is left with the wiring 32 (please refer to Section I) outside the wiring (32), and the surface soldering liquid mux) is coated with a resist 2 and The previous treatment reported that only BC was addicted, and the part of the circuit (3 2) on the back surface of the Jinhuan substrate was injured to form a protective film 6 (see the second figure 1). According to the above process, φ soil PJ can be used to make the electroless metal plating route of the surface of the package substrate, and this process can be made by M + + h A so that the electroplated metal of the product perfectly covers the fresh steel circuit wires. f | 彳 shell surface, side elevation can prevent the copper circuit wire from being short-circuited by side I insects. : 1. As mentioned above, when it is known that the metal electric money method of the integrated circuit package substrate invented in this case has industrial applicability and progress, and meets the requirements of the invention patent, the above is only a preferred implementation of the present invention. The examples are not intended to limit the scope of implementation of the present invention. That is, all equal changes and modifications made by the household according to the scope of patent application of the present invention are covered by the scope of patent of the present invention.
544877 _案號91104213_年月曰 修正_ 圖式簡單說明 圖式單說明: 第一圖A、B係習用封裝基板之金屬電鍍殘留導線示意圖。 第二圖A〜I係本發明之金屬電鍍方法示意圖。 習知<技術部份: 1 ’ .封裝基板 2’ .電鍍電路 3 ’ .電鍍導線 4’ .鍍金棒 5’ .截斷處 本發明部份: 1. 封裝基板 11.銅膜 1 2。電鍍銅層 2. 阻劑 3. 線路 31 ·電鍍金屬(鎳金) 3 2.線路 4. 柱孔 5. 卩立劑 6. 保護膜544877 _Case No. 91104213_ Year Month Amendment _ Brief Description of Drawings Description of Drawings: The first picture A and B are schematic diagrams of metal plating residual wires of conventional package substrates. The second figures A to I are schematic diagrams of the metal plating method of the present invention. Conventional < Technical part: 1 '. Package substrate 2'. Plating circuit 3 '. Plating wire 4'. Gold-plated rod 5 '. Cut-off part of the present invention: 1. Package substrate 11. Copper film 1 2. Electroplated copper layer 2. Resistor 3. Circuit 31 · Electroplated metal (nickel gold) 3 2. Circuit 4. Column hole 5. Erection agent 6. Protective film
第10頁Page 10
Claims (1)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW091104213A TW544877B (en) | 2002-03-04 | 2002-03-04 | Method for electroplating IC encapsulated substrate |
JP2002315472A JP2003253486A (en) | 2002-03-04 | 2002-10-30 | Metal plating method for package board of ic circuit |
US10/289,312 US20030164303A1 (en) | 2002-03-04 | 2002-11-07 | Method of metal electro-plating for IC package substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW091104213A TW544877B (en) | 2002-03-04 | 2002-03-04 | Method for electroplating IC encapsulated substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
TW544877B true TW544877B (en) | 2003-08-01 |
Family
ID=27802808
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW091104213A TW544877B (en) | 2002-03-04 | 2002-03-04 | Method for electroplating IC encapsulated substrate |
Country Status (3)
Country | Link |
---|---|
US (1) | US20030164303A1 (en) |
JP (1) | JP2003253486A (en) |
TW (1) | TW544877B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101932206B (en) * | 2009-06-25 | 2012-06-13 | 富葵精密组件(深圳)有限公司 | Fabrication method of multi-layer circuit board |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7626829B2 (en) | 2004-10-27 | 2009-12-01 | Ibiden Co., Ltd. | Multilayer printed wiring board and manufacturing method of the multilayer printed wiring board |
US7326591B2 (en) * | 2005-08-31 | 2008-02-05 | Micron Technology, Inc. | Interconnecting substrates for microelectronic dies, methods for forming vias in such substrates, and methods for packaging microelectronic devices |
SG130074A1 (en) * | 2005-09-01 | 2007-03-20 | Micron Technology Inc | Interconnecting substrates for microelectronic dies, methods for forming vias in such substrates, and methods for packaging microelectronic devices |
KR100660027B1 (en) | 2006-01-25 | 2006-12-20 | 삼성전기주식회사 | Manufacturing method of printed circuit board using electrolytic plating lead |
CN109561602B (en) * | 2017-09-27 | 2020-08-21 | 鹏鼎控股(深圳)股份有限公司 | Circuit board and manufacturing method thereof |
CN111188070A (en) * | 2020-01-22 | 2020-05-22 | 惠州中京电子科技有限公司 | Manufacturing method for electroplating nickel, silver and gold on IC packaging board |
-
2002
- 2002-03-04 TW TW091104213A patent/TW544877B/en not_active IP Right Cessation
- 2002-10-30 JP JP2002315472A patent/JP2003253486A/en active Pending
- 2002-11-07 US US10/289,312 patent/US20030164303A1/en not_active Abandoned
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101932206B (en) * | 2009-06-25 | 2012-06-13 | 富葵精密组件(深圳)有限公司 | Fabrication method of multi-layer circuit board |
Also Published As
Publication number | Publication date |
---|---|
US20030164303A1 (en) | 2003-09-04 |
JP2003253486A (en) | 2003-09-10 |
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