TW530385B - CMOS with strain-balanced structure and method of manufacturing the same - Google Patents

Abstract

A kind of method for manufacturing CMOS device having strain-balanced structure is proposed in the present invention. At first, a silicon-on-insulator (SOI) substrate is provided. Then, a silicon germanium layer is grown on the silicon layer, in which the silicon layer is in the twin-axis tensile strain condition and the silicon germanium layer is in the twin-axis compressive strain condition, so as to obtain a strain-balanced structure. After that, the second silicon layer is formed on the silicon germanium layer, in which the second silicon layer has the first thickness suitable for use in a PMOS device and has the second thickness suitable for use in an NMOS device. A patterning process is then conducted onto the substrate to define a PMOS device region and an NMOS device region. A gate insulation layer is formed on the second silicon layer. Finally, a gate electrode is formed on the gate insulation layer.

Description

530385 V. Description of the invention (1) The present invention relates to an out-of-field lightning a reduction ^ ^ t per effect transistor 'especially a n-channel element with a strained silicon layer and a CMOS (complementary) channel element Method: Metal oxide half field # Rayθ Germanium 0 method. 70 pieces of jade-rolled cattle field effect transistor) and its manufacturing As the size of the gate element is reduced, it is necessary to make the metal oxide half field effect (M0SFET) element at a low level. Under operating voltage, it is quite difficult to have high actuation current = high speed. Therefore, many people are trying to find a way to improve the performance of metal-oxide-semiconductor field-effect transistor devices. Strain-induced band structure modification is used to increase the mobility of carriers to increase the actuating current of the field effect transistor, which can improve the performance of the field effect transistor element, and this method has been applied to various elements. The silicon channel system of these devices is under the condition of biaxial tensile strain. It has been pointed out that the mobility of electrons is increased by using the Shixi channel in a biaxial tensile strain condition (K. Ismail et al., &Quot; Electron transport properties in Si / SiGe heterostructures: Measurements and device applications' Appl · Phys · Lett · 63, pp · 660, 1 993 ·), and the use of silicon germanium channels in the case of biaxial compressive strain to increase hole mobility (DK Nayak et al ·, 丨 Enhancement-mode quantum-well GeSi PM0Sn, IEEE Elect. Dev. Lett · 12, pp · 154, 1991 ·). However, a CMOS process technology combining NMOSFETs (N-type metal-oxide-semiconductor half-effect transistors) with silicon channels with biaxial tensile strain and PM0SFETs (P-type metal-oxide-semiconductor half-effect transistors) with silicon- germanium channels with biaxial compression strain It is difficult to achieve. In the manufacture of transistors, there are many ΙΜΜΙΙΙΙΗ 0503-7196TWF (N); TSMC2001-1254; ycchen.ptd page 5 530385 for the use of thick buffer layers or complex multilayer structures. · Ismail et al ·, IBM, Jul · 1 996,

Complementary metal-oxide semi conductor transistor logic using strained Si / SiGe heterostructure layers, U.S. Patent No. 553471 3 ·), these methods are not easy to integrate into traditional CMOS processes. Therefore, in order to manufacture a metal-oxide half-field-effect transistor element with high actuating current and high-speed efficiency, it is urgent to seek improvement for the above problems. In view of this, the object of the present invention is to provide a CMOS device structure with a strain-balanced structure and a method for manufacturing the same, which utilize the strain of an n-channel device having a tensile strained silicon layer and a p-channel device with a compressive strained silicon germanium layer. 'Balance structure' to improve the performance of field effect transistor devices. In order to achieve the above-mentioned object, the present invention proposes a method for manufacturing a CMOS device with a strain-balanced structure. 'First, a substrate with a stone layer (soo) on an insulating layer is provided. Second, a silicon-germanium layer is grown on the silicon layer. The Shixi layer is under the condition of biaxial tensile strain and the silicon-germanium layer θ is under the condition of biaxial compressive strain to obtain a strain balanced structure. Then, a second silicon is formed on the silicon-germanium layer. Layer, where the second silicon layer has a third thickness suitable for -PM0S devices, and-after the second thickness is suitable for _N_ devices ^, a patterning process is performed on this substrate to define a pM0s element and -N ': piece area. Furthermore,' gate insulation is formed on this second silicon layer; and finally, a gate electrode is formed on this gate insulation layer. The present invention also proposes a cm with a strain-balanced structure. The s element includes: a silicon substrate on an insulating layer; a silicon germanium 厣 L ^ ^ ^ ^ ^. & 丄 two growths on the silicon substrate on the insulating layer, where the silicon layer is in a double ! The glaze tensile strain

530385 V. Description of the invention (3) ΐίί: The germanium layer is under the condition of biaxial compressive strain 'to obtain a strained silicon screen-the second silicon layer' is grown on this silicon germanium layer 1, where this second use :: N_ No .: the thickness is suitable for the first element and the second thickness is suitable; the gate insulation layer is formed on the second silicon layer; ^ a gate electrode is formed on the gate insulation layer. Said steam application example 1 Its manufacturing method provides a cm0s element structure with a strain-balanced structure and a semi-successive method. The concept of the present invention is to apply the comparisons with different lattice constants to the interaction between the film layers in the loose state, and the semiconductor thin film layer with the Japanese straw in the loose state is under compressive strain. The semiconductor thin film layer with a small lattice constant is in a compressive strain condition: ^ and then a strain-balanced structure is formed. For example, a stacked layer structure of one, under the interaction of different lattice constants; layer = ii the relaxation of the sorrowful sorrowful interaction 'where the Shixi fault layer is under the biaxial condition and the silicon layer is under Under biaxial tensile strain.夂 The strain balance structure can be manufactured by the method described below. First, please refer to Figure 1 to form a buried insulating layer 11 and a semiconductor layer 12 on a semiconductor substrate. In this embodiment, an insulating layer is used. As an example, a wafer with a silicon layer (si 丨 ic〇n = n ~ insulator, so) is used as the starting material: using implanted oxygen (SIM0X) or SmartCut® technology to obtain isolation, However, this is not a limitation. The semiconductor layer (SOI layer) 12 is generally a silicon material having a thickness of about 2000 ^. The buried insulating layer 1 is generally composed of silicon oxide. After that, a silicon germanium layer 14 is epitaxially grown on the silicon layer 12. As shown in FIG. 2, the thickness t2 of the silicon germanium layer 14 is to be equal to the thickness u of the silicon layer 12 so that the silicon layer ^

530385, description of the invention (4) conditions, brother ^ ^ ^ ^ ^ ^ ^ ^ stretch conditions, and the silicon germanium layer 14 is in a biaxial compressive strain / where: to obtain a strain balanced structure. As shown in the figure: epitaxial growth of a second silicon layer 16 on the silicon germanium layer 14 is shown in the third example. The thickness t3 of the second silicon layer 16 is equal to the thickness 1: 1 of the silicon layer 12 and silicon. # 二 、 The thickness ΐ2 is equivalent, so that the second silicon layer 16 series should be more hidden under biaxial stretching. In the case of a 1-channel element, the thickness t3 of the second silicon layer 16 must be sufficient so that parasitics do not form therein when the element is turned on, and the thickness 12 of the stone germanium layer 14 must be Thick enough, such as 100 angstroms, to accommodate most of the movable carriers (γ · —C. Yeo et ai., "Enhanced

Performance in sub-100 nm CMOSFETs using strained epitaxial s i 1 i con-german i umf,, IEEE International Electron Device Meeting Technical Digest, pp. 753-756, San Francisco, CA, Dec. 20 0 0 ·). The SiGe layer 14 is under biaxial compressive strain and can greatly increase the transmission properties of holes (S. Kaya et al., N Indication of velocity overshoot in strained Si0.8Ge0 · 2 p-channel MOSFETs ", Semiconductor Science and Technology, vol. 15, pp. 573, 2000.) The Mo fraction x of Ge in Si (Bux) Ge (x) layer 14 must be high enough to improve the performance of the p-channel device, but not too much. High to control junction leakage current and prevent strain relaxation problems. The Mohr fraction X of Ge in the Si (1_x) Ge⑴ layer 14 may be between 0.1 and 0.5. In the case of n-channel elements, The second silicon layer 16 is used as a channel, because the second silicon layer 16 is under a biaxial tensile strain and can greatly

530385

Increased mobility and transmission properties (Rim K. et al., &Quot; Fabrication and analysis of deep submicron strained-Si n-M0SFETs \ IEEE Trans. Elect. Dev., Vol. 47, no. 7 'PP · 1406, jul · 2000 ·). The thickness t3 of the second silicon layer 16 in the Guan 03 region must be sufficiently thick, such as 10 Å, so that it can accommodate most of the movable carriers of the n-channel element. Regarding the thickness requirements of the second stone layer 16 for the n-channel element and the p-channel element, for the p-channel element, the thickness t3 of the second silicon layer 16 must be thin enough, such as 20 angstroms, to prevent formation in the PMOS device. Parasitic capacitance. For an n-channel element, the thickness t3 of the NMOS region must be sufficiently thick, such as 00 Angstroms to enable it to accommodate most of the reverse charges (electrons) of the n-channel element. To enable the second silicon layer 16 to have two thicknesses, it can be achieved by the following method. First, the second silicon layer 16 with a thickness of 13a is grown in the fabrication process, and then a mask layer 18 is covered in the PM0s area. , Such as a silicon oxide layer, and then selectively grow the second stone layer 16 to a thickness t3b in the area exposed by the CMOS, as shown in FIG. 4. After that, referring to FIG. 5, the mask layer 18 is removed. Secondly, the general CMOS device manufacturing process is performed. First, as shown in FIG. 6, the PMOS device area and the NMOS device area are defined by a patterning process. Then, referring to FIG. 7, a gate insulating layer 22 is formed on the second silicon layer 6. For example, a chemical vapor deposition method is used to sink the silicon layer on the second silicon layer 16. Finally, referring to FIG. 8, a gate electrode 24 is formed on the gate insulating layer 22, and η-type and P-type ion doping (not in the (Shown), and the gate electrode 24 = side 璧

530385 V. Description of the invention (6) The spacer 26 is formed, for example, a chemical vapor is used as the spacer 26. The formation of the silicon nitride layer is / page / The main idea is 'in the above-mentioned strain flat beestone layer 12 and the v / 100 杳 5 mouths' in the insulating layer 11 and Yue ## As far as possible, there is no restriction to make the silicon sound 1 2 1 钤 料 料 料 甘 日 0 to make the insulation layer 11 and the silicon layer i 2 eight: * dagger, good eight to adjust so that the broken layer 12 can change its Lattice; Yes; Ground is easy to break or relax the bond of the interface between the insulating layer 11 and the silicon layer 12 to two atoms to perform before or after the epitaxial growth of the silicon germanium layer 14. The methods described in

The feature of this month is the use of the semiconductor thin semiconductor effect with the S film layer to relax the skin between the layers and the number of days. The conductor layer with a smaller lattice constant is in the tensile strain constant. The semiconducting electrode is s-occupied and has a large lattice b ^ 溥 layer 疋 under compressive strain. Obviously, this strain balance structure is not limited to at least two layers of silicon germanium / ···· silicon / silicon germanium / silicon / dioxin xixi // shixi germanium / dioxide xixi Shi Xicuo / Shi Xizhi Ben. ^ 'The above structure can implement the present invention. The materials used in the Ming are not limited to those cited in the examples, "the various materials with appropriate characteristics and formation methods are replaced, and the structural space of Maoyue is not limited to the dimensions cited in the examples." It can be seen in the figure that the silicon-germanium layer with compressive strain can have a large transmission rate to increase the driving current of the p-channel element, and the silicon layer with a tensile strain can produce a rapid electron velocity effect to increase η Pass & = actuating current of the pieces, thereby improving the performance of field effect transistor components. Throughout Example 2 In Example 2 of the present invention, a silicon layer having tensile strain is formed.

530385

And the silicon germanium layer with compressive strain is ignoring whether the interface between the insulating layer u and the silicon layer 12 in the embodiment 丨 is easy to adjust without restriction. First, referring to FIG. 9, a buried layer is formed on a semiconductor substrate 60: an edge layer 61 and a silicon-germanium layer 62. In this embodiment, a wafer with SiGe on insulator on the insulating layer is used. Is the starting material. Shixi germanium layer μ

The germanium 3 is xl and the thickness is ". The buried insulating layer 61 is generally composed of silicon oxide. Another option for this embodiment is to use a wafer with a silicon layer (S (H) on the insulating layer) As a starting material, a buried insulating layer 91 and a silicon layer 92 are formed on a semiconductor substrate 90. The thickness of the silicon layer 92 is less than 100 A. The buried insulating layer 91 is generally composed of silicon oxide. A silicon-germanium layer 94 is epitaxially grown on the silicon layer 92, and then a diffusion process is used to diffuse germanium into the silicon layer 92 to the interface of the silicon oxide layer 9 丨 to change the regional bonding and form a stone on the insulating layer. The substrate of the SiGe layer (SiGe — on-insuiat〇r) is shown in the figure. Because the germanium diffuses to the interface of the silicon oxide layer 9 丨, the lattice constant of the initial silicon layer 92 and the germanium of the silicon germanium layer 92 are The Mohr fraction is χΐ, so a Si (1_xl) Ge (xl) layer similar to the Shixi germanium layer 62 can be formed. Please refer to FIG. 11 later on the Si (Buxl) Ge (xl) layer 62 or 94 ( For the sake of simplicity, the following description is only based on the Si (1_xl) Ge (xl) layer 62.) A second Si (1_x2) Ge (x2) layer 64 is epitaxially grown on the second Si (1_x2) Ge. (x 2) The error content of layer 64 is x2 and the thickness is t7. The molar fraction x2 of germanium in the second Si (ix2) Ge (x2) layer 64 is greater than χΐ, so that the second 31 (^ 2) (^ ( The required layer 64 is under the condition of biaxial compressive strain. This strain strength is equivalent to growing a pseudomorphical Sin_ (x2_xl)] Ge (x2_xl) layer on a silicon matrix layer, and this stone matrix layer Interface bonding with insulating layer (stone oxide layer) is strong

530385 V. The description of invention (8) is not easy to adjust without restriction. However, this second ^. The layer 64 is under a biaxial compressive strain condition, ignoring whether the interface bond between the insulating layer “and the silicon layer 62 is easy to adjust freely. Then, a second silicon is epitaxially grown on the second silicon germanium layer 64. Layer 16, as shown in FIG. 3, the strain strength is equivalent to growing a pseudomorphical silicon layer on a Si (^) Ge (x " matrix layer, and the si (Buχ1) Ge (xn The interface bond between the matrix layer and the insulating layer (silicon oxide layer) is strong and not easy to adjust freely. If Si (i xi) Ge (the interface bond between the matrix layer and the insulating layer (stone oxide layer)) The knot is completely or partially free to adjust easily, so the tensile strain of the uppermost silicon layer will be reduced. However, the second stone layer 66 (the uppermost silicon layer) is under the condition of biaxial tensile strain While ignoring whether the interface bonding between the insulating layer 61 and the silicon layer 62 is easy to adjust without restriction ^ In summary, in the description of this embodiment 2, a stone layer with tensile strain and a compressive strain can be formed. Whether the interface between the buried insulation layer ~ (silicon oxide layer) 61 and the bottommost silicon layer 62 is ignored Unconstrained adjustment. Since the second silicon layer 66 also has two thicknesses for the thickness requirements of the n-channel element and the p-channel element, the processes of the previous embodiment are then performed in accordance with Figures 4 to 8 Steps and procedures to complete the production of the element. Furthermore, the material materials used in the present invention are not limited to those cited in the examples, they can be replaced by various substances with appropriate characteristics and formation methods = replacement, and the present invention The structural space is also not limited to the ruler / small referenced in the examples. Cai Da Figure 8 shows that the invention is not yet proposed, taste points, ........丨 丨 From a female, this CMOS device has the following sub-components.

0503-7196TWF (N); TSMC200M254; ycchen.ptd * Ding Yier

530385 V. Description of the invention (9)-There is a silicon substrate 10 on the insulating layer. The first element system is a silicon layer connected to a silicon layer 12, among which 7 fin layers 1 and 4 are epitaxially grown at the "14 series" using the above method; double == biaxial tensile strain and Shi Xi structure. In the case of fine strain, a strain-balanced junction can be obtained: the first is a second silicon layer 16 that is grown on the silicon germanium layer 14; the first is that it has a first thickness and is suitable for a PM0S device , And a first degree is suitable for a NMOS device. The A ^ CM0S element also has the following sub-elements: a gate insulation layer 22, a shape; a stone layer 16; a gate electrode 24, formed on The gate insulation layer 22 is provided. The present invention further proposes a CMOS device with a strain-balanced structure. As shown in FIG. 8, the CMOS device has a secondary element. The first element is a silicon germanium layer on the insulation layer. The substrate 60, which ignores whether the interface between the insulating layer 61 and the stone germanium layer 62 is easy to adjust freely. The second element is a second silicon germanium layer 64, which is epitaxially grown using the above method. On the silicon germanium layer 62, the mole fraction of germanium of the second silicon germanium layer 64 is greater than that of the silicon germanium layer 62, so that the silicon germanium layer 62 The second silicon germanium layer 64 is under a biaxial tensile strain condition and the second silicon germanium layer 64 is under a biaxial compressive strain condition to obtain a strain balanced structure. &Amp; The third element system is a second silicon layer 66, which is grown in the first On the two silicon germanium layers 64, the second silicon layer 66 has a first thickness suitable for a PMOS device, and a second thickness suitable for a NMOS device. This CMOS device also has the following sub-components: a gate Insulation layer 2 2, shape

0503-7196TWF (N); TSMC2001-1254; ycchen.ptd page 13 53〇385

A gate electrode 24 formed on the second stone layer 16 is formed on the gate insulation layer 22. The material used in the present invention # τ ^ can be composed of a variety of materials: The structure space of the present invention cited in the examples is also replaced by the substance and the formation method, and although the present invention has been described with :; The invention is limited, and any practice is disclosed as above, but it is not intended to be used as an attached patent application.

530385 Brief description of the drawings In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, the following describes the preferred embodiments and the accompanying drawings in detail, as follows: Figures 1 to 8 show A cross-sectional view of a manufacturing process of a CMOS device having a strain balance structure according to Embodiment 1 of the present invention. 9 to 11 are cross-sectional views showing the manufacturing process of a CMOS device having a strain-balanced structure according to Embodiment 2 of the present invention. [Symbol description] There is a silicon layer base on the insulating layer of 10 ~ 11; 11, 6 and 9 1 ~ insulating layer; 12 ~ Shixi layer; 62, 92 ~ cut the wrong layer; 16, 6 ~ 6 second silicon layer ; 1 8 ~ mask layer; 2 2 ~ gate insulation layer; 2 4 ~ gate electrode; 2 6 ~ spacer wall; 94, 64 second silicon germanium layer.

0503-7196TWF (N); TSMC2001-1254; ycchen.ptd page 15

Claims (1)

530385 6. Scope of patent application k. A method for manufacturing a CM0S (Complementary Metal Oxide Semi-Electric Transistor) element with a strain-balanced structure, including the following steps: providing a substrate with a Shi Xi layer (Soi) on an insulating layer; Growing a silicon germanium layer on the silicon layer, wherein the silicon layer system is under a biaxial tensile strain condition and the silicon germanium layer system is under a biaxial compressive strain condition to obtain a strain balanced structure; A second silicon layer is formed on the germanium layer, wherein the second silicon layer has a first region with a first thickness and a second region with a second thickness; a patterning process is performed on the substrate to define the first A region is a PM0S (P-type metal-oxide-semiconductor field-effect transistor) element region and the second region is a NMOS (N-type metal-oxide-semiconductor field-effect transistor) element region; a gate insulating layer is formed on the second silicon layer; And forming a gate electrode on the gate insulating layer. 2. The method for manufacturing a CMOS device with a strain-balanced structure as described in item 1 of the scope of the patent application, further comprising interrupting or relaxing the insulating layer by implanting atoms before or after growing the stone germanium layer. The bonding of the insulating layer and the interface between the silicon layers on the base of the silicon layer (sio) makes it easy to adjust the interface between the insulating layer and the silicon layer so that the silicon layer can change its lattice constant. 3. The method for manufacturing a CMOS device with a strain-balanced structure as described in item 1 of the scope of the patent application, further comprising interrupting or relaxing the silicon layer on the insulating layer by implanting atoms after growing the silicon-germanium layer ( The bonding between the insulating layer and the interlayer interface of the silicon substrate makes the interface between the insulating layer and the silicon layer easy to adjust so that the silicon layer can change its lattice constant. 4 · The strain-balanced structure as described in item 1 of the patent application 0503-7196TW (N); TSMC2001-1254; ycchen.ptd page 16 530385 6. Method for manufacturing a patent-application CMOS device, wherein the method for forming the second silicon layer includes the following steps: forming on the silicon germanium layer Covering the second silicon layer of the first thickness; covering a mask layer in the PMOS region; selectively epitaxially growing the second silicon layer to the two thicknesses in an exposed area not covering the mask layer; and removing the mask Curtain layer. 5. The method for manufacturing a CMOS device with a strain-balanced structure as described in item 4 of the scope of the patent application, wherein the mask layer is a silicon oxide layer. 6. The method for manufacturing a CMOS device with a strain-balanced structure as described in item 1 of the scope of the patent application, wherein the first thickness is 10 to 30 angstroms. 7. The method for manufacturing a CMOS device with a strain-balanced structure as described in item 1 of the scope of the patent application, wherein the second thickness is 100-120 angstroms. 8. As described in the patent application 胄 ® item i of the manufacturing method with CMOS device, the deposition method of the monolayer oxide monolayer insulation layer is deposited using the chemical vapor phase 9 · For example, the manufacturing method of the first patented CMOS device in the scope of patent application, "Crystal method with strain balance structure". The growth of the second germanium layer using selective worms. The manufacturing method of the device, which has a strain-balanced structure between 0.1 and 0.5. The molar fraction of germanium in the split layer is medium, 0503-7196TWF (N); TSMC2001-1254; ycchen.ptd No. 17 Page 530385 6. Scope of patent application11. A right deer ▲ includes the following steps: a method for manufacturing a 2cMOS device with a strain balance structure, and lifting the bottom; the axial stretching of the germanium is better than having a pair of PM0S elements in the The CMOS base system of 12 is adjusted. The CMOS formation method of 13 is based on the supply and output, and it is based on the SiGe-on-insulator layer. t growing a second silicon germanium layer, wherein the first The strain of the silicon germanium layer: the silicon germanium layer is used to make the silicon germanium layer system under double, LV obtains a strain equilibrium structure from / and the second silicon germanium layer system is under a biaxial compressive strain j; The slab layer Λ, Gudi-thickness Π silicon layer, where the second silicon layer is in area 1, and a second thickness of the second area; the area of the pattern ;; a patterning process is performed to define the The first area is-# ^ The second area is an NMOS device area; Xi ρ arch j: a free-pole insulating layer is formed on the layer; and Λ, the edge layer is formed as an interrogation electrode. The component Λ is specially made to benefit: The strain-balanced structure described in item 忽略 ignores the insulating bank and: t, for whether there is a silicon germanium layer on the insulating layer, and whether the interface between the θ and β silicon germanium layer is unrestricted and easy to apply. The method of Li Λ Wai :: said method, including a semiconductor substrate with a Shi Xi split layer substrate on the m insulating layer; a buried insulating layer and -silicon are formed on the substrate; The silicon germanium layer; and 0503-7196TWF (N); TSMC200M254; ycchen.ptd Page 18, 530385 VI. Application Patent Scope 1 ′ The diffusion of the germanium of the silicon germanium layer into the silicon layer to the interface of the insulating layer using a diffusion process to change the regional bonding to form a germanium layer on the insulating layer. Substrate. 14. The method for manufacturing a CMOS device with a strain-balanced structure as described in item 13 of the scope of the patent application, wherein the thickness of the silicon layer is less than 100 angstroms. ', 1 5 · The method for manufacturing a CMOS device with a strain-balanced structure as described in item 丨 丨 of the scope of patent application, wherein the method for forming the second silicon layer includes the following steps: forming the first silicon layer on the silicon germanium layer A thickness of the second silicon layer; covering a mask layer in the PMOS region; selectively epitaxially growing the second silicon layer to the two thicknesses in an exposed area not covered by the mask layer; and removing the mask layer. 16 · The method for manufacturing a CMOS device with a strain-balanced structure as described in item 15 of the scope of the patent application, wherein the mask layer is a broken oxide layer. 1 7 · The method for manufacturing a CMOS device with a strain-balanced structure as described in item 11 of the scope of patent application, wherein the first thickness is 10-30 Angstroms. 18 · The method for manufacturing a CMOS device having a strain-balanced structure as described in item 11 of the scope of the patent application, wherein the second thickness is 100 to 120 Angstroms. 1 9 · The method for manufacturing a CMOS device with a strain-balanced structure as described in item 11 of the scope of patent application, wherein the gate insulating layer uses a chemical gas 0503-7196TWF (N); TSMC200M254; ycchen.ptd page 19 530385 6. Scope of patent application-Phase deposition method to deposit a silicon oxide layer. 2 0. The method for manufacturing a CMOS device having a strain-balanced structure as described in item 11 of the patent scope of Shenyan, wherein the second silicon germanium is grown by a selective epitaxy method.亍 、 彳 史 用 选 21 · A manufacturing method of a CMOS device with a strain-balanced structure φ includes the following steps: / Provide-a substrate with a silicon layer (SOI) on the insulating layer; 1 a silicon germanium layer is grown on this layer Where the Shixi layer is under a biaxial tensile strain condition and the silicon germanium layer is under a biaxial compressive strain condition to obtain a strain balanced structure; a patterning process is performed on the substrate to define a PM0S element An NMOS device region; a gate insulating layer is formed on the stone germanium layer; and a gate electrode is formed on the gate insulating layer. 22. The method for manufacturing a CjOS device with a strain-balanced structure as described in item 21 of the scope of the patent application, further comprising interrupting or relaxing the silicon on the insulating layer by implanting atoms before or after growing the silicon-germanium layer. The bonding of the insulating layer and the interface between the silicon layers on the substrate of the layer (so) makes the interface between the insulating layer and the stone layer easy to adjust so that the silicon layer can change its lattice constant. 23. The method for manufacturing a CMOS device with a strain-balanced structure as described in item 21 of the scope of the patent application, further comprising interrupting or relaxing the silicon layer on the insulating layer by implanting atoms after growing the silicon-germanium layer ( s 〖〗) The bonding of the insulating layer and the interface between the silicon layers of the base makes the interface between the insulating layer and the silicon layer easy to adjust so that the silicon layer can change its lattice constant. 0503-7196TWF (N); TSMC200M254; ycchen.ptd 530385 6. Patent application scope 24. The method for manufacturing a 'CMOS element with a strain-balanced structure as described in item 21 of the patent application scope, wherein the gate insulating layer uses α A phase deposition method is used to deposit a silicon oxide layer. Breast milk 25. As described in item 21 of the scope of the patent application, He Tusheng ancient and native CMOS elements with strain flattening ^ ^ ^. ^ IW ,,,, and 0 structure. Method I, in which the growth of the silicon germanium layer is selective. 26. For example, the founder of the CMOS device described in the scope of application for patent 21, Chegans — a place with a balance structure between 0.1 to 0.5. The Mohr fraction of germanium in the interlayer is composed of 2 and 7. columns; a simple element with a strain-balanced structure provides a silicon-germanium layer (SiGe_〇n_insuiat〇r) on the insulation layer based on the silicon-germanium A second silicon-germanium layer is grown on the layer. The molar fraction of germanium of 1 is greater than that of the middle A. The first germanium layer under the axial tensile strain of germanium II makes the double-layered stone layer system in a dual-case condition. Next, a patterned process is performed to obtain a strained staggered layer under biaxial compressive strain to define the S element region and the gate formed on the second silicon germanium layer to form a gate on the closed-pole insulating layer. Pole 2: and 28. The manufacturing method of the CMOS device according to item 27 of the patent application scope, wherein the substrate of the strain-balanced structure of the eight tons is ignoring the insulating layer and the silicon-germanium substrate. 2 There is silicon-germanium on the insulating layer. Is the interface between layers q easy and free? 530385 Adjustment. The method for manufacturing a JCM0S device with a strain-balanced structure as described in / claimed in the Patent Scope No. 27, wherein the method for forming a substrate with a germanium layer on the insulating layer includes the following steps: providing a semiconductor substrate; A buried insulating layer and a silicon layer are formed on the silicon layer; the silicon germanium layer is grown on the side silicon layer; and the germanium layer of the Shixi layer is diffused into the Shixi layer to the Yiyuan layer by the expansion process. " To change the area bonding to form the substrate of the germanium layer on the insulating layer. 30. The manufacturing method of the corresponding CMOS device as described in item 29 of the patent application scope, wherein the Shi Xiheng is small, .Structure 100 angstrom. Yuyou "y 3 1 · The method for manufacturing a CMOS device with a strain-balanced structure as described in item 27 of the patent application scope, wherein the gate insulating layer is deposited using a chemical phase deposition method. Silicon oxide layer. "3 2 · The method for manufacturing a CMOS device with a strain-balanced structure as described in item 27 of the scope of the patent application, wherein the second silicon-germanium selective epitaxy method is grown. ^ 33 · —A kind of strain-balanced structure The manufacturing method of the CMOS device is suitable for a semiconductor substrate, and includes the following steps: A first thin film layer and a second thin film are successively formed on the semiconductor substrate, wherein the first thin film layer is under a biaxial tensile strain And the second thin film layer is under a biaxial compressive strain condition to obtain a strain 530385 --------- --__ Balanced structure applying for patent scope; patterning process is performed on the substrate to define a PMOS device and NMOS device area; Thousand & and the second thin film layer A gate insulating layer is formed thereon; and a gate electrode is formed on the gate insulating layer. 34. The method for manufacturing a CMOS device having a strain-balanced structure according to item 33 of the scope of the patent application, wherein a lattice constant of the first thin film layer is smaller than a lattice constant of the second thin film layer. 35. The method for manufacturing a CMOS device having a strain-balanced structure as described in item 33 of the scope of the patent application, wherein the first thin film layer is a silicon and germanium broken layer. 4 3 6. The method for manufacturing a CMOS device with a strain-balanced junction as described in item 33 of the scope of the patent application, wherein the second thin film layer is a silicon, silicon, silicon, or silicon oxide layer. 37. The method for manufacturing a simple element with a strain as described in item 33 of the scope of the patent application, wherein the second and factory selective epitaxy method is formed. iπ, 3 8 · The method for manufacturing a CMOS device having a strain-balanced structure as described in Item 33 of the declared patent scope, wherein the gate insulating layer is formed by depositing a monoxide layer using a chemical vapor deposition method. 39 · —A method for manufacturing a component having a strain balance structure, which is applicable to a semiconductor substrate, including the following steps: A first thin film layer and a second thin film layer are formed on the semiconductor substrate successively, wherein the first thin film Strata under biaxial compressive strain conditions 530385 6. Scope of patent application The second thin film layer is under a biaxial tensile strain condition to obtain a strain balanced structure; a patterning process is performed on the substrate to define a PM0S element region and a NMOS element region; A gate insulating layer is formed on the second thin film layer; and a gate electrode is formed on the gate insulating layer. 40. The method for manufacturing a CMOS device having a strain-balanced structure according to item 39 of the scope of the patent application, wherein a lattice constant of the first thin film layer is greater than a lattice constant of the second thin film layer. 41. The method for manufacturing a CMOS device with a strain-balanced structure as described in item 39 of the scope of application for a patent, wherein the first thin film layer is a Shi Xi, Ge or SiGe layer. 42. The method for manufacturing a CMOS device with a strain-balanced structure as described in item 39 of the scope of the patent application, wherein the second thin film layer is a silicon, germanium or germanium layer. 4 3 · The method for manufacturing a CMOS device with a strain-balanced structure as described in item 3g of the scope of patent application, wherein the gate insulating layer is deposited using a chemical vapor deposition method; 44. A method for manufacturing a CMOS device with a strain-balanced structure, applicable to a semiconductor substrate, including the following steps: forming a first thin-film layer and a second thin-film layer on the semiconductor substrate successively to obtain a strain-balanced structure; The substrate is subjected to a patterning process to define a PMOS device area and a NMOS device area; 530385 6. Scope of patent application: forming a gate insulating layer on the second thin film layer; and forming a gate electrode on the gate insulating layer. 45. The method for manufacturing a CMOS device having a strain-balanced structure according to item 44 of the scope of the patent application, wherein a lattice constant of the first thin film layer is smaller than a lattice constant of the second thin film layer. 4 6. The method for manufacturing a CMOS device having a strain-balanced structure according to item 44 of the scope of the patent application, wherein a lattice constant of the first thin film layer is greater than a lattice constant of the second thin film layer. 4 7. The method for manufacturing a CMOS device with a strain-balanced structure as described in item 44 of the scope of patent application, wherein the first thin film layer is under a biaxial compressive strain condition. 48. The method for manufacturing a CMOS device with a strain-balanced structure according to item 44 of the scope of the patent application, wherein the first thin film layer is under a biaxial tensile strain condition. 4 9. The method for manufacturing a CMOS device with a strain-balanced structure as described in item 44 of the scope of patent application, wherein the second thin film layer is under a biaxial compressive strain condition. 50. The method for manufacturing a CMOS device having a strain-balanced structure according to item 44 of the scope of the patent application, wherein the second thin film layer is under a biaxial tensile strain condition. 5 1. The method for manufacturing a CMOS device having a strain-balanced structure as described in item 44 of the scope of the patent application, wherein the first thin film layer is a silicon, germanium, or silicon layer. 5 2. Strain-balanced structure as described in item 44 of the scope of patent application 0503-7196TWF (N); TSMC2001-1254; ycchen.ptd page 25 530385 ✓, manufacturing method of applying CMOS element ^ r «for patent application, wherein the second thin film layer is silicon, # 4 Shi Xi germanium layer. False or 5 3 As described in item 4 of the Ming patent, the fabrication of a CMOS device with a strain-level surname, Shengshi balance structure phase deposition, and% I method, wherein the interphase insulating layer uses a chemical phase. A deposition method deposits a silicon oxide layer. Yu Liao 54 · —a CMOS device with a strain-balanced structure, including: an insulating layer with a silicon substrate; ♦ a staggered layer 'grown on the insulating layer with a silicon substrate, f :: under biaxial tensile strain Under the circumstances, the Shixi germanium layer is located: under the compressive strain condition to obtain a strain-balanced structure; " in a double light-second silicon layer, grown on the silicon-germanium layer, wherein the second one has The first thickness is suitable for a PMOS device and a second thick NMOS device; 避 is avoided from being used for a idler insulating layer formed on the second silicon layer; and a gate electrode is formed on The gate is on an insulating layer. 55. The CMOS device described in item 54 of the scope of patent application, wherein the first thickness is 10-30 angstroms. • Structure with strain balance as described in item 54 of the declared patent scope. The CMOS το component, wherein the second thickness is 100-120 angstroms. 57. The CMOS element with a strain-balanced structure as described in item 54 of the scope of the patent application, wherein the gate insulating layer is a silicon oxide layer deposited using a chemical vapor deposition method. 58 · — A CMOS device with a strain-balanced structure, comprising: a silicon germanium layer substrate on an insulating layer; 0503-7196TWF (N); TSMC2001-1254; ycchen.ptd page 26 530385 Sixth, the scope of the application for a patent a second hard error \ wherein the second silicon error; two grown on the insulating layer has a silicon germanium layer substrate, The Shi Xi germanium layer is at i = f = Mohr fraction is greater than the dream cross layer, so that-under double, strain conditions, to obtain a strain balanced structure; the layer has a first Z grown on the second silicon On the germanium layer, the second silicon is suitable for a PMOS device at a f-degree of a NMOS device, and a second thickness is suitable-a free-pole insulating layer is formed on the second silicon layer; and a 5 g closed electrode Is formed on the gate insulating layer. As described in item 58 of the scope of the patent application, I M 0 S 7C * with a strain-balanced structure ^ (half, Gan rl · »r where 'where' is ignored for the silicon germanium layer on the insulating layer ~ ,,,, It is easy to adjust whether or not the interlayer interface of the silicon layer and the germanium layer is free. 6 〇 70 pieces of MOS with strain balance structure as described in item 58 of the patent application scope, wherein the first thickness is 10-30 angstroms. 6 1 · The element with a strain-balanced structure as described in item 58 of the scope of the patent application, wherein the second thickness is loo—120 angstroms. 62. A CMOS device with a strain-balanced structure, wherein the gate insulating layer is a silicon oxide layer deposited using a chemical vapor deposition method. 63 · —A CMOS device with a strain-balanced structure includes: a silicon substrate on an insulating layer; A Shixi germanium layer is grown on the insulating layer with a Shixi layer substrate, wherein the Shixi layer is under a biaxial tensile strain condition and the Shixi germanium layer is under a biaxial compressive strain condition. Obtain a strain-balanced structure; Page 27 530385 VI. Patent application scope A PM0S element area and an NMOS element area are located on the substrate; a gate insulating layer is formed on the silicon germanium layer; and a gate electrode is formed on the gate insulation On the floor. 64. The CMOS device having a strain-balanced structure as described in item 63 of the scope of the patent application, wherein the gate insulating layer is deposited using a chemical vapor deposition method. 'b 65 · A CMOS device with a strain-balanced structure includes: a silicon germanium layer substrate on an insulating layer; a second silicon germanium layer grown on the silicon germanium layer substrate on the insulating layer, wherein the second silicon The molar fraction of germanium in the germanium layer is greater than that of the silicon germanium layer, so that the edge-stone split layer system is under a biaxial tensile strain condition and the second silicon germanium layer system is under a biaxial compressive strain condition. A strain balanced structure is obtained; a PMOS device region and a NMOS device region are located on the substrate; a gate insulating layer is formed on the second silicon germanium layer; and a gate electrode is formed on the gate insulating layer . 66. The CMOS device with a strain-balanced structure according to item 65 of the scope of the patent application, wherein the substrate with a silicon germanium layer on the insulating layer is ignoring whether the insulating layer and the interface between the silicon germanium layer are easy to adjust without restriction. 67. The CMOS device with a strain-balanced structure according to item 65 of the scope of the patent application, wherein the gate insulating layer is a silicon oxide layer deposited using a chemical vapor deposition method. 68 · — A CMOS device with a strain-balanced structure suitable for a semi-conductor substrate ’includes: a first thin film layer grown on the substrate, wherein the first thin film layer 0503-7196W (N): TSMC200M254; ycchen.ptd page 28 530385 6. The scope of patent application is under the condition of biaxial tensile strain; the second thin film layer is grown on the first thin film layer, wherein the second thin film layer The thin film layer is under a compressive strain condition to obtain a strain-balanced structure; a PMOS device region and an OS device region are located on the substrate; a gate insulating layer is formed on the silicon germanium layer; and a gate An electrode is formed on the gate insulating layer. 69. The method for manufacturing a 0JOS device with a strain-balanced structure as described in item 68 of the scope of the patent application, wherein the lattice constant of the first thin film layer is greater than the lattice constant of the second thin film layer. 70 · The CMOS device with strain flatness as described in item 68 of the scope of patent application, wherein the first thin film layer is a shixi, zhao or shixi balance layer 4 71 · As described in item 68 of the scope of patent application A CMOS device with a strain-balanced junction, wherein the second thin film layer is a Shi Xi, Bi or Shi Xi Bi layer. . Therefore, the application of the invention has a strain-balanced ^ structure layer described in item 其中, wherein the idler insulating layer is a chemical vapor deposition method. 73. A CMOS device with a strain-balanced structure, using a plutonium conductor substrate, including : Dry suitable for half a first thin film layer, grown on the substrate; a second thin film layer, grown on the first thin film layer, the thin film layer and the first thin film layer are a strain balanced structure; κ a The PM0S element region and a nmOs element region are located on the substrate. A gate insulating layer is formed on the silicon germanium layer; and-, a gate electrode is formed on the gate insulating layer. 530385 Even γμ4. The S-element with a strain-balanced structure as described in item 73 of the scope of the patent application, wherein the first lattice constant is smaller than the lattice constant of the two film layers. Sui Xun 75 \ The CMOS device with a strain-balanced structure as described in item 73 of the scope of the patent application, wherein the lattice constant of the first thin film layer is greater than the lattice constant of the second film layer. 76. The CMOS device having a strain-balanced structure as described in item 73 of the scope of the patent application, wherein the first thin film layer is under a biaxial compressive strain condition. 77. The CMOS device with a strain-balanced structure as described in item 73 of the scope of the patent application, wherein the first thin film layer is under a biaxial tensile strain condition. The CMOS device having a strain-balanced structure as described in item 73 of the scope of the patent application, wherein the second thin film Tang system is under a biaxial compressive strain condition. 79. The CMOS device having a strain-balanced structure according to item 73 of the scope of the patent application, wherein the second thin film layer is under a biaxial tensile strain condition. 80. The CMOS device having a strain-balanced structure as described in item 73 of the scope of the patent application, wherein the first thin film layer is a chopped, germanium, or stone germanium layer. 8 1 · The CMOS device having a stress-balanced structure as described in item 73 of the scope of the patent application, wherein the second thin film layer is a silicon, germanium, or silicon-germanium layer. 8 2 · The CMOS device with a strain-balanced structure as described in item 73 of the scope of the patent application, wherein the gate insulating layer is deposited using a chemical vapor phase method. 0503-7196TW (N); TSMC2001-1254; ycchen.ptd 30th buy 530385 Sixth, the scope of patent application Plotting > 5th layer. imi page 31 0503-7196TWF (N); TSMC2001-1254; ycchen.ptd