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TW503556B - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
TW503556B
TW503556B TW090118113A TW90118113A TW503556B TW 503556 B TW503556 B TW 503556B TW 090118113 A TW090118113 A TW 090118113A TW 90118113 A TW90118113 A TW 90118113A TW 503556 B TW503556 B TW 503556B
Authority
TW
Taiwan
Prior art keywords
semiconductor
wafer
conductive
pad
along
Prior art date
Application number
TW090118113A
Other languages
English (en)
Inventor
Naoto Kimura
Original Assignee
Nippon Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co filed Critical Nippon Electric Co
Application granted granted Critical
Publication of TW503556B publication Critical patent/TW503556B/zh

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    • H—ELECTRICITY
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    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
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    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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Description

五、發明說明d) 【發明背景】 1 ·發明之領域 數個日日Η 4月係關於一種半導體裝置，尤盆b Μ认從 受又1U曰日片相互蛤晶^ ^ ^不1 尤其是關於一種有複 2·相關技術豐的堆疊式半導體褒置。 、 』心描述 前趨勢年ί須：=話等產品外殼小型化的當 的外殼内，於是tt :的尺寸。為安裝在如此小型 帶—提者，使；ΪΞΓί導體晶片同樣大小的構裝。附 寸構裝）裝置。另*式^半導體裝置稱為CSP(晶片尺 構的半導體裴 面β人建礒—種具有堆疊封裝結 上下堆疊，=提裝結構中有複數個晶片彼此 圖1為顯示習知V導二里置及之多一數的電子電路功能。 不使用於習知半導'^ 、例的剖面圖，圖2為顯 舉例來說，如圖i _、一半導體晶片的平面圖。 的，士 ψ、# 所不’具有較小的尺寸同睥罝古夕 的此一 +導體骏置^寸门B寸具有多功能 晶片22所組成 體晶片21和第—半導體 24，沿其上表:具有複數個電極銲墊 具有複數個電極鮮塾27和中繼K歹，f ，體晶片22 兩侧並列，第二半 /口 /、上表面相對的 22晶片頂部，f ^體日日片21係設計成安裝在第一半導俨 1並用黏膠固定之。 干等體 a μοο卜於頂部安裝有第二半導髀曰结 甜片2:，係安襄在-絕緣印刷ί路板；;上，：f-半導體 之。上述結構必須使 ，路板23上並用黏膠固定 貞使用長配線或細長金屬配線，以電連接 第5頁 jvjjjjo jvjjjjo 極銲墊2 4 線與晶片 量，在第 外，另設 端子25， 鲜塾2 6和 ’外部配 絕緣印刷 印刷電路 孔3 3和導 體晶片2 1 此為避免 知，習知 電路板23 的尺寸便 無法再縮 半導體晶 不能減小 可縮小。 的第一半導體晶片22因兩 小第一半導體晶 片2 2的尺寸無法 ，因而出現裝置 ’但增加配線長度易產生配線之 接觸的問題。 設有通 連接導 電極銲 板23的 配線端 ，配線 包含配 以樹脂 部機械 為·尺 片2 2略 五、發明說明（2) 導電鲜塾26和電 間相互接觸或配 基於以上考 常之電極銲墊2 7 電銲塾2 6與中繼 墊24，如此導電 附帶說明者 配線層30，並由 子31在殼體内和 層3 0則精由通道 線28、29及半導 而成樹脂體32， 力破壞。由上可 寸設計成與印刷 大些，如此裝置 但上述裝置 端子2 5存在，而 言之，由於第一 電路板23尺寸亦 步縮減的問題。 一半導體晶片2 2 置中繼端子2 5。 配線2 8連接中繼 電極銲墊2 4即可 線端子3 1連接於 電路板2 3底面伸 板23上的導電銲 電銲墊2 6連接。 、2 2的鑄模空間 外界水氣進入且 的半導體裝置技 相同，只比第一 頂部，除 用配線2 9 端子2 5與 連通。 印刷電路 出。外部 墊26連接 此外，在 内，填充 可免受外 術其特徵 半導體晶 侧有細長的中繼 片2 2的尺寸。換 縮小，絕緣印刷 尺寸無法再進一 六旦再者’若第一半導體晶片22為儲存元件，則須將記憶 谷里和尺寸較所需為大的晶片提供給中繼端子2 5使用，如 此又會使該半導體裝置的成本變得昂責。 【發明的綜合說明】 、
第6頁 503556 五、發明說明（3) 因此本發 體裝置。 依本發明 上侧表面設有 在該印刷電路 體晶片上的中 半導體晶片上 於該第一半導 未被該第二半 方向的反方向 區域為 域上之 的該兩 該第二 係沿該 導體晶 接該第 導電銲 才非列的 與該中 半導體 電極銲 該導電 極銲墊 小；第 該第一 侧係沿 半導體 特定方 片的該 一電極 墊與沿 該第二 繼端子 晶片之 墊；外 鲜塾連 對應排 尺寸及成本減小之半導 一印刷電路板，於其 一半導體晶片，安裝 晶片，從該第〆半導 移，而安裝 該特定方向 晶片在該特 在該第一 的長度小 定方向上 一區域，比在該特定 晶片覆蓋的一個第二 該第二區 導體晶片 墊，沿著 的該兩侧 該第一半 配線’連 ’連接該 向之一側 導電銲墊 與該第二 的該第二 出，並與 係與該第一及第二電 之半導體裝 複數個導電 板上方；一 心位置，朝 ，該第二半 體晶片’該 導體晶片覆 上，未被該 一電極銲墊 半導體晶片 該特定方向 晶片兩侧排 向彼此分開 第二區域上 鲜塾和該導 著該第二半 電極銲墊； ;第四金屬 朝該特定方 部端子，由 接，其中’ 歹1J 0 提供 置’包含： 銲墊；_ $ 第二半導體 特定方向偏 導體晶片在 ，一半導體 盖的一個第 第二半導體 ，沿著在該 的兩側排列 彼此分開； 列，該第二 ;複數個中 之一側排列 電辉塾；_ 導體晶片之 第二金屬配 配線，連接 向的反方向 该印刷電路 該導電銲墊 第一區域及 ，該第一半 第-一電極鲜 半導體晶片 繼端子，沿 :第一金屬 一金屬配線 朝該特定方 線’連接該 該中繼端子 之一側排列 板的底面伸 503556 五、發明說明（4) 此外’製作中繼端子及第一電極鲜塾時 置以並列較佳，f中繼端子外形宜製為-加長矩形开“立 另外，衣作第、二、三、四金屬配線以金線 再者，外部配線端子宜為軟銲料製成的銲球 。 如上所述，本發明提供如下效果：第二 原在第一半導體晶片上的中心位 片從 安裝於該第-半導體晶片上，使j在 的中繼端子，目第二半導體 =侧 被中繼端子佔用的晶片區域，半= 曰曰片尺寸，達到縮小半導體裝置尺寸的目的。導體 依本發明，第一丰塞u ^ 記憶容量之半導體晶片。因：片過大 =的半導體晶片。故本發明亦能以:低以 【較佳實施例之詳細說明】 以下將參照附m此丄丄 細說明。 、回 發明之半導體裝置實施例作詳 圖3A為顯示依本發明一每 圖，圖3B為顯示垂/苑例之半導體裝置的平面 圖3C為顯示依同一每貝鈿例之半導體裝置的剖面圖， _及3"看出體晶片的平面圖。由 2，安裝於含複數個導電置包括一第一半導體晶片 外，第二半導體 2之、'，邑緣印刷電路板3上。 置，朝特定方向IS之原安在，一半導體晶片2上的中^ 503556 五、發明說明（5) =用曰黏膠接合。第二半導體晶片丄上側表面，有複數個電 、:吁塾4在依上述特定方向分開的兩侧相對成直線並列， =數個，極銲墊5同樣於第一半導體晶片2之上侧表面，依 述特定方向分開的兩侧相對成直線排列。此外，與排列 由i述特定方向之反方向的一侧之電極銲墊4相同數目的 端子10，被插入在第一半導體晶片2較寬廣之上側表 與電中間。絕緣印刷電路板3的兩侧，排列有 ^ Μ 、干墊、5及中繼端子10相同數目的導電銲墊12。細 印刷ί線8連接第，半導體晶片1上的電極銲墊4，與絕緣 2上的電，亟板r3 if導電銲塾12 ’配線9連接第一半導體晶片 此冰電/知墊5，與絕緣印刷電路板3上的導電銲墊12。 的配線層=2經由通道孔16和印刷電路板3底側成形 的外部酉曰己線端子14=線層13與由印刷電路板3底面伸出 連接ί二接二 1塾12與中繼端子10，配線6 12即可連通。 極鋅塾4，因此電極銲墊4與導電銲塾 ,,另一方面，朝第二半導體晶片1移動方向一側的_ 線，不會有接觸到配線8、9或 體 的配 =12與電極銲塾4、5位=以因為導 墊2與電極銲塾4，酉己線9連接導電鲜塾12與電連^導電 1亜士述結構因電極銲墊4與導電銲墊1 2直接連通，而 :要中間的中繼端子10，如此可縮小第一半不再 寸，理由將詳述於後。 守媸日日片的尺
五、發明說明（6) 佳。導體中=〇其外形製成-加長矩形較 此外，中繼端子Μ / 頁光製程中的遮罩圖案。 二半導體曰：齊，而另一端位置儘可能向第 ^p 51向延伸，使該端至電極銲墊4距離等同於 V電知塾12至電極銲墊5的距離。 施例=ϊ!刷電路板的材料為陶究或玻璃樹脂，本實 一籍广# ^疋成本較低的玻璃樹脂。此外，本實施例使用 以再乳者:/接合第一半導體晶片2與第二半導體晶 口衣置在低伏特數的信號下運作，所以细金 屬配J及配線6、7、8、9採用低電阻的金線較佳。、、 其次，若能用樹脂覆蓋住配線6、7、8、9 該樹脂體15底部能與絕緣印刷電路板以相同； 而該樹脂體頂部應塑成漸尖的外型並將其邊角導圓成化 λ换i ί垃=部配線端子14與絕緣印刷電路板3不能用低 凸塊方式接合，最好先將軟銲熔成高銲球，再使- 球夾具來黏合外部配線端子14與絕緣印刷電路板3。； 如上所述，由圖2可看出習用技術中繼端子25 體晶片22是不可或缺的。然由圖孔可看出，因第二 向Λ一、半導體晶片2的一侧移動，使上述“繼端子 2 5 ”、、存在的必要。如此可省去原被中繼端子加長矩形 型所佔用的晶片區域2〇，來縮減第一半導體晶片2的尺、 503556 圖式簡單說明 圖1為習知半導體裝置之一例之剖面圖。 圖2為習知半導體裝置之第一半導體晶片的平面圖。 圖3A依本發明一實施例之半導體裝置的平面圖。 圖3B為依本發明同一實施例之半導體裝置的剖面圖。 圖3C為依同一實施例之第一半導體晶片的平面圖。 【符號說明】 1，2 1第二半導體晶片 2, 22第一半導體晶片 3，2 3絕緣印刷電路板 4, 5, 24, 27 電極銲墊 6, 7, 8, 9, 28, 29 金屬配線 1 0，2 5中繼端子 1 2，2 6 導電銲墊 1 3，3 0 配線層 1 4，31 外部配線端子 1 5，3 2樹脂體 1 6，3 3 通道孔 2 0 晶片區域
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Claims (1)

  1. 範圍 六、申請專利 • 一種半導 一印刷電路板 一第一半導體 曰曰 片覆蓋 ’沿著 的兩側 彼此分 ’沿著 該兩側 子，沿 片在 的一個第一區域，比在該 一第 置，朝特 第二半導 2 ，該第 晶片覆蓋 被該第二 第一 該第一半 側係沿該 第二 第二半導 複數 上之一彻1 二半導體 定方向偏 體晶片在 一半導體 半導體晶 電極銲墊 導體晶片 特定方向 電極銲墊 體晶片的 個中繼端 排列； ，包含： 上側表面 安裝在該 從該第一 安裝在該 方向的長 該特定方 的一個第 在該第一 排列，該 開； 該第二半 係沿該特 該第一半 設有衩數個導電銲墊； 印刷電路板上方； 半導體晶片上的中心位 第一半導體晶片上，該 度小於該第一半導體晶 向上未被該第二半導體 特定方向的反方向上未 二區域為小； 區域及该第二區域上之 第一半導體晶片的該兩 導體晶片兩侧排列，該 定方向彼此分開； 導體晶片的該第二區域 第一金屬配線 第二金屬配線 晶片之朝該特定方 第三金屬配線 第四金屬配線 之朝該特定方向的 外部端子，由 銲塾連接， ’連接 ’連接 向之一 ，連接 ，連接 反方向 該印刷 該第一電極銲墊和該導電銲墊； 該導電銲墊與沿著該第二半導體 側排列的該第二電極銲墊 该導電銲墊與該中繼端子 該中繼端子與該第二半導曰 之一侧排列的該第二以= 電路板的底面伸出，並與該導電 第12頁 503556 六、申請專利範圍 其中，該導電銲墊係與該第一及第二電極銲墊對應排 列。 2. 如申請專利範圍第1項之半導體裝置，其中，該 中繼端子與該第一電極銲墊兩者並列形成。 3. 如申請專利範圍第2項之半導體裝置，其中，該 中繼端子係呈加長的矩形。 4. 如申請專利範圍第1至3項中任一項之半導體裝 置，其中，該第一、二、三、四金屬配線均為金線。 5. 如申請專利範圍第1至3項中任一項之半導體裝 置，其中，該外部端子為形成為球狀之軟銲料。
    第13頁
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