W455 A7 B7 7155twf.doc/006 五、發明說明（I ) 發明領域 本發明是關於時脈訊號產生裝置及其使用之時脈訊號 傳遞方法，尤指一種自我產生與調整之內部時脈產生之時 脈訊號產生之裝置及其使用之時脈訊號傳遞方法。 發明背景 許多電子裝置需要時脈程序用之振盪訊號或時脈訊 號’以達成裝置內的同步。隨著電子裝置變得更爲複雜， 因而產生能夠用於低成本電子裝置內的低成本時脈訊號產 生裝置的需求。大部份的電子裝置使用相位鎖定迴路或反 相器迴路以產生內部時脈訊號。 如本技藝之人士所知，相位鎖定迴路(phase lock loop; PLL)由一相位比較器，一迴路濾波器以及一壓控振盪器 (voltage control oscillator;VOC)組成。一基本時脈與一參考 時脈被輸入PLL。相位比較器比較基本時脈與參考時脈的 相位並輸出代表基本時脈與參考時脈之相位差的訊號。相 位爐波器去除該訊號之高頻成份。壓控振盪器對應迴路濾 波器之輸出訊號而輸出一頻率變化的時脈。因此，VOC時 脈具有對應PLL之輸出訊號的振盪頻率。相位鎖定迴路設 計有許多缺點。PLL需花費時間以鎖定訊號，容易受雜訊 影響’受限於可運作的頻率範圍，具有高功率消耗，複雜 的設計以及建立成本昂貴。 許多的設計也使用反相器迴路以產生時脈訊號。反相 器迴路包括複數個反相器，每一反相器的輸入端連接到輸 出端。反相器迴路具有一輸入外部時脈並提供一串被偏移 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -----I-----I -裝--------訂----I — I I 1^. (請先閱讀背面之注意事項再填落本頁) 經濟部智慧財產局員工消費合作社印製 472455 A7 B7 7155twf·doc/006 五、發明說明（之） 相位的時脈訊號。這允許一個具有較高頻率的內部時脈的 產生。反相器迴路的缺點在於頻率不精確及頻率範圍的限 制。 此外，PLL及反相器迴路二者都需要高頻的外部頻率 產生器。這些裝置是昂貴的，並且增加印刷電路板上的高 頻應力。 因此存在有低成本，寬的頻率範圍，精確的頻率控制， 低消耗功率，且不需要昂貴的高頻時脈產生器的內部時脈 產生器的需求。 發明綜合說明 本發明包括一種可以在內部自我產生一時脈訊號並且 經由參考頻率的使用而自我調整該時脈的裝置及其使用之 時脈訊號傳遞方法。 該裝置包括複數個傳遞延遲裝置’於一實施例中可以 多工器爲之。該等多工器可以被個別地選擇以便允許一訊 號行進過其中，或不允許訊號經過。該裝置藉由在傳遞裝 置的開始設定一邏輯狀態以產生一時脈訊號。該訊號隨後 通過該等傳遞裝置。該訊號經過該傳遞裝置所需的時間依 被選擇的裝置的數目而定。於該等訊號經過該等裝置後， 邏輯狀態改變，然後程序重新開始。因此，利用在裝置的 輸出改變邏輯狀態而可以產生訊號。藉由改變在時脈產生 器中的傳遞延遲裝置的數目，可以改變時脈訊號的頻率。 而本發明之時脈產生裝置所利用之調整時脈訊號之方 4 本紙張尺度適用中國國家標準（CNS)A4規格（2.10 X 297公釐） -------------裝--------訂---------線 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 472455 A7 B7 7155twf. doc/006 五、發明說明（>) 法，包括決定對應一參考頻率之來自一被產生時脈訊號之 時脈訊號的數目，並選擇複數傳遞延遲裝置。 (請先閱讀背面之注意事項再填寫本頁) 爲決疋輸出訊號的頻率’輸出被與·一可由不昂貴的外 部石英振盪器所產生的參考訊號比較。被輸入的參考,頻率 爲已知。被產生的時脈訊號的數目在參考訊號的一個時脈 週期內被計算。然後裝置計算所產生的時脈訊號頻率而可 以於需要時改變頻率。本發明也揭露一時脈除法器用以進 一步調整被產生的時脈訊號。 因此，本裝置藉由提供一種低成本，可變化的頻率以 及不需要昂貴的高頻時脈產生器的裝置而解決了習知技術 的許多問題。 本發明這些以及其它的特徵於此處所附之申請專利範 圍中描述並形成此處之另一部份。然而，爲了本發明以及 經由使用本發明所產生的優點及目的的較佳了解，應該參 照本發明例示用之所附圖式及相對的描述。 -·線. 圖式簡要說明 第1圖是本發明時脈產生器之一實施例。 經濟部智慧財產局員工消費合作社印製 第2圖是調整所產生之時脈訊號頻率的流程。 第3圖是調整所產生之時脈訊號頻率的方法。 第4圖是本發明時脈觸發器之一實施例。 _ 5圖是用以計算所產生之時脈的時脈週期之時序 圖。 第6圖是本發明時脈產生器及調整方法之完整裝置之 5 本紙張尺度適用中國國家標準（CNShW規格（2丨〇 χ 297公釐） 472455 A7 B7 7155twf * doc/006 五、發明說明（斗） 實施例。 圖號說明 (請先閱讀背面之注意事項再填寫本頁) 10 NAND 20多工器 200計數器 310裝置 320裝置 詳細說明 在以下較佳實施例的詳細說明，於此處所附圖式中註 明參考標號’並藉由表示本發明可能實施之特定較佳說明 實施例而被顯示。該等較佳實施例所描述的細節足以讓熟 悉本技藝之人士能據以實施，並可以了解到在不脫離本發 明之精神及範圍下可有使用不同邏輯及改變的實施例。因 此，以下的描述將無限制之意，本發明之範圍將僅由所附 申請專利範圍所定義。 經濟部智慧財產局員工消費合作社印製 第1圖表示本發明裝置之時脈產生電路之一實施例。 該電路使用一閘的傳遞延遲以產生一時脈訊號，如果許多 的閘被連接在一起’則傳遞延池將是所有閘的傳遞延遲的 總和。在本發明之較佳實施例，多工器20被用來當成傳 遞延遲使用’但本技藝之人士可以使用其它具有傳遞延遲 的裝置。每個多工器20可以經由邏輯定址30被個別驅動 或禁驅動。然而，本技藝中之人士可以理解驅動定址可以 由許多不同的方法產生，包括使用處理器，開關，鎖定器， 暫存器等。 本紙張尺度適用中國國家標準（CNS)yVl規格（2丨〇 X 297公楚） 472455 A7 B7 7155twf·d〇c/〇06 五、發明說明（f ) (請先閱讀背面之注意事項再填寫本頁) 回到第1圖，第1圖表不~種包括複數可定址的多工 器20以及一 NAND 10的裝置。NAND 10之一輸fe被連接 到來自多工器20的輸出。NAND 10的輸出連接到多工器20 的輸入。致能En_GCLK連接至NAND 10的輸入並能驅動 或禁驅動時脈產生器。'在圖中我們設定每個MUX 20的傳 遞延遲是DMUX，而NAND 10的傳遞延遲是DNAND。如 果我們設定Mux_sel[N:l]爲x7FFFh(傳遞16 MUXs以及1 NAND閘），我們會有一個半週期時間相當於16*DMUX + 1*DNAND的時脈訊號。因此產生的時脈具有週期時間爲 2*(16*DMUX + 1*DNAND)。 閘的傳遞延遲將會被處理變化，操作溫度，電壓，接 線負載…等等所影響。因此要計算想要的頻率是很困難 的，所以精確的時脈頻率產生需要調整。於較佳實施例中， 參考頻率是一外部石英產生器。本技藝中之人士將理解到 任何的參考頻率將可使用外部源與例如處理器所有的內部 時脈的內部源二者。 經濟部智慧財產局員工消赀合作社印製 第2圖表示依據外部時脈訊號調整所產生的時脈訊號 的流程圖。此方法首先藉由選擇對應所需之延遲的複數裝 置來設定傳遞延遲110。在步驟120，裝置計算在一參考 時脈訊號的時間週期內有多少所產生的時脈訊號週期發 生。被產生的時脈頻率隨後藉由以已知的參考頻率的頻率 乘上一參考時脈內的週期數目而決定。在步驟丨3〇，裝置 決定所產生的時脈頻率是否在想要的範圍內。如果時脈頻 率位落入想要的範圍內則程式結束。如果時脈訊號未落入 7 本紙張尺度.通ϋ國ΐ家標準（CNS)A4規格（210 X 297公爱)---- 經濟部智慧財產局員工消費合作社印製 472455 A7 7155twf.doc/006 ^ 五、發明說明（^ ) 想要的範圍內則程式計算何種的傳遞延遲是需要的以達成 讓時脈訊號落入想要的範圍內。程式隨後回到步驟110。 第3圖表示結合以上方法用以較佳地調整所產生之時 脈的另一種方法。所產生的時脈（GCLK)以及一參考時脈 (PCLK)被輸入計數器200。參考時脈(PCLK)的頻率已知爲 [X]。計數器決定在一參考時脈訊號的時間週期內有多少所 產生之時脈訊號的週期，其被標示爲[η]。所產生之時脈的 頻率隨後可被決定。在步驟210，用以除所產生之時脈訊 號[g]以得到想要的頻率[f]的數字是[m]。除數[m]由以下方 程式決定： m=n*x/y 在步驟220,所產生的時脈訊號[g]被[m]除以便獲得想 要的時脈輸出頻率[y]。因爲除數是整數基底，爲了更多的 時脈輸入我們必須改變傳遞延遲以便達到接近整數的[m] 値。 第4圖表示依據本發明較佳實施例用以觸發所產生之 時脈訊號的計算的裝置。可參照第5圖以解釋時脈訊號的 關係。當Count_trig訊號被輸入裝置310時即驅動一個被 輸入裝置320的Need_Count訊號。一 AND閘被連接到裝 置310的致能。AND閘連接到二重置訊號，rest_，及 Rest_Count_trig。Rest_Count_trig 被想像爲一內部重置訊 號，而rest_可以是外部重置訊號。裝置320驅動對應PCLK 之時脈訊號週期之Eable_Count訊號。裝置320的致能連 8 I紙張尺度適用中國國家標準（CNS)A.l規格（210 X 297公釐) ' -----I------- I-----I 訂·!----- (請先閱讀背面之注意事項再填寫本頁) 472455 7155twf·doc/006 五、發明說明（f]) 接至重置訊號 rest_。Rest_Count-trig 訊號使 Need_Count 訊 號降爲低準位因此重置計數觸發。第5圖是對應第4圖裝 置之時序圖。 第6圖表示之前所有元件被結合在一想像裝置內。在 步驟610設定產生時脈訊號之頻率的傳遞延遲。在步驟620 產生時脈頻率。在步驟630，藉由使用參考頻率640決定 所產生之時脈訊號的頻率。在步驟650，如果所產生的頻 率是想要的則程式繼續。如果所產生的頻率需要被改變則 在步驟660決定新的傳遞延遲且程式回到步驟610。在步 驟660，一除數値被決定，然後所產生的訊號依據步驟670 的値被除。在步驟680輸出最後時脈訊號。 在不脫離本發明之精神及範圍的情況下可對本發明所 揭示之實施例做不同的修改。因此本發明係依所附之申請 專利範圍而定。 I--- - - - - - - - -- 1111111 · 11111111 I ! (請先閱讀背面之注意事項再填f:本頁) 經濟部智慧財產局員工消費合作社印製 本''氏張尺度相中關家標準（CNS)A‘l規格⑵ο X 297公釐）W455 A7 B7 7155twf.doc / 006 V. Description of the Invention (I) Field of the Invention The present invention relates to a clock signal generating device and a method for transmitting a clock signal, and particularly to a self-generated and adjusted internal clock when a clock is generated. Device for generating pulse signal and method for transmitting clock signal using the same. BACKGROUND OF THE INVENTION Many electronic devices require an oscillating signal or a clock signal 'for a clock program to achieve synchronization within the device. As electronic devices become more complex, there is a need for low-cost clock signal generating devices that can be used in low-cost electronic devices. Most electronic devices use a phase-locked loop or inverter loop to generate internal clock signals. As known to those skilled in the art, a phase lock loop (PLL) consists of a phase comparator, a loop filter, and a voltage control oscillator (VOC). A basic clock and a reference clock are input to the PLL. The phase comparator compares the phases of the basic clock and the reference clock and outputs a signal representing the phase difference between the basic clock and the reference clock. The phase furnace removes the high frequency components of the signal. The voltage-controlled oscillator outputs a frequency-varying clock corresponding to the output signal of the loop filter. Therefore, the VOC clock has an oscillation frequency corresponding to the output signal of the PLL. There are many disadvantages to the phase locked loop design. It takes time for the PLL to lock the signal, and it is susceptible to noise. It is limited by the operating frequency range, has high power consumption, complicated design, and is expensive to set up. Many designs also use inverter circuits to generate the clock signal. The inverter loop includes a plurality of inverters, and the input terminal of each inverter is connected to the output terminal. The inverter circuit has an input external clock and provides a series of offsets. The paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) ----- I ----- I- -------- Order ---- I — II 1 ^. (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 472455 A7 B7 7155twf · doc / 006 V. Description of the invention (of) Phase clock signal. This allows the generation of an internal clock with a higher frequency. The disadvantages of the inverter loop are the inaccurate frequency and the limited frequency range. In addition, both the PLL and the inverter loop require a high-frequency external frequency generator. These devices are expensive and increase the high frequency stress on the printed circuit board. Therefore, there is a need for a low-cost, wide frequency range, accurate frequency control, low power consumption, and an internal clock generator that does not require an expensive high-frequency clock generator. Comprehensive description of the invention The present invention includes a device capable of self-generating a clock signal internally and self-adjusting the clock through the use of a reference frequency, and a clock signal transmission method using the same. The device includes a plurality of transfer delay devices'. In one embodiment, it may be a multiplexer. The multiplexers can be individually selected to allow a signal to travel through it, or to allow signals to pass through. The device generates a clock signal by setting a logic state at the beginning of the transmission device. The signal then passes through the transmission devices. The time required for the signal to pass through the transmission device depends on the number of devices selected. After the signals pass through the devices, the logic state changes and then the program restarts. Therefore, signals can be generated by changing the logic state at the output of the device. By changing the number of transmission delay devices in the clock generator, the frequency of the clock signal can be changed. The method of adjusting the clock signal used by the clock generating device of the present invention 4 The paper size is applicable to the Chinese National Standard (CNS) A4 specification (2.10 X 297 mm) ------------- Packing -------- Order --------- line (please read the precautions on the back before filling this page) Printed by the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economy 472455 A7 B7 7155twf. Doc / Fifth, the invention (>) method includes determining the number of clock signals from a generated clock signal corresponding to a reference frequency, and selecting a complex transmission delay device. (Please read the notes on the back before filling out this page) To determine the frequency of the output signal, the output is compared with a reference signal that can be generated by an inexpensive external quartz oscillator. The entered reference, the frequency is known. The number of clock signals generated is counted during one clock period of the reference signal. The device then calculates the frequency of the generated clock signal and can change the frequency if needed. The invention also discloses a clock divider for further adjusting the generated clock signal. Therefore, the present device solves many problems of the conventional technology by providing a device which is low-cost, variable in frequency, and does not require an expensive high-frequency clock generator. These and other features of the invention are described in and form a further part of the patent application appended hereto. However, for a better understanding of the advantages and objectives of the present invention as well as through the use of the present invention, reference should be made to the drawings and the relative descriptions exemplified in the present invention. -·. Brief Description of the Drawings Figure 1 is an embodiment of the clock generator of the present invention. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Figure 2 is the process of adjusting the frequency of the generated clock signal. Figure 3 is a method of adjusting the frequency of the generated clock signal. Fig. 4 is an embodiment of a clock trigger according to the present invention. Figure 5 is a timing diagram for calculating the clock cycle of the generated clock. Fig. 6 is a complete device of the clock generator and adjusting method of the present invention. The paper size 5 is applicable to the Chinese national standard (CNShW specification (2 丨 〇χ 297 mm) 472455 A7 B7 7155twf * doc / 006. 5. Description of the invention ( Bucket) embodiment. Figure number description (please read the precautions on the back before filling out this page) 10 NAND 20 multiplexer 200 counter 310 device 320 device detailed description The detailed description of the preferred embodiment below, attached here The reference numeral 'is indicated in the formula and is shown by indicating specific preferred illustrative embodiments in which the present invention may be implemented. The details described in these preferred embodiments are sufficient for those skilled in the art to implement and understand There may be embodiments using different logic and changes without departing from the spirit and scope of the present invention. Therefore, the following description will have no meaning, and the scope of the present invention will be defined only by the scope of the attached patent application. Ministry of Economic Affairs Printed by the Intellectual Property Bureau employee consumer cooperative Figure 1 shows an embodiment of the clock generating circuit of the device of the present invention. This circuit uses a gate delay to generate Clock signal, if many gates are connected together, then the propagation delay pool will be the sum of the propagation delays of all the gates. In the preferred embodiment of the present invention, the multiplexer 20 is used as a propagation delay. Those skilled in the art can use other devices with transfer delays. Each multiplexer 20 can be individually or disabled driven by logical addressing 30. However, those skilled in the art can understand that driving addressing can be generated by many different methods, including Use processors, switches, latches, registers, etc. This paper size applies to the Chinese National Standard (CNS) yVl specification (2 丨 〇X 297 公 楚) 472455 A7 B7 7155twf · d〇c / 〇06 5. Description of the invention (F) (Please read the notes on the back before filling in this page) Back to Figure 1, the first chart does not include a device with multiple addressable multiplexers 20 and a NAND 10. One of NAND 10 loses Is connected to the output from multiplexer 20. The output of NAND 10 is connected to the input of multiplexer 20. Enable En_GCLK is connected to the input of NAND 10 and can drive or disable the clock generator. 'In the picture we set each The transfer delay of MUX 20 is DMUX, and the transfer delay of NAND 10 is DNAND. If we set Mux_sel [N: l] to x7FFFh (pass 16 MUXs and 1 NAND gate), we will have a half cycle time equivalent to 16 * DMUX + 1 * DNAND clock signal. The resulting clock has a cycle time of 2 * (16 * DMUX + 1 * DNAND). The transfer delay of the gate will be processed and changed, operating temperature, voltage, wiring load, etc. It is difficult to calculate the desired frequency, so the precise clock frequency generation needs to be adjusted. In a preferred embodiment, the reference frequency is an external quartz generator. Those skilled in the art will understand that any reference frequency will be able to use both external sources and internal sources such as the processor's internal clock. Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 2 shows the flowchart of the clock signal generated by adjusting the external clock signal. This method first sets the delivery delay 110 by selecting a plurality of devices corresponding to the required delay. At step 120, the device calculates how many clock signal cycles occur during a time period of a reference clock signal. The generated clock frequency is then determined by multiplying the frequency of the known reference frequency by the number of cycles in a reference clock. In step 丨 30, the device determines whether the generated clock frequency is within a desired range. If the clock frequency bit falls within the desired range, the program ends. If the clock signal does not fall into the 7-paper standard, it is compatible with the National Family Standard (CNS) A4 specification (210 X 297 public love)-printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 472455 A7 7155twf.doc / 006 ^ V. Description of the Invention (^) When the desired range is reached, the program calculates what kind of transmission delay is needed to achieve that the clock signal falls within the desired range. The program then returns to step 110. Fig. 3 shows another method combining the above methods to better adjust the generated clock. The generated clock (GCLK) and a reference clock (PCLK) are input to the counter 200. The frequency of the reference clock (PCLK) is known as [X]. The counter determines how many cycles of the clock signal are generated during a time period of the reference clock signal, which is marked as [η]. The frequency of the generated clocks can then be determined. In step 210, the number used to divide the generated clock signal [g] to obtain the desired frequency [f] is [m]. The divisor [m] is determined by the following equation: m = n * x / y In step 220, the generated clock signal [g] is divided by [m] to obtain the desired clock output frequency [y]. Because the divisor is an integer base, for more clock inputs we must change the propagation delay in order to reach [m] 接近 which is close to the integer. Fig. 4 shows a device for triggering the calculation of the generated clock signal according to a preferred embodiment of the present invention. Refer to Figure 5 to explain the relationship of the clock signals. When the Count_trig signal is input to the device 310, a Need_Count signal of the input device 320 is driven. An AND gate is connected to the enable of the device 310. The AND gate is connected to two reset signals, rest_, and Rest_Count_trig. Rest_Count_trig is imagined as an internal reset signal, while rest_ can be an external reset signal. The device 320 drives the Eable_Count signal corresponding to the clock signal period of the PCLK. The enabling paper size of the device 320 is based on the Chinese National Standard (CNS) Al specification (210 X 297 mm). '----- I ------- I ----- I Order ·! ----- (Please read the notes on the back before filling this page) 472455 7155twf · doc / 006 V. Description of the invention (f)) Connect to the reset signal rest_. The Rest_Count-trig signal lowers the Need_Count signal to a low level and the reset count is triggered. Fig. 5 is a timing chart corresponding to the device of Fig. 4. Fig. 6 shows that all components were previously integrated into an imaginary device. In step 610, a transmission delay of the frequency of the generated clock signal is set. A clock frequency is generated in step 620. In step 630, the frequency of the generated clock signal is determined by using the reference frequency 640. In step 650, if the generated frequency is desired, the routine continues. If the generated frequency needs to be changed, a new delivery delay is determined in step 660 and the program returns to step 610. In step 660, a divisor 値 is determined, and then the generated signal is divided according to 値 in step 670. In step 680, the last clock signal is output. Various modifications may be made to the embodiments disclosed by the present invention without departing from the spirit and scope of the present invention. Therefore, the present invention depends on the scope of the attached patent application. I -----------1111111 · 11111111 I! (Please read the precautions on the back before filling in f: this page) Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Zhongguanjia Standard (CNS) A'l Specification ⑵ο X 297 mm)