TW470884B - Parallel bus system capable of expanding peripheral devices - Google Patents

Abstract

The present invention provides a parallel bus system capable of expanding peripheral devices, which has a central processing unit, more than one peripheral devices, and a parallel bus for connecting to the central processing unit and the ore than one peripheral devices. The parallel has a line for use as a peripheral device selection line, another line for uses as a system clock line, and the other lines for forming the lines required by one byte of the system. The message type on the other lines include instruction byte, address byte and data byte. Generally, the other lines are used to first send instruction byte, next send address byte and then send data byte.

Description

^^ 0884

The present invention relates to a parallel bus system, in particular, to a parallel bus system that can be used as a peripheral device, which can be used by a system on a chip (Uysi: em chip) or other similar systems to expand its peripheral devices.

As shown in the first figure, the system on a general chip (System On Chip) already has a central processing unit n, a decoder 12, and a number of peripheral devices 13, 14, 15, etc. on a chip 1. The internal connection is CS1. , CS2, CS3, and bus 10 are all set. It is very difficult to use other peripheral devices when using it. If two chips are connected for expansion, not only the wiring is complicated, but the programming is very tedious. At present, the general serial bus system has the function of expanding peripheral equipment ', but because it is a serial bus system, the transmission of related commands and data is very slow. Therefore, it is an object of the present invention to provide a j 可 system capable of expanding peripheral devices. Related systems cooperate with such a parallel bus system design to easily expand required peripheral devices. Another object of the present invention is to enable peripheral devices in the proposed parallel bus system to control the bus as needed, so that peripheral devices can also control data transmission. ^ »Another object of the present invention is to make the proposed parallel bus system jgji

Page 4 470884 V. Description of the invention (with more than one central row. The processing unit can control the bus in a time-sharing manner. The first picture is the intention of the system on chip. The first picture It is a schematic diagram of an embodiment of the parallel bus system of the present invention. The figure is a schematic diagram of a parallel bus system with two central processing units of the present invention. The fourth diagram is a flowchart of the operation mode of the present invention. = Refer to the first figure, which is a schematic diagram of an embodiment of the parallel bus system of the present invention. A central processing unit 21 and a number of peripheral devices 22, 23, 24, ... are connected to each other by a parallel bus 20. Parallel bus Row 20 has ten lines (the number of lines is not limited in the present invention). The function of each line is shown in Table 1.

Table 1 Name Description ~ 8 CD0-CD7 Instruction characters, address characters, and data character transmission lines 9 SCLK system clock line 10 CSB Peripheral device selection line Page 5 V. Description of the invention (3) System clock line SCLK It is the line used to send the clock signal of the system to m ^ ^ ', M' · · · etc. from the center to the surroundings 22 2S 9/1. Bian Pei is connected; the communication line is more than the central processing unit 21 to notify all peripheral devices to notify all peripheral devices to accept messages. When the potential is low, the central processing unit 21 notifies all idle sides to send instructions on the ~~ CD7 line. After the Yuan Zhou's edge / bit rate is ready to receive the message, all the bits of the address character M + / 疋 W ^ 7 can be sent, followed by the bit 0 P, and then all the bits of the data character. Every week ^ ^ Begin to interpret these messages in order to work as directed. , So that the characters (8 bits) are first sent to the CD0 ~ CD7 line. In order for the peripheral device to know that this is the instruction character, the CDO line can be specified as 1 to represent the type of instruction character. Shown: Table instruction name CD0 ~ CD7 Description IDEN 11 00 IDO ~ ID3 Select peripheral device instruction COMBO 1101DA0 ~ DA3 Select instruction of peripheral device sub device M0DE1 11100001 Peripheral device is small memory instruction M0DE2 11100010 Peripheral device is large memory instruction NAUTO 11101000 Memory address in peripheral device does not increase or decrease automatically

Page 6 470884 V. Description of the invention (4) AUTOA1 11101100 Memory address in the peripheral device AUTOA2 11101101 Move 1 instruction Peripheral memory address white AUT0S1 11101110 Move 2 instruction Peripheral memory address white AUT0S2 11101111 Subtract 1 Instruction peripheral memory address WR1B 11110000 Subtraction 2 Instruction write 1 character data WR2B 11110001 Write 2 character data WR3B 11110010 Write 3 sub 7L data WR4B 11110011 Write 4 character data RMW1B 11110100 Overwrite after reading 1-character data RMW2B 11110101 Overwrite 2-character data after reading RMW3B 11110110 Overwrite 3-character data after reading RMW4B 11110111 Overwrite 4-character data after reading RFW1B 11111000 Read 1-character data after writing RFW2B 11111001 Read-write after reading 2-character data RFW3B 11111010 Read 3-character data after writing RFW4B 11111011 Read 4-character data after writing RD1B 11111100 Read 1-character data RD2B 11111101 Read 2-character data RD3B 11111110 Read 3-character data RD4B 11111111 Read 4-character data

Page 7 470884

REGISTER 1 0R5R4R3R2R1 R0 Select register command ^ The command character is usually more than one character (the character in this example is 8 bits). The first character .ID is IDEN, which indicates which peripheral device is ready to receive messages. The next four codes are the codes of the peripheral devices. In this example, 16 peripheral devices can be specified. Followed by COMBO or M0DE1, M0DE2 or NAUT0, AUT0A1, AUT0A2, AUT0S1, AUT0S2, etc. ’When using ^, it means that the designated peripheral device contains several sub-devices. 'The last four codes of COMBO specify the address of the sub-device. In this example, it can contain up to 16 sub-devices. M〇DE1, m〇〇e2 is used to determine whether the memory of the peripheral device is small or large; NAUT〇 is used to determine the memory in the peripheral device ^ Address is not automatically added or subtracted, if AUT0A1, AUT0A2, AUT0S1, or AUT0S2 ' Then subsequent data can be transmitted continuously without having to append instruction characters and address characters each time. One time, one of the remaining 16 read-write instruction characters is sent. The read-write characters are divided into four types as follows: 1 * The write instruction characters are not written by the central processing unit to the peripheral device. In this case, the data is from 0 person to 1 yuan to 4 characters, that is, WR1B, WR2B, WR3B, WR4B 〇2. After writing, write the characters ^ If the central processing unit wants to read the data in the peripheral device, add 1 # 马 入 The original address in the peripheral device, the type of data can be one word to four $-Yu Fan, namely RMW1B, RMW2B, RMW3B, RMW4B. d • Read characters after writing

470884

It means that the central processing unit wants to write data into the peripheral device and then read out to verify whether it is written correctly. The data type can be one character to four characters, namely RFW1B, RFW2B, RFW3B, RFW4B. 4 · Read command character Indicates that the central processing unit wants to read the data in the peripheral device. The data type can be one character to four characters, namely RD1B, RD2B, RD3b RD4B. ’’

The register selection instruction REGISTER is used to instruct the central processing unit to send data to the registers associated with the peripheral device for processing. The first two bits are 10, and the last six bits R5R4R3R2R1R0 can specify 64 registers. . After the instruction sub-element is sent, the address character is sent immediately, and the type of the address character is shown in Table 3. Table 3 Address instructions CD0 ~ CD7, CD0 ~ CD7, CD0 ~ CD7, description (address) 00A21-A16, A15-A8, A 7 to A 0, M0DE2: Address 4MB (Address) 010A20 to A16, A15 to A8, A 7 to A 0, M0DE2: Address 2MB (Address) 0110A19 to A16, A15 ~ A8, A 7 ~ A 0, M0DE2: Address 1MB (Address) Oil 10A18 ~ A16, A15 ~ A8, A7 ~ A0, M0DE2: Address 512KB (Address) 011110A17 ~ A16, A15 ~ A8, A7 -A0, M0DE2: Address 2 56KB (Address) 0111110A16, A15-A8, A 7 to A 0, Μ 0 DE 2: Address 1 28KB Page 9 470884 V. Description of the invention (7) (Address) 01111110 , (Address) 01111111, (address) 01111111, (address) 01111111, (address) 01111111, A15 to A8, A7 to A0, MODE2: address

64KB 0 A14 ~ A8, A7 ~ A0, MODE2: address

32KMB 10 A13 ~ Α8 ·, Α7 ~ AO, MODE2: Address 1 6KB 110 Α12 ~ Α8, Α7 ~ AO, MODE2: Address

8KB

1.110 All to A8, A7 to AO, MODE2: address

The address instruction of 4KB Table 3 is explained by a worm example. Three characters are continuously sent on the CD0 ~ CD7 lines. The predetermined bit value varies according to the size of the memory. If it is a 4MB memory, its first The first two bits of the character are specified as "〇〇". If it is 2MB of memory, the first three bits of the first character are specified as "〇 丨 〇", and so on. Please note that the first bit CD0 of an address character is set to 0 so that the first bit 4 of the address character is distinguished. If the command character is used in the command character, the address character only needs to send a ^^^ element, which means that the memory address is only 1 28 characters. After the address characters are sent, the data characters are sent out immediately, and the number has been specified by the aforementioned four read and write characters. After the data characters have been sent, the peripheral device selection line CSB goes high.

Page 10 470884 V. Description of the invention (8) Notify each peripheral The present invention controls the peripheral devices at appropriate timings Notify the other week Please see the second device with 33, 34 or a central processing The fourth figure to understand the present invention Size, logic class and form, can only be used only for example attached application

End this round of device messages. Peripheral devices can also be designed to cooperate with the central processing order _ to make this parallel bus, if you can actively control the peripheral equipment after the selection line CSB in the central processing order, stop the control early! Makeup, you can choose your device selection line CSB, Device accepts the message. The second picture is another parallel bus of the present invention-a kind of bear, Genyang processing units 31 and 32 can be arranged to control the phase cycle separately:, 35, as long as the parallel bus 30 is not controlled by the master, one of the central processing can be charged. The unit has priority and can interrupt the ^ unit and take control of this parallel bus. This is a flowchart of the operation mode of the present invention, from which the light operation steps can be performed. In the parallel bus system, there are no restrictions on the number of parallel lines, the sign of the characters, the order of the lines, the number of central processing units of the command character and the address character, and there is no limitation: System on Chip. The above examples show that it cannot be taken as a limitation, and the spirit and scope of the present invention should be based on the patent scope. mm ικηη page 11

Claims (1)

470884 6. The scope of the patent application: a parallel bus system with expandable peripheral devices, which has a central management unit, one or more peripheral devices, and one for connecting the central office: one or more The parallel buses of peripheral devices are characterized by: ^ There is a line on the distant parallel bus as the peripheral device selection line; • There is another line on the parallel bus as the system clock line; C. The other lines on the bus constitute The system needs one line of characters, and the message types flowing on the green include command characters, address characters, and data characters; ^ ^ de generally sends these other lines first on the bus The command $ to 70 ′ sends the address character, and then the data character. The system of item 1 in the patent application, in which the peripheral device selection line 疋 central processing unit notifies all peripheral devices whether to accept the message or not. Second > The system of item 1 of the patent scope, in which the command characters include more than one type of command character for selecting the peripheral position, which is used to indicate which peripheral device is connected to the subsequent address characters and data characters. . 4. The system according to item 1 of the scope of patent application, wherein the command characters include more than one command character for selecting a relevant register in a peripheral device. 5. According to the system of claim 1, the instruction characters include more than one instruction bit which determines the number of consecutive characters of the subsequent address characters, and is used to indicate how many subsequent address characters. 6. The system of item 1 in the scope of patent application, in which the command characters include more than one command character for automatically adding or subtracting the address of data to be stored in the peripheral device. Page 12 470884 Application for patent scope 7 · If the system of patent application No. 6 'in which the right uses far to specify the command characters for automatic addition and subtraction of the address of the data to be stored in the peripheral device, subsequent phases and data transmission can be saved Divide the command character and address character to speed up the transmission speed. For example, the backup station Gan Shi from the application scope of the patent application is from the entry --- read, write, read the system that Deshun once lost. Instruction elements include meta. There are 9 people in the four modes of instruction such as “comment”, “,” and “read-after-write”. ^ If-in the scope of patent application No. 8, the Z word can indicate the address to the system. Among these four modes, 70. There are several characters in the data characters at the back of the child. 10: If the scope of patent application is No. 8 1 Data reading in the peripheral device: Department: System, where the read instruction character is 11 Order characters. Write the relevant data into the peripheral device, 2 system, where the write instruction character 1 2 · Such as the instruction character of the eighth tool in the scope of patent application. The command character is a system that reads the peripheral setting \, in which the command character of the overwrite mode is read. The data in the center is processed and written into the original address. 13. If the eighth instruction in the scope of the patent application, the command character is the writer's system. The data in the center can be read out to make sure. 14 · For example, the scope of patent application 苐 1 work deduction 1 5 · For the scope of patent application} ^^ After sending the address character and data word ^ system, which should follow the instructions The peripheral device stopped accepting messages. After that, the peripheral device selection line will notify the 1 R member system such as wm ^ W _____ by i 軎, where the central processing unit 470884 6. Scope of patent application When the peripheral device selection line is not used, if each peripheral device has its own central processor, the peripheral device selection line can be used to control other peripheral devices to accept messages. 16. If the system of item 1 of the patent application scope, wherein the number of central processing units is greater than one, and all are connected to the parallel bus, time-sharing control of related peripheral devices can be arranged, or one of the central processing units has priority , Can interrupt another central processing unit and take control of this parallel bus. Page 14