[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

TW477029B - Method of reducing thick film stress of spin on dielectric and the resulting sandwich dielectric structure - Google Patents

Method of reducing thick film stress of spin on dielectric and the resulting sandwich dielectric structure Download PDF

Info

Publication number
TW477029B
TW477029B TW090103958A TW90103958A TW477029B TW 477029 B TW477029 B TW 477029B TW 090103958 A TW090103958 A TW 090103958A TW 90103958 A TW90103958 A TW 90103958A TW 477029 B TW477029 B TW 477029B
Authority
TW
Taiwan
Prior art keywords
dielectric layer
patent application
silicon dioxide
item
layer
Prior art date
Application number
TW090103958A
Other languages
English (en)
Inventor
Ching-Fa Ye
Yue-Chuan Li
Jr-Chiuan Shiu
Guo-Hau Wu
Shuo-Cheng Wang
Original Assignee
Nat Science Council
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nat Science Council filed Critical Nat Science Council
Priority to TW090103958A priority Critical patent/TW477029B/zh
Priority to US10/075,293 priority patent/US6774461B2/en
Application granted granted Critical
Publication of TW477029B publication Critical patent/TW477029B/zh
Priority to US10/893,263 priority patent/US6903029B2/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02131—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being halogen doped silicon oxides, e.g. FSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02137—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material comprising alkyl silsesquioxane, e.g. MSQ
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02329—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen
    • H01L21/02332—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen into an oxide layer, e.g. changing SiO to SiON
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/312—Organic layers, e.g. photoresist
    • H01L21/3121—Layers comprising organo-silicon compounds
    • H01L21/3122—Layers comprising organo-silicon compounds layers comprising polysiloxane compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02203—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being porous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
    • H01L21/02216—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H01L21/31629—Deposition of halogen doped silicon oxide, e.g. fluorine doped silicon oxide
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/26—Web or sheet containing structurally defined element or component, the element or component having a specified physical dimension
    • Y10T428/263—Coating layer not in excess of 5 mils thick or equivalent
    • Y10T428/264—Up to 3 mils
    • Y10T428/265—1 mil or less

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Formation Of Insulating Films (AREA)

Description

477029 A7 B7 五、發明說明（） 發明領域 本發明係關於一種降低旋塗式介電質厚膜應力的方 法及其所形成的三明治介電質結構。 發明背景 一般旋塗式（Spin on Di elec trie)介電質的應用很廣， 因爲旋塗式介電質技術主要是解決平坦度問題，使後續微 影過程中不易產生嚴重的景深（Depth of Focus)問題，提高 薄膜光蝕刻（Photo-patterning)準確度。爲了增進旋塗式介 電質之平坦度，通常須旋塗較厚的介電質，但介電質膜應 力將隨著旋塗厚度增加而變大，過大的厚膜應力會使得介 電質產生龜裂，漏電流大幅增加，介電質失去絕緣特性， 因此一般採用兩次旋塗（Double coating)的方式，以獲得較 厚的介電質。其次，低介電常數介電層的擋水能力及熱穩 定性通常不佳，有必要進一步提出改善。 申請人於我國發明專利申請第881 21 609號案（申請日 88年12月9日）提出一具有銅導線/阻障介電層/低-K介電質 溝槽結構的半導體元件及其製法，其中提出一種以液相沈 積之氟氧化矽（LPD FSG)經氨氣電漿（NH3 plasma)處理後 作爲銅導線之阻障介電層的新技術。該案的內容藉由參考 方式被倂入本案。 發明要旨 本發明提出一種利用液相沉積（LPD)之氟氧化矽 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) -—------訂--------- 經濟部智慧財產局員工消費合作社印製 477029 A7 B7 五、發明說明Γ ) (Fluorosilicate Glass，FSG)成長於介電質間，以降低旋塗 (請先閱讀背面之注意事項再填寫本頁) 式介電質厚膜應力的方法，避免旋塗式介電質因厚膜應力 過大而產生龜裂現象，亦可避免後續沈積於介電質上之薄 膜因介電質對其產生過大應力，致使沈積厚膜產生龜裂。 較佳地，將該氟氧化矽膜予以氮氣電漿處理，可使整層FSG 膜質氮化，阻擋可移動的離子穿透，有效提高熱穩定性及 水氣的遷移效應，使旋塗式介電質的可靠性大幅提升，並 使得旋塗式介電質在應用上更具潛力。 發明之詳細說明 本發明揭示一種降低旋塗式介電質厚膜應力的方 法，包含下列步驟： a) 於一基材上旋塗一第一介電層； b) 於該第一介電層上成長液相沈積二氧化矽層；及 c) 於該液相沈積二氧化矽層旋塗一第二介電層。 本發明同時亦揭示一種具有降低的厚膜應力的三明 治介電質結構，包含 經濟部智慧財產局員工消費合作社印製 一形成於一基材的第一介電層，其具有一介於至 700 nm的厚度； 一形成於該第一介電層上的液相沈積二氧化砂層，其 具有一介於5至100 nm的厚度；及 一形成於該液相沈積二氧化矽層的第二介電層，其具 一介於1〇〇至700 nm的厚度。 較佳的，該第一介電層及第二介電層爲選自氫倍半氧 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 477029 A7 — B7 五、發明說明（3 ) 石夕院（hydrogen si Is esquiuxane)或甲基倍半氧砂院（methyl silsesquioxane，以下簡稱MSQ)的低·Κ介電層。更佳的，該 第一介電層及第二介電層爲甲基倍半氧矽烷。 較佳的，該液相沈積二氧化矽層爲一含有6-10原子％ 的氟的含氟二氧化矽層。 較佳的，該液相沈積二氧化矽層爲一經過氮氣電漿處 理或氨氣電漿處理的液相沈積二氧化矽層，其具有3-50原 子％的氮及0.5-10原子。/〇的氟。 較佳的，該液相沈積二氧化矽層具有一介於10至30 nm的厚度。 較佳的，該第一介電層加第二介電層的厚度和介於 800至 1 200 nm 〇 較佳的，本發明方法於步驟c)之前進一步包含： b’）對所形成的基材/第一介電層/液相沈積二氧化矽 層結構施予一熱熟化（Curing)處理。更佳的，步驟b’）的熱 熟化處理包含係於一介於1 50至650°C的溫度的氮氣氣氛中 進行3 0分鐘至2小時的時間。 較佳的，本發明方法於步驟c)之前進一步包含： b’）將該液相沈積二氧化矽層施予一氮氣電漿處理或 氨氣電漿處理。更佳的，該氮氣電漿處理或氨氣電漿處理 係於25-400°C，10-800毫托，RF功率密度0.2-2 W/cm2及氮 氣或氨氣流速100-2000 sccm的條件下進行30秒至2小時。 較佳的，本發明方法的步驟b)包含將該基材浸入於一 個二氧化矽超飽和氫氟矽酸水溶液中一段時間，於是在該 -6- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） -------------- I.------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 477029 A7 ______ B7 五、發明說明（4 ) (請先閱讀背面之注意事項再填寫本頁) 第一介電層上形成一含氟二氧化矽層。較佳的，該二氧化 矽超飽和氫氟矽酸水溶液係藉由將一個二氧化矽飽和氫氟 矽酸水溶液加熱至其溫度昇高10°C以上而製備。更佳的， 該二氧化矽飽和氫氟矽酸水溶液的溫度爲0°C，而該二氧化 矽超飽和氫氟矽酸水溶液的溫度爲25t。較佳的，該二氧 化矽飽和氫氟矽酸水溶液係藉由將二氧化矽粉末加入一濃 度爲0.5-5.0M氫氟矽酸水溶液中，於〇它攪拌一段時間後並 過濾去除其中殘留的二氧化矽粉末而製備。 較佳的，本發明方法進一步包含於進行步驟c)的第二 介電層的旋塗之前，加熱烘乾步驟b)所成長的液相沈積二 氧化砂層。 較佳的，本發明方法進一步包含於進行步驟b’）的熱 熟化處理之前，加熱烘乾步驟b)所成長的液相沈積二氧化 石夕層。 較佳的，本發明方法進一步包含於進行步驟b，）的氮 氣電漿處理或氨氣電漿處理之前，加熱烘乾步驟b)所成長 的液相沈積二氧化矽層。 經濟部智慧財產局員工消費合作社印製 較佳的，本發明方法進一步包含於進行步驟c)的第二 介電層的旋塗之後，對所形成的基材/第一介電層/液相沈 積二氧化矽層/第二介電層結構施予一熱熟化處理。更佳 的，此熱熟化處理包含係於一介於150至650°C的溫度的氮 氣氣氛中進行3 0分鐘至2小時的時間。 對照例1 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） 477029 cl .士》 A7 B7 --yfcrj—i T ( (2001年12月修正） 圖1所示爲傳統旋塗式介電質所採用之兩次旋塗 (Double coating)結構，其製備方法包含於一砂基材1〇上採 用MSQ介電質旋塗二次，每次旋塗約500nm的厚度，並於 每次旋塗後，置於通氮氣之爐管中，進行400°C熟化（Curing) 30分鐘，得第一 MSQ介電質21及第二MSQ介電質22。 經濟部智慧財產局員工消費合作社印製 實施例1 將80克二氧化矽粉末加入1500毫升、4M的氫氟矽酸 (silicic acid，H2SiF6)溶液中，然後將此溶液置於0°C的恆溫 水槽中攪拌，形成矽酸的飽和溶液。之後將此飽和溶液予 以過濾、除去未能完全溶解的二氧化矽粉末，再將此溶液 靜置於25 °C的恆溫水槽中，利用升溫、溶液飽和度變化的 原理，使溶液達超飽和。此時的恆溫水槽溫度即爲FSG之 成長溫度。 於一矽基材1 0上採用MSQ介電質進行旋塗而形成一 厚度約500 nm的一第一 MSQ介電層21，再將所獲得的基材 /MSQ介電層結構浸入於該25°C的超飽和溶液中，開始於該 第一MSQ介電層21上成長LPD FSG 30至厚度約25 nm。於 此溫度下，沈積速率約20 nm/hr。取出該基材/MSQ介電層 / LPD FSG層結構，接著，進行180°C、250°C各一分鐘的烘 烤（Baking)，隨後置於通氮氣之爐管中，進行第一次熟化 (400°C、3 0分鐘），接著旋塗第二MSQ介電層22，並再進行 (第二次熟化400°C、30分鐘），於是|蒦得如圖2所示的結構。 (請先閱讀背面之注音？事項再填寫本頁)
本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 477029 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（6 ) 實施例2 除了不進行第一次熟化外，重覆實施例1的步驟，而 獲得基材/MSQ介電層/LPD FSG層/MSQ介電層結檫。 使用薄膜應力量測儀（Tencor FLX-2908)，以非破壞性 的方法，量測對照例1、實施例1及2製備方法中各步驟 的薄膜的內應力；該機台包括一 He-Ne雷射光源、反射鏡、 透鏡和定位感測器。藉著轉動反射鏡，雷射光會掃描在基 材表面，經定位感測器量測來自基材表面的反射光的偏移 量，如此可得基板的曲率。經分別量測得到基材鍍膜前後 之曲率半徑値R。、R後，由史東尼方式[Stoney 1 909]計算 求得薄膜的應力（σ ):
其中Es、ts、vs分別爲基材之楊氏係數、厚度及蒲松比 (Poisson ration)，tf則爲薄膜厚度。結果被示於圖3。 在圖3中發現，MSQ介電質間夾有LPD-FSG的實施例1 及2，其最終之厚膜應力分別爲53.9Mpa及44.4MPa ’明顯 較對照例1的傳統兩次旋塗法之70 MPa降低許多’顯見 LPD-FSG確有降低厚膜應力之功效。 於本發明的另一方案中，該第一 MSQ層上的厚度 2 511111之1^0-?80被置於一電槳輔助化學氣相沈積反應器 (P E C V D r e a c t 〇 r )中使用氮氣電獎將0吴質予以忍化’處理 參數如下：N 2流量是2 0 0 s · c. c · m.，實驗過程溫度是2 〇 0 °C ’ 上層基板溫度是25(TC，RF能量密度是W/cm2，氣壓是 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） n n i^i ϋ - ϋ n ϋ ϋ · ϋ I ϋ - I - ϋ ^1 一I ϋ - m ϋ n - I ·1 n L — (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 477029 A7 ------------B7_____ 五、發明說明（7 ) 400 mTorr，時間爲15 min。然後於LPD-FSG上第二次旋塗 MSQ，形成MSQ/LPD-FSG/MSQ之三明治結構’最後置於 通氮氣之爐管中，進行400°C熟化30分鐘。 圖4(a)與（b)是利用化學分析電子能譜儀分析LPD F S G有無經由氮氣電漿處理後膜質的表面成分與化學位移 情形。由圖4(a)係對氮原子鍵結（N Is)分析，我們可以發現 未經過氮氣電漿處理的LPD FSG(如虛線所示）無氮鍵結產 生。相對之下，有經過氮氣電漿處理的LPD FSG則在束縛 能爲397.4 eV有強度峰値（intense peak)出現，其範圍落在 3 96.97〜3 97.82 eV之間屬於氮氧化矽鍵結。再由圖4(b)矽原 子鍵結（Si 2p)圖中，我們觀察到未經過氮氣電漿處理的 LPD FSG所產生的強度峰値約在束縛能103.4 eV處，其鍵 結主要爲氧化矽鍵結（SiOx)。LPD FSG有經過氮氣電漿處理 產生的強度峰値約在1 02.2 eV處，此鍵結主要爲氮氧化矽 鍵結，由此可知LPD FSG在氮氣電漿處理後其強度峰値由 未處理前的103.4 eV變爲102.2 eV，這主要是原本膜質中的 矽氟鍵結（Si-F)與矽氧鍵結（Si-O)在氮氣電漿處理後’氮原 子滲入膜質中取代氧原子或是氟離子形成矽氮鍵結（Si_ N)。由於氮原子的電子親和力較氧原子與氟原子來的小’ 所以會造成峰値強度往束縛能小的地方位移。 圖5是利用化學分析電子能譜儀，對LPD FSG有無經 氮氣電漿處理後膜質中氮元素濃度的縱深分析。由圖中可 觀察到LPD FSG經過氮氣電漿處理後，氮元素從膜層的表 面到矽基板都可以偵測到，且濃度維持在20 atom %之上。 -10 - 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ----------------^ C請先閲讀背面之注意事頊存填寫本頁) Ί (2001年12月修正) 五、發明說明（） 然而沒有經過電漿處理的LPD FSG無法偵測出氮元素濃 度，大多維持在雜訊値左右，由圖4及圖5我們可以得知， LPD FSG經過氮氣電漿處理後有效地將氮元素均勻摻入膜 層中，且氮取代氧或氟，形成氮砂鍵，因此氮氣電槳處理 的效應不僅止於表面處理，而可達到整層膜質的氮化。 LPD-FSG及MSQ等介電質均爲Low-K介電質，一起使 用既可降低介電質之厚膜應力，又對降低RC延遲非常有 效，並可改善M S Q膜易吸水、熱穩定性不佳，容易使金屬 導線氧化甚至腐蝕的缺點，在未來的半導體製程中極有可 能被廣泛使用。 圖示說明及圖號說明： 圖1爲一以兩次旋塗法製備的傳統MSQ介電質厚膜之 剖視示意圖。 圖2爲一以本發明方法製備的三明治介電質厚膜之剖 視示意圖。 圖3爲本發明實施例1及2與對照例1所使用製備方法中 各步驟的膜應力。 圖4(a):經由化學分析電子能譜儀分析LPD FSG有無經 由氮氣電漿處理後膜質表面成分的N Is光譜。 圖4(b):經由化學分析電子能譜儀（ESCA)分析LPD FSG 有無經由氮氣電槳處理後膜質表面成分的Si 2p光譜。 圖5 ··經由化學分析電子能譜儀（ESCA)分析LPD FSG有 無經由氮氣電漿處理後膜質中氮元素濃度的縱深分析。 10..矽基材21,22..MSQ介電層30·.液相沉積之氟氧化矽(LPDFSG) -11 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ----------------------訂-------—線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製

Claims (1)

  1. 477029 A8 B8 C8 ________D8 __ 六、申請專利範圍 1 · 一種降低旋塗式介電質厚膜應力的方法，包含下列步 驟： (請先閱讀背面之注意事項再填寫本頁) a) 於一基材上旋塗一第一介電層； b) 於該第一介電層上成長液相沈積二氧化矽層；及 c) 於該液相沈積二氧化矽層旋塗一第二介電層。 2·如申請專利圍範圍第1項的方法，其於步驟c)之前進一 步包含： b’）對所形成的基材/第一介電層/液相沈積二氧化矽層結構 施予一熱熟化處理。 3 .如申請專利圍範圍第1項的方法，其於步驟c)之前進一 步包含： b ’）將該液相沈積二氧化矽層施予一氮氣電漿處理或氨氣 電漿處理。 4·如申請專利圍範圍第1項的方法，其中該第—介電層具 有一介於1 〇 〇至7 〇 〇 n m的厚度。 經濟部智总財4局員工消費合作社印製 5. 如申請專利圍範圍第1項的方法，其中該第二介電層具 有一介於1〇〇至700 nm的厚度。 6. 如申請專利圍範圍第4項的方法，其中該第一介電層加 桌一*介電層的厚度和介於800至1200 nm。 -12- 本紙張尺度適用中國國家標準（CNS ) A4規格Ϊ210Χ297公董）一 477029 A8 B8 C8 D8 六、申請專利範圍 (請先閱讀背面之注意事項再填寫本頁) 7. 如申請專利圍範第1項的方法，其中該液相沈積二氧化 矽層具有一介於5至100 nm的厚度。 8. 如申請專利圍範圍第7項的方法，其中該液相沈積二氧 化矽層具有一介於10至30 nm的厚度。 9. 如申請專利範圍第1項的方法，其中的第一介電層及第 二介電層爲選自氫倍半氧砂院（hydrogen silsesquiuxane)或 甲基倍半氧砂院（methyl silsesquioxane)的低-K介電層。 1 〇.如_請專利範圍第9項的方法，其中的第一介電層及第 二介電層爲甲基倍半氧矽烷。 1 1 .如申請專利範圍第1項的方法，其中步驟b)包含將該基 材浸入於一個二氧化矽超飽和氫氟矽酸水溶液中一段時 間，於是在該第一介電層上形成一含氟二氧化矽層。 經濟部智葸財/$局員工消費合作社印製 1 2.如申請專利範圍第1 1項的方法，其中的二氧化矽超飽 和氫氟矽酸水溶液係藉由將一個二氧化矽飽和氫氟矽酸水 溶液加熱至其溫度昇高1 〇它以上而製備。 i 3 .如申請專利範圍第1 2項的方法，其中該二氧化矽飽和 氫氟矽酸水溶液的溫度爲〇°C ’而該該二氧化矽超飽和氫氟 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 477029 A8 B8 C8 D8 六、申請專利範圍 矽酸水溶液的溫度爲25°C。 (請先閱讀背面之注意事項再填寫本頁} 1 4.如申請專利範圍第1 3項的方法’其中該二氧化砍飽和 氫氟矽酸水溶液係藉由將二氧化矽粉末加入一濃度爲0.5· 5.0M氫氟矽酸水溶液中，於〇°C攪拌一段時間後並過濾去 除其中殘留的二氧化砂粉末而製備。 1 5 .如申請專利範圍第11項的方法，其中步驟b)所形成的 含氟二氧化矽層含有6-10原子％的氟。 16. 如申請專利範圍第3項的方法，其中步驟b’）的氮氣電 漿處理或氨氣電漿處理係於25-400^，1 0-800毫托，RF功 率密度0.2-2 W/cm2及氮氣或氨氣流速1 00-2000 seem的條 件下進行30秒至2小時。 17. 如申請專利範圍第16項的方法，其中步驟b’）的氮氣電 漿處理或氨氣電漿處理使該含氟二氧化矽層具有3 - 5 0原子 °/。的氮及〇. 5 -1 〇原子％的氟。 經濟部智总財/$.局P'工消費合作社印製 18. 如申請專利範圍第2項的方法，其中步驟V)的熱熟化 處理包含係於一介於150至65(TC的溫度的氮氣氣氛中進行 30分鐘至2小時。 1 9.如申請專利範圍第1項的方法，其進一步包含於進行步 -14- 本紙張尺度適用中國國家標準（ CNS ) A4規格( 210X297公釐） ' 477029 A8 B8 C8 D8 六、申請專利範圍 驟C)的第一介電層的旋塗之前’加_供乾步驟b)所成長的 液相沈積二氧化矽層。 20·如申請專利範圍第2項的方法，其進一步包含於進行步 驟b’）的熱熟化處理之前，加熱烘乾步驟b)所成長的液相沈 積二氧化矽層。 2 1 ·如申請專利範圍第3項的方法，其進一步包含於進行步 驟b’）的氮氣電漿處理或氨氣電漿處理之前，加熱烘乾步驟 b)所成長的液相沈積二氧化矽層。 2 2 ·如申請專利範園第1項的方法，其進一步包含於進行步 驟c)的第二介電層的旋塗之後，對所形成的基材/第一介電 層/液相沈積二氧化矽層/第二介電層結構施予一熱熟化處 理。 23·如申請專利範圍第22項的方法，其中的熱熟化處理包 含係於一介於1 50至650°C的溫度的氮氣氣氛中進行30分鐘 至2小時。 24.--種具有降低的厚膜應力的三明治介電質結搆，包含 一形成於.一基材的第一介電層’其具有一介於1 〇 〇至7 0 0 n m 的厚度； 一形成於該第一介電層上的液相沈積二氧化矽層’其具有 -15- 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 、-口 經濟部智慧財產局員工消費合作社印製 經濟部智慧財/$.局員工消費合作社印製 477029 A8 B8 C8 D8 々、申請專利範圍 一介於5至100 nm的厚度；及 一形成於該液相沈積二氧化砂層的第二介電層，其具一介 於100至700 nm的厚度。 25.如申請專利範圍第24項的三明治介電質結構，其中的 第一介電層及第二介電層爲選自氫倍半氧矽烷（hydrogen silsesquiuxane)或甲基倍半氧石夕院（methyl silsesquioxane) 的低-K介電層。 2 6.如申請專利範圍第25項的三明治介電質結構，其中的 第一介電層及第二介電層爲甲基倍半氧矽烷。 27.如申請專利範圍第24項的三明治介電質結構’其中的 液相沈積二氧化矽層爲-含存6-10原子％的氟的含氟二氧 化矽層。 2 8 .如申請專利範圍第24項的三明治介電質結構，其中的 液相沈積二氧化矽層爲一經過氮氣電漿處理或氨氣電漿處 理的液相沈積二氧化矽層，其具有3-50原子％的氮及0.5-10 原子％的氟。 2 9.如申請專利圍範圍第24項的三明治介電質結構’其中 該液相沈積二氧化矽層具有一介於1〇至30 ^⑺的厚度。 -16- 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐Ί 一 一 (請先閱讀背面之注意事項再填寫本頁)
    477029 A8 B8 C8 D8 六、申請專利範圍 30.如申請專利圍範圍第24項的三明治介電質結構，其中 該第一介電層加第二介電層的厚度和介於800至1200 nm。 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財/!.局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐）
TW090103958A 2001-02-21 2001-02-21 Method of reducing thick film stress of spin on dielectric and the resulting sandwich dielectric structure TW477029B (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
TW090103958A TW477029B (en) 2001-02-21 2001-02-21 Method of reducing thick film stress of spin on dielectric and the resulting sandwich dielectric structure
US10/075,293 US6774461B2 (en) 2001-02-21 2002-02-15 Method of reducing thick film stress of spin-on dielectric and the resulting sandwich dielectric structure
US10/893,263 US6903029B2 (en) 2001-02-21 2004-07-19 Method of reducing thick film stress of spin-on dielectric and the resulting sandwich dielectric structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW090103958A TW477029B (en) 2001-02-21 2001-02-21 Method of reducing thick film stress of spin on dielectric and the resulting sandwich dielectric structure

Publications (1)

Publication Number Publication Date
TW477029B true TW477029B (en) 2002-02-21

Family

ID=21677414

Family Applications (1)

Application Number Title Priority Date Filing Date
TW090103958A TW477029B (en) 2001-02-21 2001-02-21 Method of reducing thick film stress of spin on dielectric and the resulting sandwich dielectric structure

Country Status (2)

Country Link
US (2) US6774461B2 (zh)
TW (1) TW477029B (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7109092B2 (en) 2003-05-19 2006-09-19 Ziptronix, Inc. Method of room temperature covalent bonding
US7357977B2 (en) * 2005-01-13 2008-04-15 International Business Machines Corporation Ultralow dielectric constant layer with controlled biaxial stress
US7265437B2 (en) * 2005-03-08 2007-09-04 International Business Machines Corporation Low k dielectric CVD film formation process with in-situ imbedded nanolayers to improve mechanical properties
WO2015059488A1 (en) * 2013-10-23 2015-04-30 Micromass Uk Limited Charge-stripping of multiply-charged ions

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2912457B2 (ja) * 1991-02-01 1999-06-28 日本板硝子株式会社 薄膜コンデンサ
US5567660A (en) * 1995-09-13 1996-10-22 Taiwan Semiconductor Manufacturing Company Ltd Spin-on-glass planarization by a new stagnant coating method
US5616233A (en) * 1996-05-01 1997-04-01 National Science Council Method for making a fluorinated silicon dioxide layer on silicon substrate by anodic oxidation at room temperature
US6090726A (en) * 1996-07-05 2000-07-18 National Science Council Pretreatment method of a silicon wafer using nitric acid
US5691240A (en) * 1996-11-20 1997-11-25 Mosel Vitelic Inc. Method for forming blanket planarization of the multilevel interconnection
US6187663B1 (en) * 1999-01-19 2001-02-13 Taiwan Semiconductor Manufacturing Company Method of optimizing device performance via use of copper damascene structures, and HSQ/FSG, hybrid low dielectric constant materials
US6461983B1 (en) * 1999-08-11 2002-10-08 Micron Technology, Inc. Method for pretreating a substrate prior to application of a polymeric coat
US6492257B1 (en) * 2000-02-04 2002-12-10 Advanced Micro Devices, Inc. Water vapor plasma for effective low-k dielectric resist stripping
US6294832B1 (en) 2000-04-10 2001-09-25 National Science Council Semiconductor device having structure of copper interconnect/barrier dielectric liner/low-k dielectric trench and its fabrication method
US6521524B1 (en) * 2001-02-07 2003-02-18 Advanced Micro Devices, Inc. Via filled dual damascene structure with middle stop layer and method for making the same

Also Published As

Publication number Publication date
US6774461B2 (en) 2004-08-10
US20020142580A1 (en) 2002-10-03
US20040258932A1 (en) 2004-12-23
US6903029B2 (en) 2005-06-07

Similar Documents

Publication Publication Date Title
KR100730633B1 (ko) 다공성 실리카 박막을 제조하기 위한 플라즈마 가공
JP4813737B2 (ja) 窒化ケイ素フィルムを形成するための超薄オキシニトリドのｕｖ前処理法
EP1265813B1 (en) Plasma processing for porous silica thin film
JP3568537B2 (ja) マイクロエレクトロニクス構造体用電子ビーム加工膜
US7611757B1 (en) Method to improve mechanical strength of low-K dielectric film using modulated UV exposure
JP2005503672A (ja) 多孔質低誘電率材料のプラズマ硬化法
WO2000051174A1 (en) A method of processing a polymer layer
JP2003503849A (ja) 基材上にフィルムを形成する方法及び装置
TW200426944A (en) Low dielectric constant insulating film and method of forming the same
Orlowski et al. Ultrafast laser‐induced oxidation of silicon: A new approach towards high quality, low‐temperature, patterned SiO2 formation
JPH098032A (ja) 絶縁膜形成方法
TW477029B (en) Method of reducing thick film stress of spin on dielectric and the resulting sandwich dielectric structure
JP6236709B2 (ja) シリコン窒化膜の製造方法及びシリコン窒化膜
TW200416937A (en) Semiconductor manufacturing device and the manufacturing method for the same
JPH1126449A (ja) 絶縁膜の成膜方法
JPH10242137A (ja) 基材上に不溶性コーティングを形成する方法
JPH06333917A (ja) 半導体ウエーハの酸化前処理方法
JP2004266068A (ja) 多孔質シリカ系薄膜の製造方法
Zhang et al. Low-temperature atomic hydrogen treatment of SiO2/Si structures
JP2636715B2 (ja) 半導体装置の製造方法
TW471032B (en) Deposition of insulation layer containing fluorinated silicate glass for the application of cap layer
JPH11111716A (ja) 半導体素子の絶縁膜及びその製造方法
JP2883333B2 (ja) 半導体装置の製造方法
JPH11274152A (ja) 半導体装置のｓｏｇ層形成方法
JP2004273786A (ja) 疎水性多孔質ｓｏｇ膜の作製方法

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees