476155 A7 67 3 8pif. doc/008 B7 五、發明說明（I ) 發明範圍 本發明是有關於一種半導體元件，且特別是有關於一 種在半導體元件中平行地具有複數個獨立的特徵電路之輸 入電路。 習知技藝 特徵電路是用在不同的目的上，例如，在封裝程序中 用以標示缺陷產品，以及用以辨識不同的產品以避免彼此 之間的混亂。 在以低頻爲介面的半導體產品中，一個輸入/輸出埠的 低頻特性是很少加以考慮的。然而，近來所發展的半導體 元件是在高頻或高速狀況下進行操作。熟悉此技藝者會知 道，高速的電子介面存在著不同且通常爲失真的特性。據 此，就必須在半導體產品於高速操作的時候，配備有可以 在高頻介面，例如：數億赫茲(Hz)，進行操作時能正確掌 控操作的輸入/輸出埠。在高速操作中的一個問題就是半導 體在高速介面下輸入/輸出的阻抗變化。有許多的解決技術 被提出來以減少與半導體產品之輸入/輸出埠的阻抗相關 的問題。 輸入埠的阻抗特性是與耦接到輸入埠上的內部訊號 線、電感、寄生電容，以及輸入緩衝區的電容有關。再者， 耦接到輸入埠或伴隨著輸入璋的電路(如：靜電放電器，波 形夾鉗電路，以及耦接測試電晶體），以及標示半導體產品 之特徵電路的寄生電容，通常是以增加輸入埠的電阻的方 式影響輸入埠的阻抗特性。 第1圖爲顯示一個傳統輸入電路的圖式。在此傳統輸 4 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 ▼ · ϋ 1· n ϋ ί «ϋ ϋ 一 _ 1 ϋ ϋ H ·ϋ I— n I I 1· ϋ n ϋ ^1 ϋ ϋ I ^1 n II ϋ I ^1 ϋ H I 1 ϋ n ϋ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 476155 A7 6738pif.doc/008 B7 五、發明說明（、 入電路中，第一，第二與第η個特徵電路110，112與114 具備有各自的輸入緩衝區1〇〇, 1〇2與1〇4以獲得大量的指 標。每一個特徵電路Π0，112與114包括有保險絲（如： 第2圖中的F20)，而這些保險絲是否切斷則決定了電流是 否會流入特徵電路110，112與114之中。 第2圖是顯示第1圖之輸入電路的一個單獨特徵電路 的圖形。此單獨特徵電路包括一個主要保險絲F20,以及Ν 型金屬氧化半導體（Metal-Oxide Semiconductor，MOS)電晶 體 MN21，MN22 與 MN23。每一個 NMOS 電晶體 MN21， MN22與MN23具有互相耦接的一個閘極與一個源極，並 以二極體的方式進行操作。NM0S電晶體MN21，MN22與 MN23是以串連的方式耦接。波形夾鉗電路208是位於輸 入璋INPUT1與輸入緩衝區200之間，用以補償施加到輸 入緩衝區200中的輸入訊號的波形。 儲存在個別特徵電路110之中的資訊，係藉由探測輸 入埠上的電壓所獲得，而當輸入璋上的電壓改變時，個別 特徵電路中就會有電流流動。如果主保險絲F20沒有切 斷’則當輸入埠上的電壓比電源供應電壓VDD還高出 NMOS電晶體MN21，MN22與MN23之臨界電壓的總和 時’電流就會在特徵電路110之中流動。在一個封裝的半 導體元件中，各種的資訊是以特徵電路中切斷或沒切斷的 保險絲組合來表示。 輸入/輸出埠所具有的阻抗，使得個別特徵電路110包 括了如同閘極重疊電容與NMOS電晶體MN23之接合電容 般的寄生電容。個別特徵電路11〇中的寄生電容在相關輸 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ϋ ϋ a— n I ϋ ϋ ϋ ϋ I ϋ ϋ ϋ ·ϋ ^1 · n ϋ I ϋ ϋ ϋ I ϋ ϋ ϋ 1 ϋ I 1 I ϋ a^i J ϋ n n ϋ ϋ ϋ ϋ n I ϋ < (請先閱讀背面之注意事項再填寫本頁) 476155 A7 6738pif.d〇c/〇〇8_B7 五、發明說明（々） 入埠以高速進行訊號交換時，會導致寄生效應的產生。 (請先閱讀背面之注意事項再填寫本頁) 因此，特徵電路通常使用的是低速度的輸入/輸出璋介 面。據此，在具有特徵電路的半導體元件中的傳統輸入電 路，就會因爲在高速介面下有高阻抗而限制了可得的指標 數量。 再者，一個傳統的個別特徵電路無法與波形夾鉗電路 208 —起使用。波形夾鉗電路208係用來在一個預定的範 圍內，對輸入訊號的波形進行補償，且通常是用在一個半 導體元件內的一個輸入元件上。一般的波形夾鉗電路對於 比外部電源供應電壓VDD高出1VT(VT是在波形夾紺電路 中之電晶體的臨界電壓）的訊號，以及比外部接地電壓VSS 低1VT的訊號進行夾鉗。舉例來說，當有一個比外加電源 供應電壓VDD還高超過1VT的電壓被加在輸入埠INPUT1 之上的時候，波形夾鉗電路208的一個電晶體就會打開， 而電流就會改道至此波形夾鉗電路中。因此，在個別特徵 電路110中所流動的電流是無法探測的。 因此，對於一個可以減少輸入/輸出埠的阻抗，且可以 在半導體元件中與波形夾鉗電路一起使用的特徵電路就是 必須要的。 經濟部智慧財產局員工消費合作社印製 爲了解決上述的問題，本發明的一個目的就是提供一 種在半導體元件中的輸入電路，其用以獲得大量的指標 (index)，並且可以在高頻下進行訊號交換（interfacing)。 本發明的另一個目的是提供一種特徵電路，其可以與 提供給半導體元件之輸入埠所使用的波形夾鉗電路一起使 用。 ， 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 476155 A7 6738pif.doc/008 B7 五、發明說明（十） 據此，爲了達成上述及本發明其他的目的’就在具有 用以將施加到輸入璋上的訊號傳播到一個輸入緩衝區之輸 入線的一個半導體元件中，提供了一個個別特徵電路。二 或多個個別特徵電路平行的耦接在輸入線以及一個預定電 壓節點之間，並且對應於一個預定的控制訊號而被選擇性 的致能。一個個別特徵電路包括一個指標器（indexer)與一 個選擇器（selector)，並以串連的方式耦接在電壓節點與輸 入線之間。 較佳的是，選擇器的兩接點對應於控制訊號而短路或 斷路，且指標器包括一或多個電壓削減元件（voltage reducing device)以及特徵保險絲，電壓削減元件以串連的 方式耦接於指標器的輸入與輸出端之間，而每一特徵保險 絲則與相對應的電壓削減元件平行的耦接。如此，在指標 器上的電壓降就會隨著特徵保險絲切斷或不切斷的組合而 改變。 較佳的是，指標器可以包括一或多個可變電阻以及特 徵保險絲，可變電阻在指標器的輸入與輸出兩端之間以串 連锅接’而特徵保fe絲則與相對應的一個可變電阻平行稱 接。如此，在指標器的輸入與輸出端之間流動的電流總量， 就會隨著特徵保險絲切斷或不切斷的組合而改變。 較佳的是，指標器可以包括一或多個可變電阻以及特 徵保險絲’可變電阻於指標器的輸入與輸出端之間平行耦 接，而每一個特徵保險絲則與相對應的一個可變電阻串連 耦接。如此，在指標器的輸入與輸出端之間流動的電流總 量，就會隨著特徵保險絲切斷或不切斷的組合而改變。 7 -----------·裝！[_訂---------線--------------------- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 476155 A7 B7 6738pif.d〇c/〇〇g 五、發明說明（匕） (請先閱讀背面之注意事項再填寫本頁) 較佳的是，指標器可以包括一或多個電壓削減元件以 及特徵保險絲，電壓削減元件以串連的方式耦接於指標器 的輸入與輸出端之間，而每一特徵保險絲則與不同數量的 電壓削減元件平行的耦接。如此，橫跨指標器而以不同數 目的電壓削減元件所決定的電壓降，就會隨著特徵保險絲 切斷或不切斷的組合而改變。 藉由使用根據本發明之具有一或多個個別特徵電路的 一個輸入電路，在以高速操作的半導體元件中的各種資訊 就可被加以標示（indexed)。此外，本發明中的個別特徵電 路可以與半導體元件之輸入璋中所提供的波形夾鉗電路一 起使用。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂’下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下： 圖式之簡單說明： 第1圖繪示的是顯示在一個半導體元件中的傳統輸入 電路的電路圖； 第2圖繪示的是顯示第丨圖之輸入電路中的一個個別 特徵電路的電路圖； 經濟部智慧財產局員工消費合作社印製 第3圖繪示的是根據本發明之一半導體元件的一個輸 入電路的一個較佳實施例； 第4圖繪示的是根據本發明之一輸入電路的一個個別 特徵電路的一個較佳實施例； 第5圖繪示的是根據本發明之一輸入電路的一個個別 特徵電路的第二較佳實施例； 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 x 297公爱） 476155 A7 B7 673 8pif. doc/00 8 五、發明說明（c) 第6圖繪示的是根據本發明之一輸入電路的一個個別 特徵電路的第三較佳實施例； (請先閱讀背面之注意事項再填寫本頁) 第7圖繪示的是根據本發明之一輸入電路的一個個別 特徵電路的第四較佳實施例； 第8圖繪示的是根據本發明之一輸入電路的一個個別 特徵電路的第五較佳實施例； 第9圖繪示的是根據本發明之一輸入電路的一個個別 特徵電路的第六較佳實施例； 第10圖繪示的是根據本發明之一輸入電路的一個個 別特徵電路的第七較佳實施例； 第11圖繪示的是根據本發明之一輸入電路的一個個 別特徵電路的第八較佳實施例； 第12圖繪示的是根據本發明之一輸入電路的一個個 別特徵電路的第九較佳實施例；以及 第13圖繪示的是根據本發明之一輸入電路的一個個 別特徵電路的第十較佳實施例。 圖式的標號說明 100，102，104，200 :輸入緩衝區 110，112，114，311-313 :個別特徵電路 經濟部智慧財產局員工消費合作社印製 208 :波形夾鉗電路 300 :慢速輸入緩衝區 301，303，305，307 ··波形夾紺電路 302，304，306 :高速輸入緩衝區 315 :輸入線 420，520，620，720，820，920，1020，1120，1220，1320 : 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 476155 A7 6738pif.doc/008 B7 五、發明說明（9) 指標器 430，530，630，730，830，930，1030 ’ 1130，1230，1330 : 選擇器 F20，F40，F50，F60，F84，F125 :主要保險絲 F41-F43，F51-F53，F61-F63，F81-F83，F91-F93，F101-F103，F111-F113，F121-F124，F134-F137 :特徵保險絲 MN2卜MN23，MN41-MN43，MN51-MN53，MN61-MN63， MN81-MN83，MN101-MN103，MN121-MN124，MN131-MN134 : NMOS 電晶體 MP90-MP93，MP111-MP113 : PMOS 電晶體 MP40，MN50，MP60，MN70，MN80，MN100 :主要電晶 體 INPUT1，INPUT2，INPUT3，INPUTn :輸入埠 SEL1，SEL2，SEL3 :控制訊號 較佳實施例 本發明將在此之後參考所附圖式，藉由解釋本發明之 較佳實施例以詳細說明。在這些圖式中，相同的參考標號 標示了相同的元件。 第3圖繪示的是根據本發明之半導體元件的輸入電路 的一個較佳實施例。第3圖的輸入電路包括數條輸入線， 這些輸入線分別將輸入到輸入璋INPUT1，INPUT2， INPUT3··· INPUTn的訊號傳輸到輸入緩衝區300，302， 3〇4…306之中，而且還有一或多個特徵電路311，312與 313平行地耦接在一條輸入線315以及一個預定電壓節點 VSS之間。個別特徵電路311，312與313分別回應於控制 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -------------- (請先閱讀背面之注音？事項再填寫本頁) I l·---訂 i 經濟部智慧財產局員工消費合作社印製 線 I ----------------------- 經濟部智慧財產局員工消費合作社印製 476155 A7 _ 6738pif.doc/008 B7 五、發明說明（¾ ) 訊號SEL1，SEL2與SEL3而被致能。爲了淸楚的說明， 以相對低速來要求進丫了日只5虎父換（interfacing)的稱接璋被 稱爲慢速輸入緩衝區300，而以相對高速來要求進行訊號 交換的耦接埠則稱爲高速輸入緩衝區302，304或306。 在第3圖的輸入電路中’一或多個個別特徵電路311， 312與313是平行耦接在慢速輸入緩衝區300的輸入線315 與電壓節點VSS之間，而並沒有爲快速輸入緩衝區302， 304與306提供個別特徵電路。以平行方式耦接的個別特 徵電路311，312與313，會分別回應於控制訊號SEL1， SEL2與SEL3而被加以致能。 指標(index)資訊的讀取方法爲，多個個別特徵電路中 的一個被予以致能，而當輸入線315上的電壓改變時，就 探測在此被致能的個別特徵電路之中，電流開始流動時的 電壓。舉例來說，當要讀取第一個別特徵電路311的指標 資訊的時候，控制訊號SEL1，SEL2與SEL3的施加方式 就要使得只有此第一個別特徵電路311爲致能，而其他的 個別特徵電路312與313則不予致能(disable)。之後，施 加到輸入埠INPUT1之上的電壓會改變，而在此被致能的 第一個別特徵電路311之中，電流開始流動時的電壓就會 被加以探測。在讀取完此第一個別特徵電路311的指標資 訊之後，控制訊號SEL1與SEL2的施加方式就使得第一個 別特徵電路311不予致能，而第二個別特徵電路則成爲致 能的狀態。 在循序致能所有的個別特徵電路，並且取得所有需要 的資訊之後，就不予致能所有的個別特徵電路，312 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------------裝-----r---訂---------線丨 •----------------- (請先閱讀背面之注意事項再填寫本頁) 476155 A7 _ 6738pif.doc/008 B7 五、發明說明（q) 與313。因此，所有的個別特徵電路311 ’ 312與313就不 會在半導體元件的正常模式下操作。據此，即使在半導體 元件以高速進行訊號交換的時候，在半導體元件內的輸入 埠的阻抗也不會受到影響。 波形夾鉗電路301，303，305與307耦接到輸入緩衝 區300，302，304與306，以分別修正施加在這些輸入緩 衝區上的訊號的波形。 施加在個別特徵電路311，312與313之上的外部電壓 最好是接地電壓VSS，因爲如果此外部電壓是一個電源供 應電壓VDD的話，在要探測個別特徵電路中的電流開始流 動時的電壓的時候，還必須施加高於此外部電源供應電壓 的一個電壓才行。此外，既然在個別特徵電路中所流動的 電流可以在波形夾鉗電路301還未操作的時候探測到(在電 流流經波形夾鉗電路301之前），個別特徵電路就可以與波 形夾鉗電路一起使用。 更佳的是，控制訊號SEL1，SEL2與SEL3中的每一 個都是具有輸入電路之半導體元件中的模式暫存器組 (MRS，mode register set)訊號。當一個控制訊號是一個模 式暫存器組訊號的時候，就不需要用以產生此控制訊號的 特殊電路。 在第3圖中，快速輸入緩衝區302, 304與306以及慢 速輸入緩衝區300並不是絕對的判定，而是根據施加在半 導體元件之每個輸入埠上訊號的頻率而相對判定的。換句 話說，一或多個個別特徵電路係耦接到施加相對低速訊號 的一個低速輸入緩衝區上，而在施加相對高速訊號的一個 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製476155 A7 67 3 8pif. Doc / 008 B7 V. Description of the invention (I) Scope of the invention The invention relates to a semiconductor element, and in particular to an input circuit having a plurality of independent characteristic circuits in parallel in the semiconductor element . Known techniques Characteristic circuits are used for different purposes, for example, to mark defective products in a packaging process, and to identify different products to avoid confusion with each other. In semiconductor products with a low-frequency interface, the low-frequency characteristics of an input / output port are rarely considered. However, recently developed semiconductor devices operate at high frequency or high speed. Those skilled in the art will know that high-speed electronic interfaces have different and often distorted characteristics. Therefore, when semiconductor products are operated at high speeds, they must be equipped with input / output ports that can accurately control the operation when operating at high-frequency interfaces, such as hundreds of millions of hertz (Hz). One problem in high-speed operation is the impedance variation of the input / output of the semiconductor at the high-speed interface. Many solutions have been proposed to reduce the problems associated with the impedance of the input / output ports of semiconductor products. The impedance characteristics of the input port are related to the internal signal lines, inductance, parasitic capacitance, and capacitance of the input buffer coupled to the input port. In addition, the parasitic capacitance of circuits that are coupled to the input port or accompanied by input chirps (such as electrostatic dischargers, waveform clamp circuits, and test transistor couplings) and characteristic circuits that indicate semiconductor products are usually increased. The resistance of the input port affects the impedance characteristics of the input port. Figure 1 is a diagram showing a conventional input circuit. Lose 4 in this tradition (please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ▼ · ϋ 1 · n ϋ ί «ϋ ϋ 一 _ 1 ϋ ϋ H · ϋ I— n II 1 · ϋ n ϋ ^ 1 ϋ ϋ I ^ 1 n II ϋ I ^ 1 ϋ HI 1 ϋ n ϋ This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) Employees of Intellectual Property Bureau, Ministry of Economic Affairs Printed by the consumer cooperative 476155 A7 6738pif.doc / 008 B7 V. Description of the invention (in the circuit, the first, second and n-th characteristic circuits 110, 112 and 114 have their own input buffers 100, 1 〇2 and 104 to obtain a large number of indicators. Each of the characteristic circuits Π0, 112, and 114 includes fuses (such as: F20 in Figure 2), and whether these fuses are cut off determines whether current will flow into the characteristic circuit. 110, 112, and 114. Figure 2 is a diagram showing a separate characteristic circuit of the input circuit of Figure 1. This separate characteristic circuit includes a main fuse F20, and an N-type metal-oxide semiconductor (MOS) ) Transistors MN21, MN22 and MN23. Each NMOS transistors MN21, MN22 and MN23 have a gate and a source coupled to each other and operate as a diode. NMOS transistors MN21, MN22 and MN23 are coupled in series. Waveform clip The clamp circuit 208 is located between the input 璋 INPUT1 and the input buffer 200 to compensate the waveform of the input signal applied to the input buffer 200. The information stored in the individual characteristic circuit 110 is detected by the input port Obtained when the voltage on input 璋 changes, current will flow in individual characteristic circuits. If the main fuse F20 is not cut off, then the voltage on the input port is higher than the power supply voltage VDD by NMOS. When the sum of the threshold voltages of the crystals MN21, MN22 and MN23, the current will flow in the characteristic circuit 110. In a packaged semiconductor device, various information is based on a combination of fuses that are cut or not cut in the characteristic circuit. The impedance of the input / output port makes the individual characteristic circuit 110 include the parasitic capacitance like the junction capacitance of the gate overlap capacitor and the NMOS transistor MN23. The parasitic capacitance in the individual characteristic circuit 11o applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) at the relevant paper size. Ϋ ϋ a— n I ϋ ϋ ϋ I ϋ ϋ ϋ · ϋ ^ 1 · n ϋ I ϋ ϋ ϋ I ϋ ϋ ϋ 1 ϋ I 1 I ϋ a ^ i J ϋ nn ϋ ϋ ϋ I n I ϋ < (Please read the notes on the back before filling this page) 476155 A7 6738pif.d. c / 〇〇8_B7 V. Description of the invention (々) When entering a port for high-speed signal exchange, parasitic effects will occur. (Please read the notes on the back before filling this page.) Therefore, low-speed input / output interface is usually used for the characteristic circuit. According to this, the conventional input circuit in a semiconductor device with a characteristic circuit will limit the number of indicators available due to the high impedance in the high-speed interface. Furthermore, a traditional individual characteristic circuit cannot be used together with the waveform clamp circuit 208. The waveform clamp circuit 208 is used for compensating the waveform of an input signal within a predetermined range, and is usually used for an input element within a semiconductor element. The general waveform clamp circuit clamps a signal that is 1VT higher than the external power supply voltage VDD (VT is the threshold voltage of the transistor in the waveform clamp circuit) and a signal that is 1VT lower than the external ground voltage VSS. For example, when a voltage higher than the external power supply voltage VDD exceeds 1VT is applied to the input port INPUT1, a transistor of the waveform clamp circuit 208 is turned on, and the current is redirected to this waveform. In the clamp circuit. Therefore, the current flowing in the individual characteristic circuit 110 cannot be detected. Therefore, a characteristic circuit which can reduce the impedance of the input / output port and can be used with a waveform clamp circuit in a semiconductor device is necessary. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. In order to solve the above-mentioned problems, an object of the present invention is to provide an input circuit in a semiconductor element, which is used to obtain a large number of indexes and can be performed at high frequencies. Signal exchange (interfacing). Another object of the present invention is to provide a characteristic circuit which can be used with a waveform clamp circuit provided to an input port of a semiconductor element. , This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 476155 A7 6738pif.doc / 008 B7 V. Description of invention (ten) According to this, in order to achieve The above and other objects of the present invention 'provide an individual characteristic circuit in a semiconductor element having an input line for propagating a signal applied to an input chirp to an input buffer. Two or more individual characteristic circuits are coupled in parallel between the input line and a predetermined voltage node, and are selectively enabled corresponding to a predetermined control signal. An individual characteristic circuit includes an indexer and a selector, and is coupled in series between the voltage node and the input line. Preferably, the two contacts of the selector are short-circuited or open-circuited corresponding to the control signal, and the indicator includes one or more voltage reducing devices and characteristic fuses, and the voltage reducing components are coupled in series. Between the input and output terminals of the indicator, each characteristic fuse is coupled in parallel with the corresponding voltage reduction element. In this way, the voltage drop across the indicator will change with the combination of characteristic fuses being cut or not cut. Preferably, the indicator may include one or more variable resistors and characteristic fuses. The variable resistor is connected in series between the input and output ends of the indicator, and the characteristic protection wire is corresponding to A variable resistor is connected in parallel. In this way, the total amount of current flowing between the input and output terminals of the indicator will change with the combination of whether the characteristic fuse is cut or not. Preferably, the indicator may include one or more variable resistors and characteristic fuses. The variable resistors are coupled in parallel between the input and output terminals of the indicator, and each characteristic fuse is corresponding to a variable The resistors are coupled in series. In this way, the total amount of current flowing between the input and output of the indicator will change with the combination of the characteristic fuse being cut or not. 7 ----------- · Install! [_Order --------- Line --------------------- (Please read the precautions on the back before filling this page) This paper size Applicable to China National Standard (CNS) A4 specification (210 X 297 mm) 476155 A7 B7 6738pif.d〇c / 〇〇g 5. Description of invention (dagger) (Please read the precautions on the back before filling this page) Better The indicator can include one or more voltage reduction elements and characteristic fuses. The voltage reduction elements are coupled in series between the input and output terminals of the indicator, and each characteristic fuse is connected to a different amount of voltage. Cut parallel coupling of components. In this way, the voltage drop determined by the voltage reduction element with different numbers across the indicator will change depending on whether the characteristic fuse is cut or not. By using an input circuit having one or more individual characteristic circuits according to the present invention, various kinds of information in a semiconductor device operating at a high speed can be indexed. In addition, the individual characteristic circuit in the present invention can be used together with the waveform clamp circuit provided in the input of the semiconductor element. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following describes a preferred embodiment in conjunction with the accompanying drawings, which are described in detail as follows: Brief description of the drawings: FIG. 1 Shown is a circuit diagram of a conventional input circuit displayed in a semiconductor element; Figure 2 shows a circuit diagram showing an individual characteristic circuit in the input circuit of Figure 丨; printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs FIG. 3 illustrates a preferred embodiment of an input circuit of a semiconductor device according to the present invention; FIG. 4 illustrates a preferred embodiment of an individual characteristic circuit of an input circuit according to the present invention; FIG. 5 shows a second preferred embodiment of an individual characteristic circuit of an input circuit according to the present invention; the paper size is applicable to the Chinese National Standard (CNS) A4 specification (21 × x 297 public love) 476155 A7 B7 673 8pif. Doc / 00 8 V. Description of the Invention (c) Figure 6 shows a third preferred embodiment of an individual characteristic circuit of an input circuit according to the present invention; (please read first Note on the back, please fill in this page again) Figure 7 shows a fourth preferred embodiment of an individual characteristic circuit of an input circuit according to the present invention; Figure 8 shows an input circuit according to the present invention A fifth preferred embodiment of an individual characteristic circuit according to the invention; FIG. 9 shows a sixth preferred embodiment of an individual characteristic circuit of an input circuit according to the invention; FIG. 10 shows an embodiment according to the invention A seventh preferred embodiment of an individual characteristic circuit of an input circuit; FIG. 11 illustrates an eighth preferred embodiment of an individual characteristic circuit of an input circuit according to the present invention; FIG. 12 illustrates It is a ninth preferred embodiment of an individual characteristic circuit of an input circuit according to the present invention; and FIG. 13 shows a tenth preferred embodiment of an individual characteristic circuit of an input circuit according to the present invention. 100, 102, 104, 200 of the drawings: Input buffers 110, 112, 114, 311-313: Individual characteristic circuits Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 208: Waveform clamp circuit 300: Slow input Buffers 301, 303, 305, 307. Waveform clamp circuits 302, 304, 306: High-speed input buffers 315: Input lines 420, 520, 620, 720, 820, 920, 1020, 1120, 1220, 1320: This Paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 476155 A7 6738pif.doc / 008 B7 V. Description of the invention (9) Indicator 430, 530, 630, 730, 830, 930, 1030 '1130 , 1230, 1330: Selectors F20, F40, F50, F60, F84, F125: Main fuses F41-F43, F51-F53, F61-F63, F81-F83, F91-F93, F101-F103, F111-F113, F121 -F124, F134-F137: Characteristic fuses MN2, MN23, MN41-MN43, MN51-MN53, MN61-MN63, MN81-MN83, MN101-MN103, MN121-MN124, MN131-MN134: NMOS transistors MP90-MP93, MP111- MP113: PMOS transistors MP40, MN50, MP60, MN70, MN80, MN100: main transistors INPUT1, INPUT2, INPUT3, I NPUTn: input ports SEL1, SEL2, SEL3: control signals. Preferred embodiments The present invention will be described in detail below with reference to the accompanying drawings, by explaining the preferred embodiments of the present invention. In these drawings, the same reference numerals indicate the same elements. Fig. 3 shows a preferred embodiment of an input circuit of a semiconductor device according to the present invention. The input circuit in FIG. 3 includes several input lines, and these input lines respectively transmit the signals input to the inputs 璋 INPUT1, INPUT2, INPUT3, ..., INPUTn to the input buffers 300, 302, 304 ... 306, and There are also one or more characteristic circuits 311, 312 and 313 coupled in parallel between an input line 315 and a predetermined voltage node VSS. Individual characteristic circuits 311, 312, and 313 responded to the control of this paper's size by applying the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -------------- (Please read the back first Phonetic notation? Please fill out this page for more information.) I l · --- Order i Print line for consumer cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs I --------------------- -Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 476155 A7 _ 6738pif.doc / 008 B7 V. Description of the invention (¾) The signals SEL1, SEL2 and SEL3 were enabled. For the sake of clarification, a relatively low-speed connection is required. The connection interface of the 5 tigers is referred to as a slow input buffer 300, and a relatively high-speed coupling port is required for signal exchange. They are called high-speed input buffers 302, 304, or 306. In the input circuit of FIG. 3, one or more of the individual characteristic circuits 311, 312, and 313 are coupled in parallel between the input line 315 of the slow input buffer 300 and the voltage node VSS, and there is no buffer for the fast input. Regions 302, 304, and 306 provide individual characteristic circuits. The individual feature circuits 311, 312, and 313 coupled in parallel are enabled in response to the control signals SEL1, SEL2, and SEL3, respectively. The method of reading the index information is that one of a plurality of individual characteristic circuits is enabled, and when the voltage on the input line 315 is changed, the current is detected in the enabled individual characteristic circuits. The voltage at which flow begins. For example, when the index information of the first individual characteristic circuit 311 is to be read, the control signals SEL1, SEL2 and SEL3 are applied in such a way that only this first individual characteristic circuit 311 is enabled, and other individual characteristics are enabled. The circuits 312 and 313 are disabled. After that, the voltage applied to the input port INPUT1 will change, and in the first individual characteristic circuit 311 which is enabled here, the voltage when the current starts to flow will be detected. After reading the index information of the first individual characteristic circuit 311, the control signals SEL1 and SEL2 are applied in such a manner that the first individual characteristic circuit 311 is disabled, and the second individual characteristic circuit 311 becomes enabled. After sequentially enabling all the individual characteristic circuits and obtaining all the required information, we will not enable all the individual characteristic circuits. 312 paper sizes are applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm)- ----------- install ----- r --- order --------- line 丨 • ---------------- -(Please read the notes on the back before filling this page) 476155 A7 _ 6738pif.doc / 008 B7 V. Description of the invention (q) and 313. Therefore, all of the individual characteristic circuits 311'312 and 313 will not operate in the normal mode of the semiconductor device. Accordingly, even when the semiconductor device performs signal exchange at high speed, the impedance of the input port in the semiconductor device is not affected. The waveform clamp circuits 301, 303, 305, and 307 are coupled to the input buffers 300, 302, 304, and 306 to modify the waveforms of the signals applied to these input buffers, respectively. The external voltage applied to the individual characteristic circuits 311, 312, and 313 is preferably the ground voltage VSS, because if the external voltage is a power supply voltage VDD, it is necessary to detect the voltage at which the current in the individual characteristic circuits starts to flow. At this time, a voltage higher than the external power supply voltage must be applied. In addition, since the current flowing in the individual characteristic circuit can be detected before the waveform clamp circuit 301 is operated (before the current flows through the waveform clamp circuit 301), the individual characteristic circuit can be combined with the waveform clamp circuit use. More preferably, each of the control signals SEL1, SEL2 and SEL3 is a mode register set (MRS) signal in a semiconductor element having an input circuit. When a control signal is a mode register group signal, no special circuit is needed to generate the control signal. In Figure 3, the fast input buffers 302, 304, and 306 and the slow input buffer 300 are not absolute decisions, but are relatively determined based on the frequency of the signal applied to each input port of the semiconductor element. In other words, one or more individual characteristic circuits are coupled to a low-speed input buffer to which a relatively low-speed signal is applied, and a paper size to which a relatively high-speed signal is applied is compliant with China National Standard (CNS) A4 (210 X 297 mm) (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs
▼ .1 ϋ ϋ n ϋ I ί 一一0, · ϋ ϋ I I ammmm ϋ I I n I ame— ϋ ϋ I I n ϋ n I ί I I n ϋ n ϋ ^1 ϋ ϋ ϋ I 476155 A7 __ 6738pif.doc/008 _B7 i、發明說明（Θ) 高速輸入緩衝區之上’並不耦接個別特徵電路’如此高速 輸入緩衝區的輸入阻抗就能變低。 第3圖中的個別特徵電路311，312或313的架構與操 作，將參考第4圖到第13圖做更詳細的敘述。 第4圖繪示的是根據本發明之一輸入電路的一個個別 特徵電路的一個較佳實施例。第4圖中的個別特徵電路311 包括一個指標器（indexer)420與一個選擇器430，指標器 420與選擇器430則在電壓節點VSS與輸入線315之間串 連耦接。大體上，選擇器430的兩端係回應於控制訊號SEL1 而短路或斷路。指標器420包括串連在電壓節點VSS與選 擇器430之間的一或多個NMOS電晶體MN41，MN42與 MN43，以及分別與電晶體MN41，MN42，與MN43平行 耦接的特徵保險絲F41，F42與F43。此指標器420還包括 —個主保險絲F40,其串連於電壓節點VSS與電晶體MN41 之間。 在個別特徵電路311的指標器420之中，就標示了半 導體元件內的資訊。選擇器430也包括一個主要電晶體 MP40，其閘極耦接至控制訊號SEL1。 以下所述係與個別特徵電路311的詳細操作有關。爲 了說明上的淸晰，假設半導體元件是一個動態隨機存取記 憶體（DRAM)，且此DRAM是以X4與X8的模式加以設計， 並以X4的模式封裝。同時也假設，主保險絲F40與特徵 保險絲F41，F42與F43在DRAM處於X4模式下不會切 斷，而特徵保險絲F41，F42與F43在DRAM處於χ8模 式下會被切斷。這個假設僅是爲了提供在執行時所建立的 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公釐） (請先閱讀背面之注音？事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 曹裝 • ·1 ϋ n H ϋ I -1 一 δ、塞 w a··· MM MB W MB I 線-Φ----------------------- 476155 A7 6738pif.doc/008 B7 五、發明說明（（1 ) 一個例子。因此，本發明可以不管此處的假設，而適用於 具有其他模式型式的半導體元件上。 在以上所述的情況下，dram設計所使用的模式上的 資訊，是由以下的程序而獲得。首先，以邏輯低(L)來施加 控制訊號SEL1，以藉此打開主要電晶體MP40。之後，個 別特徵電路311被予以致能（也就是，選擇器430會短路）。 接下來，一個變動的電壓被施加到輸入線315之上，而在 此同時，就探測流經個別特徵電路311的電流。當在特徵 電路311中的電流開始被探測到之時的輸入線315的電壓 VIN符合下述的式子（1)的時候，特徵保險絲F40與F41就 不會被切斷。 VIN〉VSS+VTN43+VTN42 (1) 其中， VtN42 和 VTN43 是NMOS電晶體MN42與MN43的臨 界電壓（threshold voltage)。因此，就可以根據上述的假設 推斷出此DRAM是以X8模式所設計出來的。 在另一方面，如果電流在輸入線315的電壓VIN符合 以下的式子（2)的時候留過個別特徵電路311，就可以推論 電晶體MN41，MN42與MN43都被繞過。 VIN>VSS (2) 據此，特徵保險絲F40，F41，F42與F43就不被切斷，且 因此可以推論此DRAM是以X4模式設計。 請再度參考第3圖，在第一個別特徵電路311的指標 資訊以上述的方法讀取到之後，就只有控制訊號SEL2成 爲邏輯低，而其他的控制訊號SEL1與SEL3則都是邏輯高 (H)。因此’只有第二個別特徵電路3 12是被予以致能的， 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 ▼裝 —Bi i·— n i·— IBBi emmf l 1 n« n ·1 1 I 線皿·---------------------- 476155 A7 B7 6738pif.doc/008 五、發明說明（ια") 而第二個別特徵電路312的指標資訊則可以經過上述相同 的方法取得。 當從個別特徵電路311-313中讀取指標資訊的程序結 束之後，半導體元件正常操作的時候，具有高（VDD)電爲 的控制訊號SEL1就被施加到主要電晶體MP40(請參考第4 圖）的閘極上，且因此主要電晶體MP40就不被予以致能 (disable)。據此，本發明具有一個額外的優點，其可以藉 由主要電晶體MP40的閘極重疊（overlap)電容而減少輸入 阻抗。 本發明並不限定於第4圖之指標器的架構。舉例來 說，保險絲F41，F42與F43並非必須分別與電晶體MN41， MN42與MN43平行耦接。然而，每一個電晶體可被繞過 (bypass)的狀況的數目，可在提供相當數量的保險絲與電晶 體的時候增加。據此，第4圖之指標器420的架構就僅是 用以解釋本發明的一個例子，而任何的架構，只要在輸入 線315與接地電壓VSS之間的電壓降可隨著一組保險絲切 斷或不切斷的組合而改變，就可以被使用於本發明中。此 外’第4圖的指標器420並不限定於具有三個電晶體的架 構。隨著指標器420包括更多個電晶體，指標器420所能 表示的指標的數量就會隨之增加。再者，指標器420中的 電晶體並不必爲NMOS形式。除了 NMOS型式的電晶體之 外’可提供一個預定電壓降的雙載子(bipolar)電晶體（未繪 出）與兩極真空管（diode)(未繪出)都可以使用。 在此同時，根據本發明而在個別特徵電路中的選擇 器’並不限定於第4圖中的選擇器430的架構。任何可以 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製▼ .1 ϋ ϋ n ϋ I ί 一一 0, · ϋ ϋ II ammmm ϋ II n I ame— ϋ ϋ II n ϋ n I ί II n ϋ n ϋ ^ 1 ϋ ϋ ϋ I 476155 A7 __ 6738pif.doc / 008 _B7 i. Description of the invention (Θ) The 'high-speed input buffer' is not coupled to individual characteristic circuits, so the input impedance of the high-speed input buffer can be reduced. The structure and operation of the individual characteristic circuits 311, 312, or 313 in FIG. 3 will be described in more detail with reference to FIGS. 4 to 13. Fig. 4 shows a preferred embodiment of an individual characteristic circuit of an input circuit according to the present invention. The individual characteristic circuit 311 in FIG. 4 includes an indexer 420 and a selector 430, and the indexer 420 and the selector 430 are serially coupled between the voltage node VSS and the input line 315. Generally, the two ends of the selector 430 are shorted or opened in response to the control signal SEL1. The indicator 420 includes one or more NMOS transistors MN41, MN42, and MN43 connected in series between the voltage node VSS and the selector 430, and characteristic fuses F41, F42 coupled in parallel with the transistors MN41, MN42, and MN43, respectively. With F43. The indicator 420 also includes a main fuse F40, which is connected in series between the voltage node VSS and the transistor MN41. In the indicator 420 of the individual characteristic circuit 311, the information in the semiconductor element is marked. The selector 430 also includes a main transistor MP40, whose gate is coupled to the control signal SEL1. The following is related to the detailed operation of the individual characteristic circuit 311. For the sake of clarity, it is assumed that the semiconductor device is a dynamic random access memory (DRAM), and the DRAM is designed in X4 and X8 mode, and is packaged in X4 mode. It is also assumed that the main fuse F40 and the characteristic fuses F41, F42 and F43 will not be cut when the DRAM is in the X4 mode, and the characteristic fuses F41, F42 and F43 will be cut when the DRAM is in the χ8 mode. This assumption is only to provide that the paper size established at the time of implementation is applicable to the Chinese National Standard (CNS) A4 specification (21 × 297 mm) (please read the note on the back? Matters before filling this page) Intellectual Property of the Ministry of Economic Affairs Printed by the staff's consumer cooperative of the Bureau • 1 ϋ n H ϋ I -1 δ, plug wa ... MM MB W MB I line-Φ ---------------- ------- 476155 A7 6738pif.doc / 008 B7 V. Explanation of the invention ((1) An example. Therefore, the present invention can be applied to semiconductor devices having other modes regardless of the assumptions here. In the case described above, the information on the mode used in the dram design is obtained by the following procedure. First, the control signal SEL1 is applied with a logic low (L) to turn on the main transistor MP40. After that, The individual characteristic circuit 311 is enabled (that is, the selector 430 is short-circuited). Next, a fluctuating voltage is applied to the input line 315, and at the same time, the current flowing through the individual characteristic circuit 311 is detected. The output when the current in the characteristic circuit 311 starts to be detected. When the voltage VIN of the line 315 meets the following formula (1), the characteristic fuses F40 and F41 will not be cut off. VIN> VSS + VTN43 + VTN42 (1) Among them, VtN42 and VTN43 are NMOS transistors MN42 and Threshold voltage of MN43. Therefore, it can be inferred that the DRAM is designed in X8 mode based on the above assumptions. On the other hand, if the voltage VIN of the current on the input line 315 meets the following formula ( 2) When the individual characteristic circuit 311 is left, it can be inferred that the transistors MN41, MN42, and MN43 are bypassed. VIN> VSS (2) According to this, the characteristic fuses F40, F41, F42, and F43 are not cut off. And therefore it can be inferred that this DRAM is designed in X4 mode. Please refer to Figure 3 again. After the index information of the first individual characteristic circuit 311 is read in the above-mentioned method, only the control signal SEL2 becomes logic low, while the others The control signals SEL1 and SEL3 are both logic high (H). Therefore, 'only the second individual characteristic circuit 3 12 is enabled. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read first Please fill in this page before filling in this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ▼ 装 —Bi i · — ni · — IBBi emmf l 1 n «n · 1 1 I wire dish · ------- --------------- 476155 A7 B7 6738pif.doc / 008 V. Description of the invention (ια ") The index information of the second individual characteristic circuit 312 can be obtained through the same method as above. After the process of reading the index information from the individual characteristic circuits 311-313 is completed, when the semiconductor device is operating normally, the control signal SEL1 with a high (VDD) behavior is applied to the main transistor MP40 (please refer to Figure 4) ), And therefore the main transistor MP40 is not disabled. Accordingly, the present invention has an additional advantage that it can reduce the input impedance by the gate overlap capacitance of the main transistor MP40. The present invention is not limited to the architecture of the indicator in FIG. 4. For example, the fuses F41, F42 and F43 do not have to be coupled in parallel with the transistors MN41, MN42 and MN43, respectively. However, the number of conditions that each transistor can be bypassed can increase when a significant number of fuses and transistors are provided. According to this, the structure of the indicator 420 in FIG. 4 is only an example for explaining the present invention, and any structure, as long as the voltage drop between the input line 315 and the ground voltage VSS can be switched with a group of fuses It can be used in the present invention by changing the combination of on or off. In addition, the indicator 420 of Fig. 4 is not limited to a structure having three transistors. As the indicator 420 includes more transistors, the number of indicators that the indicator 420 can represent increases. Furthermore, the transistor in the indicator 420 need not be in the form of an NMOS. In addition to NMOS type transistors, bipolar transistors (not shown) and diodes (not shown) that provide a predetermined voltage drop can be used. At the same time, the selector 'in the individual characteristic circuit according to the present invention is not limited to the structure of the selector 430 in FIG. Any paper size applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs
| · I ϋ n I— emmmm 1^L I 1 ·1 ϋ 1 I ϋ I n ·ϋ ϋ ϋ I 1 I n 1_1 ϋ n «ϋ ϋ ·1 ϋ ϋ n I n I ϋ I 476155 A7 6738pif.doc/008 B7 五、發明說明（G) 將個別特徵電路311的操作予以致能的架構都可以被用爲 選擇器。據此，選擇器430可以是回應於控制訊號SEL1 而短路或斷路的開關（switch)(未繪出）’或是將控制訊號 SEL1施加到基極上的一個雙載子電晶體。 第5圖繪示的是根據本發明之一輸入電路的一個個別 特徵電路的第二較佳實施例。個別特徵電路311包括一個 選擇器530以及一個指標器520。選擇器530是由一個主 要電晶體MN50所組成。指標器520包括NMOS電晶體 MN51，MN52與MN53,以及特徵保險絲F51，F52與F53。 指標器520還包括一個主要保險絲F50。 第5圖的個別特徵電路311的架構與第4圖個別特徵 電路的架構相似，所不同的地方在於，主要電晶體MN50 是一個NMOS電晶體。據此，要打開（turn on)主要電晶體 MN50，就必須使控制訊號SEL1爲邏輯高(H)。如同第4 圖之實施例，在所有保險絲F50，F51，F52與F53都沒有 被切斷的狀況下，假若主要電晶體MN50不存在，則輸入 線315就會見到NMOS電晶體MN51，MN52與MN53的 閘極重疊電容（gate overlap capacitance)。然而，藉由將主 要電晶體MN50耦接在輸入線315與指標器520之間，輸 入線315就可以僅止於看見主要電晶體MN50的閘極重疊 電容。第5圖之實施例的其他操作都與第4圖的實施例相 似，所以在此處就不詳加敘述。 第6與7圖顯不的是根據本發明之個別特徵電路的不 同實施例。 在第6圖的個別特徵電路311中，選擇器630包括一 16 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 • «I ϋ n i_i ·ϋ I f n n ϋ —·1 ϋ ϋ 11 線丨"4ΙΡ--------------------- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 476155 A7 B7 6738pif.doc/008 五、發明說明（Μ) 個主要電晶體MP60。指標器620包括NMOS電晶體 MN61，MN62與MN63,以及特徵保險絲F6卜F62與F63。 指標器620還包括一個主要保險絲F60。第7圖的指標器 720與第6圖的指標器620具有相同的架構。而與第6圖 之選擇器630不同的，第7圖的選擇器730包括一個NMOS 形式的主要電晶體MN70。 在顯示於第6或7圖之個別特徵電路的實施例中，選 擇器630或730耦接到一個接地電壓VSS，而指標器620 或720則耦接在選擇器630或730與輸入線315之間。較 佳的是，指標器620或720可以更包括一個電晶體(未繪 出），其閘極與源極相連，且位於電晶體MN63或MN73的 汲極與輸入線315之間。當這個電晶體存在的時候，在所 有保險絲沒被切斷時，由輸入線315所見的閘極重疊電容 就可以減少。 第6與7圖的個別特徵電路的其他操作，分別與第4 與5圖之個別特徵電路相似，所以在此就不加以詳細說 明。 第8圖繪示的是根據本發明之個別特徵電路的又一個 實施例。第8圖的個別特徵電路311包括串連於一個電壓 節點VSS與一條輸入線315之間的一個指標器820與一個 選擇器830。選擇器830的兩端回應於第一控制訊號SEL1 而電性短路或斷路。指標器820包括串連於選擇器830與 電壓節點VSS之間的一或多個NMOS電晶體MN81，MN82 與MN83，以及分別平行耦接到電晶體MN81，MN82與 MN83上的特徵電阻F81，F82與F83。指標器820還可以 I n ϋ ϋ ϋ ί I ^1 ^1 I 1 ϋ ϋ .^1 I sl· 1 n n 一-口*· I ϋ ϋ 1 ϋ I ·ϋ I 1 ϋ (請先閱讀背面之注咅？事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 476155 6738pif.doc/008 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（（<) 更佳的包括串連於電晶體MN83與電壓節點VSS之間的一 個主要保險絲F 8 4。 在標示（indexing)的程序中，控制訊號以邏輯高的 方式被施加在選擇器830之主要電晶體MN80的閘極上。 之後，回應於控制訊號SEL1，主要電晶體MN80就被打開， 且指標器820中的電晶體MN81，MN82與MN83也會打 開。然而，由於保險絲F81，F82與F83分別與電晶體 MN81，MN82與MN83平行耦接，因此電晶體MN81，MN82 與MN83會被選擇性的繞過。因此，當電晶體MN81，MN82 與MN83的寬度比長度（W/L)的比値分別被設定成不同 値，且電晶體MN81，MN82與MN83中的兩個被繞過的時 候，在指標器820之中流動的電流IJDX的總量就會根據 所繞過的兩個電晶體MN81-MN83而改變。 舉例來說，假設在半導體元件以X4模式封裝的時候’ 在指標器820之中流動的電流I_IDX的總量爲1〇毫安培 (mA)，而在半導體元件以X8模式封裝的時候，在指標器 820之中流動的電流I_IDX的總量爲20毫安培(mA)。此 外，還假設電晶體MN81的W/L比値較電晶體MN83的 W/L比値爲大。如上所述，這些假設僅是例子而已。然後’ 當保險絲F81被切斷時所流的電流181，就會比保險絲F82 被切斷時所流的電流182大。因此，藉由調整各種的參數’ 電流IJDX的總量就可以設定爲20mA或10mA。 據此，當保險絲F82與F83沒被切斷，而只有保險絲 F81被切斷的時候，所得到的結論就會是此一半導體兀件 是以X8模式所封裝的。當保險絲F81與F83沒被切斷’ (請先閱讀背面之注音2事項再填寫本頁) 言 Γ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 476155 A7 B7 6738pif.doc/008 五、發明說明（4) 而保險絲F82被切斷的時候，所得到的結論就會是此一半 導體元件是以X4模式所封裝的。 根據第8圖之實施例所得的個別特徵電路，並不像第4 到7圖之較佳實施例中的個別特徵電路一樣，是由輸入線 的電壓層級(voltage level)來取得指標資訊，而是由輸入線 中所流動之電流總量來取得指標資訊。根據第8圖所示的 架構，就可以免去變化電壓直到輸入線中有電流開始流動 的這一個程序。 較佳的是，電晶體MN81，MN82與MN83彼此之間的 W/L比値相差甚遠，以使電流I_IDX的變化可被輕易的探 測到。此外，當電晶體MN81，MN82與MN83彼此之間的 W/L比値相差甚遠的時候，在半導體製造時所產生的程序 差異的影響，就可以因此而減少。 指標器820的可變電阻並不限定於NMOS電晶體，而 可以使用能夠接收控制訊號SEL1並產生電流的任何種類 的電阻。據此，此可變電阻可以是閘極耦接至控制訊號的 PM0S電晶體(未繪出），或是將控制訊號施加到其基極上的 雙載子電晶體(bipolar)(未繪出）。另一方面，可變電阻可以 有不同的阻抗。當指標器820包括雙載子電晶體（未繪出) 的時候，此雙載此電晶體可以具有不同的電流增益（current gain)値。 本發明之特徵電路中的選擇器，並不限定於選擇器830 的架構。任何可致能個別特徵電路311操作的架構都可以 使用於此。因此，選擇器830可以是回應於控制訊號SEL1 而短路或斷路的開關（未繪出），或是將控制訊號施加到其 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製| · I ϋ n I— emmmm 1 ^ LI 1 · 1 ϋ 1 I ϋ I n · ϋ ϋ ϋ I 1 I n 1_1 ϋ n «ϋ ϋ · 1 ϋ ϋ n I n I ϋ I 476155 A7 6738pif.doc / 008 B7 V. Description of the Invention (G) Any architecture that enables the operation of individual feature circuits 311 can be used as a selector. Accordingly, the selector 430 may be a switch (not shown) that is short-circuited or opened in response to the control signal SEL1 or a bipolar transistor that applies the control signal SEL1 to the base. Fig. 5 shows a second preferred embodiment of an individual characteristic circuit of an input circuit according to the present invention. The individual characteristic circuit 311 includes a selector 530 and an indicator 520. The selector 530 is composed of a main transistor MN50. The indicator 520 includes NMOS transistors MN51, MN52 and MN53, and characteristic fuses F51, F52 and F53. The indicator 520 also includes a main fuse F50. The architecture of the individual characteristic circuit 311 in FIG. 5 is similar to the architecture of the individual characteristic circuit in FIG. 4 except that the main transistor MN50 is an NMOS transistor. Accordingly, to turn on the main transistor MN50, the control signal SEL1 must be set to logic high (H). As in the embodiment of FIG. 4, under the condition that all fuses F50, F51, F52 and F53 are not cut off, if the main transistor MN50 does not exist, the input line 315 will see the NMOS transistors MN51, MN52 and MN53. Gate overlap capacitance. However, by coupling the main transistor MN50 between the input line 315 and the indicator 520, the input line 315 can be limited to seeing the gate overlapping capacitance of the main transistor MN50. The other operations of the embodiment of Fig. 5 are similar to those of the embodiment of Fig. 4, so they will not be described in detail here. Figures 6 and 7 show different embodiments of individual characteristic circuits according to the invention. In the individual characteristic circuit 311 in FIG. 6, the selector 630 includes a 16 (please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs • «I ϋ n i_i · ϋ I fnn ϋ — · 1 ϋ ϋ 11 wires 丨 " 4ΙΡ --------------------- This paper size applies to China National Standard (CNS) A4 (210 X 297 male) (Centimeter) 476155 A7 B7 6738pif.doc / 008 5. Description of the invention (M) The main transistor MP60. The indicator 620 includes NMOS transistors MN61, MN62 and MN63, and characteristic fuses F6, F62 and F63. The indicator 620 also includes a main fuse F60. The indicator 720 of FIG. 7 has the same architecture as the indicator 620 of FIG. 6. Unlike the selector 630 in FIG. 6, the selector 730 in FIG. 7 includes a main transistor MN70 in the form of an NMOS. In the embodiment of the individual characteristic circuit shown in FIG. 6 or 7, the selector 630 or 730 is coupled to a ground voltage VSS, and the indicator 620 or 720 is coupled between the selector 630 or 730 and the input line 315. between. Preferably, the indicator 620 or 720 may further include a transistor (not shown), the gate of which is connected to the source, and is located between the drain of the transistor MN63 or MN73 and the input line 315. When this transistor is present, the gate overlap capacitance seen by the input line 315 can be reduced when all fuses are not cut. The other operations of the individual characteristic circuits of Figs. 6 and 7 are similar to the individual characteristic circuits of Figs. 4 and 5, respectively, so they will not be described in detail here. Fig. 8 shows still another embodiment of an individual characteristic circuit according to the present invention. The individual characteristic circuit 311 of FIG. 8 includes an indicator 820 and a selector 830 connected in series between a voltage node VSS and an input line 315. Both ends of the selector 830 are electrically shorted or opened in response to the first control signal SEL1. The indicator 820 includes one or more NMOS transistors MN81, MN82, and MN83 connected in series between the selector 830 and the voltage node VSS, and characteristic resistors F81, F82 coupled to the transistors MN81, MN82, and MN83 in parallel. With F83. The indicator 820 can also I n ϋ ϋ ϋ ί I ^ 1 ^ 1 I 1 ϋ ϋ. ^ 1 I sl · 1 nn One-port * · I ϋ ϋ 1 ϋ I · ϋ I 1 ϋ (Please read the Note: Please fill in this page again.) The paper printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 476155 6738pif.doc / 008 A7 B7 Intellectual Property of the Ministry of Economic Affairs Printed by the Bureau ’s Consumer Cooperatives 5. Invention Description (<) It is better to include a main fuse F 8 4 connected in series between transistor MN83 and voltage node VSS. In the indexing process, the control signal A logic high is applied to the gate of the main transistor MN80 of the selector 830. Then, in response to the control signal SEL1, the main transistor MN80 is turned on, and the transistors MN81, MN82 and MN83 in the indicator 820 are also turned on. It will open. However, because the fuses F81, F82 and F83 are coupled in parallel with the transistor MN81, MN82 and MN83, respectively, the transistor MN81, MN82 and MN83 will be selectively bypassed. Therefore, when the transistor MN81, MN82 and MN83 ratio of width to length (W / L) When it is set to be different, and two of the transistors MN81, MN82, and MN83 are bypassed, the total amount of current IJDX flowing in the indicator 820 will be based on the two transistors MN81- MN83. For example, suppose that when the semiconductor device is packaged in X4 mode, the total amount of current I_IDX flowing in the indicator 820 is 10 milliamperes (mA), and when the semiconductor device is packaged in X8 mode, At this time, the total amount of current I_IDX flowing in the indicator 820 is 20 milliamperes (mA). In addition, it is also assumed that the W / L ratio 电 of the transistor MN81 is larger than the W / L ratio 电 of the transistor MN83. As above As mentioned, these assumptions are just examples. Then 'the current 181 flowing when the fuse F81 is cut is greater than the current 182 flowing when the fuse F82 is cut. Therefore, by adjusting various parameters' The total amount of current IJDX can be set to 20mA or 10mA. According to this, when fuses F82 and F83 are not cut, and only fuse F81 is cut, the conclusion is that this semiconductor element is based on X8 mode package. When fuses F81 and F83 are not cut ('Please read the note 2 on the back before filling this page) Γ This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 476155 A7 B7 6738pif.doc / 008 5. Description of the invention ( 4) When the fuse F82 is cut, the conclusion is that this semiconductor component is packaged in X4 mode. The individual characteristic circuit obtained according to the embodiment of FIG. 8 is not the same as the individual characteristic circuit of the preferred embodiment of FIGS. 4 to 7, and the index information is obtained by the voltage level of the input line, and The indicator information is obtained from the total amount of current flowing in the input line. According to the architecture shown in Figure 8, the procedure of changing the voltage until the current in the input line starts to flow can be eliminated. Preferably, the W / L ratio 电 of the transistors MN81, MN82, and MN83 are far from each other, so that the change of the current I_IDX can be easily detected. In addition, when the W / L ratios MN of the transistors MN81, MN82, and MN83 are very different from each other, the influence of the process differences during semiconductor manufacturing can be reduced accordingly. The variable resistance of the indicator 820 is not limited to the NMOS transistor, and any type of resistor capable of receiving the control signal SEL1 and generating a current may be used. According to this, the variable resistor can be a PM0S transistor (not shown) whose gate is coupled to the control signal, or a bipolar transistor (not shown) whose control signal is applied to its base. . On the other hand, variable resistors can have different impedances. When the indicator 820 includes a dual-carrier transistor (not shown), the dual-carrier transistor may have different current gains. The selector in the characteristic circuit of the present invention is not limited to the architecture of the selector 830. Any architecture capable of enabling the operation of the individual characteristic circuit 311 can be used here. Therefore, the selector 830 may be a switch (not shown) which is short-circuited or opened-circuited in response to the control signal SEL1, or a control signal is applied to it (please read the precautions on the back before filling this page) Printed by Employee Consumer Cooperative
-· ϋ .^1 I tl· ϋ n ϋ 一^J ϋ 1 ϋ ϋ n n ϋ I ϋ n ϋ ί ^1 ϋ ϋ ϋ ϋ ϋ H ϋ ϋ n ϋ ϋ 1 ϋ ϋ n 1 ϋ ^1 I 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 476155 A7 6738pif.doc/008 B7 五、發明說明（（〕） 基極上的雙載子電晶體(bipolai:)(未繪出）。 第9圖繪示的是根據本發明之一輸入電路的另一個個 別特徵電路的實施例。顯示於第9圖之個別特徵電路的指 標器920包括串連於選擇器930與一接地電壓VSS之間的 一或多個電晶體MP91，MP92與MP93，以及與電晶體 MP91，MP92和MP93分別並連的特徵電阻F91，F92與 F93 ° 根據第9圖之實施例所得的個別特徵電路311的架 構，與第8圖的實施例相似，其相異處在於選擇器930的 電晶體MP90，MP91，MP92與MP93以及指標器920是 PMOS形式。因此，詳細的說明在此就予以省略。 第1〇圖繪示的是根據本發明之一輸入電路的另一個 個別特徵電路的實施例。第10圖的個別特徵電路311包括 串連於接地電壓VSS與輸入線315之間的一個指標器1020 以及選擇器1030。本質上，選擇器1030的兩端係回應於 控制訊號SEL1而電性短路或斷路。指標器1020包括並連 耦接於選擇器1030與接地電壓VSS之間的三個電晶體 MN101，MN102與MN103，以及分別串連於電晶體 MN101，MN102和MN103與接地電壓VSS之間的特徵保 險絲F101，F102與F103。在指標器1020的兩端之間流動 的電流I-IDX的總量，會隨著特徵保險絲F101，F102與 F103切斷或不切斷的組合而改變。 在標示（indexing)的程序中，控制訊號SEL1以邏輯高 (H)的方式被施加在選擇器1〇3〇之主要電晶體MN100的閘 極上。之後，回應於控制訊號SEL1，主要電晶體MN100 20 本紙張尺度適用中國國家標準（CNS)A4規格（21G X 297公釐) "" 两 (請先閱讀背面之注意事項再填寫本頁) -----r---訂---------線丨m----------------------- 476155 A7 6738pif.doc/008 B7 五、發明說明（u) 就被打開，且指標器1020中的電晶體MN101 ’ MN102與 MN103也會打開。然而，由於保險絲Fl〇l，F102與F103 分別耦接在電晶體MN101 ’ MN102與MN103的汲極與接 地電壓VSS之間，因此電晶體MN101，MN102與MN103 會被選擇性的繞過。因此，當電晶體MN101 ’ MN102與 MN103的寬度比長度（W/L)的比値分別被設定成不同値’ 指標電流I_IDX就會隨著切斷的保險絲的組合而變。這是 因爲指標電流I_IDX是分別流經電晶體ΜΝ1〇1，MN102 與MN103之中的電流1101，Il〇2與1103的總和。必須注 意的是，顯示於第10圖中的指標器1020的架構’並非做 爲限疋之用。 第11圖繪示的是根據本發明之一輸入電路的另一個 個別特徵電路的實施例。第11圖中的指標器H20包括平 行耦接於選擇器1130與接地電壓VSS之間的三個電晶體 MP111，MP112與MP113,以及分別串連於電晶體MP111， MP112與MP113與接地電壓VSS之間的特徵保險絲 Fill ， F112 與 F113 〇 第Π圖中的個別特徵電路與第10圖的個別特徵電路 的差異在於，指標器1120中的電晶體MP111，MP112與 MP113，以及選擇器1130係爲PMOS形式。除此之外，第 Π圖的個別特徵電路的操作會與第10圖之個別特徵電路 的操作相近，因此在此就不予以詳細描述。 第12圖所繪示的是根據本發明之一輸入電路的又一 個個別特徵電路的實施例。第12圖的各瞥特徵電路311包 括串連於接地電壓VSS與輸入線315之間的一個指標器 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 -裝-----r---訂------- 丨線_#--------------- 476155 A7 B7 6738pif.doc/008 五、發明說明（q) 1220以及選擇器1230。選擇器1230的兩端回應於控制訊 號SEL1而電性短路或斷路。指標器1220包括串連於選擇 器1230與接地電壓VSS之間的四個電晶體MN121， MN122，MN123與MN124，以及分別從電晶體MN124的 源極耦接到電晶體MN121，MN122，MN123與MN124的 汲極的特徵保險絲F121，F122，F123與F124。所繞過的 電晶體的個數會隨著特徵保險絲F121’F122’F123與F124 的切斷與否的組合而改變，而因此指標器1220中的電壓降 也會產生變化。較佳的是，指標器1220還包括串連於電晶 體MN124的源極與接地電壓VSS之間的一個主要保險絲 F125。 第12圖中指標器1220內的保險絲的排列與第4到7 圖中的保險絲的排列方式不同。當第12圖中的一個外部保 險絲(例如F121)沒被切斷的時候’位於外部保險絲（F121) 兩端之間的電晶體，不管內部保險絲(例如F122，F123與 F124)的狀態爲何，都會被繞過(bypass)。換句話說，與第4 到7圖之指標器的架構不同的，當外部保險絲(例如F121) 沒被切斷的時候，就會具有與所有內部保險絲(例如F122， F123與F124)沒被切斷同樣的效果。據此，所繞過的電晶 體的個數可以藉由一個單獨的外部保險絲來加以調整。舉 例來說，四個電晶體MN121，MN122，MN123與MN124 可以以使用保險絲F121來加以繞過。 第12圖的操作與架構除了上述的差異之外，都與第4 到7圖的操作及架構相似，因此在此省去詳細的敘述。 第13圖繪示的是根據本發明之一輸入電路的另一個 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 x 297公釐） (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 -a I n I n n 一a,_ · 1 1 ϋ ϋ mma§ 1 ά—φ----------------------- 476155 A7 B7 6738pif.doc/008 五、發明說明) 個別特徵電路的實施例。指標器1320包括四個電晶體 MN131，MN132，MN133 與 MN134,以及特徵保險絲 F134， F135，F136與F137，這些元件的排列都與第12圖中的指 標器1220中元件的排列方式相同。 第13圖的個別特徵電路311與第12圖的差異在於， 選擇器1330是串連耦接於指標器1320與接地電壓VSS之 間。除了這點差異之外，第13圖的個別特徵電路的架構與 操作都與第12圖的個別特徵電路相同，因此，在此就省略 詳細的說明。 根據本發明所得的個別特徵電路，並不限定於顯示在 第4到13圖中的實施例的架構。任何的架構，只要在允許 電流於特徵電路內流動的輸入電路中的輸入線的電壓，可 以隨著電壓削減元件（voltage reducing device)，或是安裝 於其上之可變電阻與特徵保險絲的排列而改變，就可以加 以使用。 雖然本發明已以參照特定的實施例予以說明，但很明 顯的，熟知此技藝者當然可以對這些實施例進行修改。因 此，本發明的範圍將以所附專利申請範圍訂定之。 在根據本發明所得之半導體元件內具有平行個別特徵 電路的一個輸入電路之中，個別特徵電路可選擇以特殊的 測試模式加以驅動，如此就可以避免特徵電路在產品上的 不良影響。根據本發明所得之具有平行特徵電路的一個輸 入電路可以與高速操作的半導體元件一起使用，而且可以 確保多量的指標器。此外，此特徵電路可以與位於半導體 元件之輸入璋上的波形夾紺電路共用。 23 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） c請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製-· Ϋ. ^ 1 I tl · ϋ n ϋ 一 ^ J ϋ 1 ϋ ϋ nn ϋ I ϋ n ϋ ί ^ 1 ϋ ϋ ϋ ϋ ϋ H ϋ ϋ n ϋ ϋ 1 ϋ ϋ n 1 ϋ ^ 1 I This paper Standards apply to China National Standard (CNS) A4 specifications (210 X 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 476155 A7 6738pif.doc / 008 B7 V. Description of the invention (()) Double-carrier electricity on the base Crystal (bipolai :) (not shown). FIG. 9 shows another embodiment of an individual characteristic circuit of an input circuit according to the present invention. The indicator 920 of the individual characteristic circuit shown in FIG. 9 includes a string. One or more transistors MP91, MP92, and MP93 connected between the selector 930 and a ground voltage VSS, and characteristic resistors F91, F92, and F93 connected in parallel with the transistors MP91, MP92, and MP93 ° According to Fig. 9 The structure of the individual characteristic circuit 311 obtained in this embodiment is similar to the embodiment of FIG. 8 except that the transistors MP90, MP91, MP92 and MP93 of the selector 930 and the indicator 920 are in the form of PMOS. Therefore, the details The description is omitted here. FIG. 10 shows an input circuit according to one of the present invention. The individual characteristic circuit 311 shown in FIG. 10 includes an indicator 1020 and a selector 1030 connected in series between the ground voltage VSS and the input line 315. In essence, two of the selector 1030 The terminal is electrically shorted or opened in response to the control signal SEL1. The indicator 1020 includes three transistors MN101, MN102 and MN103 which are connected in parallel between the selector 1030 and the ground voltage VSS, and are connected in series to the transistor Characteristic fuses F101, F102, and F103 between MN101, MN102, and MN103 and the ground voltage VSS. The total amount of current I-IDX flowing between both ends of the indicator 1020 will be cut by the characteristic fuses F101, F102, and F103. In the indexing process, the control signal SEL1 is applied to the gate of the main transistor MN100 of the selector 1030 in a logic high (H) manner. After that, In response to the control signal SEL1, the main transistor MN100 20 This paper size applies to the Chinese National Standard (CNS) A4 specification (21G X 297 mm) " " Two (Please read the precautions on the back before filling this page)- --- r --- Order --------- line 丨 m ----------------------- 476155 A7 6738pif.doc / 008 B7 V. Invention Note (u) is turned on, and the transistors MN101 ′ MN102 and MN103 in the indicator 1020 are also turned on. However, since the fuses F101, F102 and F103 are respectively coupled between the drains of the transistors MN101 ′ MN102 and MN103 and the ground voltage VSS, the transistors MN101, MN102 and MN103 are selectively bypassed. Therefore, when the ratios of the width to length (W / L) of the transistors MN101 ′ MN102 and MN103 are set to be different, respectively, the index current I_IDX changes with the combination of the cut-off fuses. This is because the index current I_IDX is the sum of the currents 1101, 1102, and 1103 flowing through the transistors MN101, MN102, and MN103, respectively. It must be noted that the structure of the indicator 1020 shown in FIG. 10 is not used for limitation. Fig. 11 shows another embodiment of an individual characteristic circuit of an input circuit according to the present invention. The indicator H20 in FIG. 11 includes three transistors MP111, MP112 and MP113 coupled in parallel between the selector 1130 and the ground voltage VSS, and three transistors MP111, MP112 and MP113 connected to the ground voltage VSS in series. The characteristic fuses Fill, F112 and F113 〇 The difference between the individual characteristic circuit in Figure Π and the individual characteristic circuit in Figure 10 is that the transistors MP111, MP112 and MP113 in the indicator 1120, and the selector 1130 are PMOS. form. In addition, the operation of the individual characteristic circuit of Fig. Π will be similar to the operation of the individual characteristic circuit of Fig. 10, so it will not be described in detail here. FIG. 12 shows another embodiment of an individual characteristic circuit of an input circuit according to the present invention. The characteristic circuit 311 in FIG. 12 includes an indicator connected in series between the ground voltage VSS and the input line 315. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 public love) (please read the back first) Please note this page before filling in this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ----- r --- Order ------- 丨 线 _ # --------- ------ 476155 A7 B7 6738pif.doc / 008 5. Description of the invention (q) 1220 and selector 1230. Both ends of the selector 1230 are electrically shorted or opened in response to the control signal SEL1. The indicator 1220 includes four transistors MN121, MN122, MN123, and MN124 connected in series between the selector 1230 and the ground voltage VSS, and coupled to the transistors MN121, MN122, MN123, and MN124 from the source of the transistor MN124, respectively. The characteristics of the drain are fuses F121, F122, F123 and F124. The number of bypassed transistors will change depending on whether the characteristic fuses F121'F122'F123 and F124 are cut or not, and therefore the voltage drop in the indicator 1220 will also change. Preferably, the indicator 1220 further includes a main fuse F125 connected in series between the source of the transistor MN124 and the ground voltage VSS. The arrangement of the fuses in the indicator 1220 in FIG. 12 is different from the arrangement of the fuses in FIGS. 4 to 7. When an external fuse (such as F121) in Figure 12 is not cut off, the transistor located between the two ends of the external fuse (F121), regardless of the status of the internal fuse (such as F122, F123, and F124) Bypassed. In other words, unlike the structure of the indicator in Figures 4 to 7, when the external fuse (such as F121) is not cut, it will have no disconnection with all internal fuses (such as F122, F123, and F124). Break the same effect. Based on this, the number of bypassed transistors can be adjusted by a separate external fuse. For example, the four transistors MN121, MN122, MN123 and MN124 can be bypassed by using fuse F121. The operations and architecture of FIG. 12 are similar to those of FIGS. 4 to 7 except for the above-mentioned differences, so detailed descriptions are omitted here. Figure 13 shows another paper size of an input circuit according to the present invention, which is applicable to the Chinese National Standard (CNS) A4 specification (21 × 297 mm) (Please read the precautions on the back before filling this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs-a I n I nn 一 a, _ · 1 1 ϋ ϋ mma§ 1 ά—φ ------------------- ---- 476155 A7 B7 6738pif.doc / 008 V. Description of the invention) Examples of individual characteristic circuits. The indicator 1320 includes four transistors MN131, MN132, MN133, and MN134, and characteristic fuses F134, F135, F136, and F137. The arrangement of these components is the same as that of the indicator 1220 in Fig. 12. The difference between the individual characteristic circuit 311 in FIG. 13 and FIG. 12 is that the selector 1330 is coupled in series between the indicator 1320 and the ground voltage VSS. Except for this difference, the structure and operation of the individual characteristic circuit of FIG. 13 are the same as those of the individual characteristic circuit of FIG. 12, and therefore, detailed descriptions are omitted here. The individual characteristic circuits obtained according to the present invention are not limited to the architecture of the embodiments shown in Figs. 4 to 13. For any architecture, as long as the voltage of the input line in the input circuit that allows current to flow in the characteristic circuit, it can follow the voltage reducing device, or the arrangement of the variable resistor and characteristic fuse mounted on it. But change, you can use it. Although the present invention has been described with reference to specific embodiments, it is obvious that those skilled in the art can certainly modify these embodiments. Accordingly, the scope of the invention will be determined by the scope of the appended patent applications. In an input circuit having parallel individual characteristic circuits in the semiconductor element obtained according to the present invention, the individual characteristic circuits can be selected to be driven in a special test mode, so that the adverse effects of the characteristic circuits on the product can be avoided. An input circuit having a parallel characteristic circuit obtained according to the present invention can be used with a semiconductor element operating at a high speed, and a large number of indicators can be secured. In addition, this characteristic circuit can be shared with the waveform clamp circuit located on the input of the semiconductor element. 23 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) c Please read the notes on the back before filling out this page) Printed by the Employees ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs
▼ m I ϋ n ϋ n n ϋ^-r*°J· -ϋ n n I I 1_· ϋ I Ml n ϋ ϋ ϋ I ϋ I I n ϋ n ϋ n n ϋ n ϋ n ϋ ϋ n I▼ m I ϋ n ϋ n n ϋ ^ -r * ° J · -ϋ n n I I 1_ · ϋ I Ml n ϋ ϋ ϋ I ϋ I I n ϋ n ϋ n n ϋ n ϋ n ϋ I n I