TW464979B - Ultrasonic assisted method of forming a conduction layer on a semiconductor device - Google Patents

Abstract

The present invention provides three embodiments of the ultrasonic assisted method of forming a conduction layer on a semiconductor device that produce ultrasonic energy on the substrate so as to perform deposition during (1) PVD or CVD, (2) annealing, and (3) plating deposition. The first embodiment relates to the provision of ultrasonic energy that vibrates a substrate and deposits the first layer on the substrate, so that it is possible to form a more homogeneous deposition on the side-walls of the opening and to reduce the production of overhang and void. The second embodiment relates to the usage of ultrasonic vibration during annealing or RTA process, so that it is possible to form a more smooth deposition in the contact hole of barrier layer/seed layer/conduction layer. The third embodiment relates to a method ultrasonically vibrate a substrate in vertical or horizontal direction so as to plate a conduction layer (e.g., copper layer) on the substrate, it is then possible to produce a better step coverage for metal plating in a small contact hole.

Description

46 497 9 Α? ---------- 67 V. Description of the invention () Field of the invention: The month of this issue is 'about the use of ultrasonic semiconductor device manufacturing processes, especially about electrical bonding, deposition' or annealing the substrate , A method of filling or plugging the contact / interlayer holes by ultrasonically vibrating the substrate. Background of the invention: ULSI circuits have been developed to the sub-micron stage. Traditional chemical vapor deposition and physical vapor deposition (PVD) processes for the deposition of metal thin films currently face problems with poor step coverage of vertical contact holes with diameters smaller than 0.5 μm and high aspect ratios. Therefore, there is a need for an improved deposition annealing technique to improve the step coverage of vertical contact holes with small diameters and high aspect ratios. Printed by the Consumers' Cooperative of the China Standards Bureau of the Ministry of Economic Affairs 1.1. N-in-I ---- 1 Private ---- 1---, 1T (Please read the precautions on the back before filling this page) In order to overcome Various problems have been developed to improve the problems mentioned above, and their contents are recorded in related patents and technical documents. Among them, the closest and most obvious related technology development to solve this problem can be referred to the following patent description. U.S. Patent No. 5,620,103 (Xu et al.) Patent description, which describes a physical vapor deposition method using ultrasonic waves after sedimentation. U.S. Patent No. 5,763,01 8 (Sato) describes that it is about a chemical vapor deposition (CVD) method. U.S. Patent No. 5,219,79 (Miyatake) patent specification discloses a process using ultrasonic aluminum annealing. U.S. Patent No. 5,290,733 (Hayasaka et al.) Patent specification discloses a method for electroplating metal (aluminum). U.S. Patent No. 5,42 5,96 5 (Tasmor et al,) Patent Description, Revealing the Use of Ultrasound Waveforms 2 Paper Sizes Free Use of Chinese National Standards < CNS > A4 Specification (210X297 mm) Ministry of Economic Affairs Standards Bureau Shellfish Consumer Cooperation. Du Yin 46497 9 Λ7 Β7 V. Description of the invention () Method for forming polycrystalline vermiculite. U.S. Patent No. 5,275,714 (Bonnet et al.) Patent Description, which describes a galvanic deposition process using ultrasound. U.S. Patent No. 5,270,252 (Papanicolaon) states that its content describes wet photoresist removal steps using ultrasound, however these processes can be further improved. Purpose and summary of the invention: The purpose of the present invention is to (1) deposit in (1) the deposition, (2) the annealing and / or (3) the electroplating process, and contact / interstitial cavity through the method of ultrasonic vibration wafer. Layer (b) seed layer (c) deposition of conductive layer (eg metal plug). Another object of the present invention is to contact / interlayer via (a) a barrier layer (b) by (1) depositing, (2) annealing and / or (3) electroplating, by ultrasonically oscillating the wafer. Seed layer (c) Deposition of conductive layer (eg, metal plug) to improve step coverage. In order to achieve the above purpose, the present invention provides three specific embodiments. In the process of (1) deposition, (2) annealing / RTA, or (3) electroplating deposition, 'ultrasonic waves are used in the contact holes on the substrate to oscillate the substrate. The three specific embodiments can be any combination. The three specific embodiments are: (1) First specific embodiment-performing on-site ultrasonic oscillation during CVD or PVD. (2) A second specific embodiment-in-situ or non-situ ultrasonic annealing. 3 The paper size is in accordance with the Chinese National Standard (CNS) A4 * t (210 X 297 mm) (Please read the precautions on the back before filling in this tile)

Consumer cooperation of the Central Bureau of Standards, Ministry of Economic Affairs ‘Du printed 46497- A7 _____ B7 V. Description of the invention () (3) The third embodiment-electroplating by ultrasonic vibration method. First «Example-Ultrasonic shock weight in-situ during CVD or PVD deposition The first specific embodiment of the present invention is a method of providing 4 sonic energy for vibrating a substrate and depositing on the substrate . Since this ultrasonic oscillation is carried out in the field between the sediments, it is an on-site ultrasonic deposition. This ultrasonic oscillation makes the deposition on the side walls of the opening more uniform and reduces the generation of overhangs and holes. The first specific embodiment is to use the ultrasonic oscillation method and the .CVD or PVD process to deposit resistance in the contact holes on the substrate. The barrier layer / seed layer / and the first conductive layer (eg, plug); the above-mentioned physical vapor deposition (PVD) can be: evaporation, sputtering, and molecular beam epitaxy (MBE). A substrate 10 'is provided. The substrate has a hole 22 extending through the insulating layer 20 on the substrate. The substrate 10 is fixed on the plate 11 in the deposition reaction chamber. The first layer is deposited on the insulating layer by chemical vapor deposition or physical vapor phase, and is filled at least partially into the gift hole 22 on the substrate. During the sedimentation period, a flat plate Π—ultrasonic energy 12 is provided to oscillate the substrate 10. This step is a critical step. Its oscillation direction can be horizontal, vertical or a combination of the two = the oscillation frequency of this substrate is greater than 70 kHz.

Second specific embodiment-market or non-field RTP The second embodiment of the present invention is to anneal the conductive layer or the barrier layer. 4 The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). ) (Please read the notes on the back before filling in this X)

J Order 464979 A7 _ B7_ __ 5. During the description of the invention () or RTA, the ultrasonic vibration method is used to make the deposition of the barrier layer / seed layer / conductive layer more flat or to fill the contact / interlayer holes. If the ultrasonic oscillation method is used after the deposition during annealing, this situation is called non-situ; because the wafer is annealed in the same tool, it is called in-situ. The second specific embodiment of the present invention-the method of using ultrasonic oscillation during substrate annealing 'has the following steps: forming an insulating layer 120 on the substrate 10. The contact holes expose a portion of the wafer to the outside or the underlying conductive layer is exposed to the outside. A barrier layer 124 made of Ta or TaN is deposited by chemical vapor deposition (CVD) or physical vapor deposition (PVD), and then a conductive layer Π4 is deposited on the barrier layer 124, and at least partially filled. Full contact hole 1 2 2. The next step is to heat the substrate 10 and oscillate the substrate at the same time with ultrasonic waves 12 to make the conductive layer flow and thus fill the contact holes. Printed by the Shellfish Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs-I — ^ ^^ 1 Ρ1 I-ϋ ^ — ^ i 11- 一 ^^^^ 1 n ^ t ^^^^ 1, one: L (Please read the precautions on the back before filling this page) Under N2 gas or Ar gas Or in the reaction chamber of forming gas (N2 + H: 2), heat the substrate to a temperature between 400 ° C and 550 ° C (tgt450 ° C) (range +/- 1 0 ° C), The oscillation frequency used to oscillate the substrate is between 1 K and 70 kHz. And the surface diffusion is used to planarize the conductive layer. The third Λ embodiment-ultrasonic plating-the third specific embodiment is a profit of 5 paper standard universal Chinese National Standard (CNS) A4 size (210 X 297 mm) A7 B7 Central Bureau of Standards, Ministry of Economic Affairs Printed by Pui Gong Consumer Co., Ltd. 5. Description of the invention () A method of electroplating a metal (such as Cu) on a substrate by ultrasonic vibration. An insulating layer 220 is formed on the substrate. Then, a contact hole 220 is formed to extend through the insulating layer 220. A physical vapor deposition (PVD) process is used to deposit a barrier layer 224 'composed of TaN / Ta on the insulating layer and fill the above-mentioned contact hole 220. A seed consisting of Cu is formed on the barrier layer 224. Next is a critical step, using ultrasonic vibration, to electroplat a conductive layer 234 containing at least copper on the seed 226 (for example: Cu) and the barrier layer 224. There are two ways to attach the wafer to the wafer loser 250. The wafer holder holds the wafer so that it faces up or down. The substrate 10 is fixed on a wafer clip; the exposed surface of the insulating layer 220 or the barrier layer 224 faces downward. Use ultrasonic waves to shake the substrate vertically or horizontally, or shake the plating solution. Utilizing this ultrasonic oscillation can make the plating of small contact holes have better step coverage. The present invention has many advantages over conventional techniques. The three specific embodiments of the present invention use ultrasonic vibration to deposit a barrier layer / conductive layer, anneal, or electroplating in small contact holes to provide better step coverage. 6 (Please read the notes on the back before filling in this page) '1T. Ϊ,. This paper size applies to Chinese National Standard (CNS) Yakisumi (210X 297 mm) 464979 A7 B7 Employees of the Central Procurement Bureau of the Ministry of Economic Affairs Printed by the Consumer Cooperatives 5. Description of the invention (The above contents are helpful to understand the advantages of the present invention. However, the understanding of the present month month # can be learned from the description and the surrounding of the present invention. The outline and advantages of the semiconductor device according to the present invention can be further understood by the following detailed description according to the present invention and the accompanying drawings. FIG. 1 shows a method according to the present invention, which provides ultrasonic energy to oscillate crystals during sedimentation. Circle, a schematic cross-sectional view of a wafer flat plate I. Figures 2 and 3 show schematic cross-sectional views of a method for depositing mineral layers using ultrasonic energy according to a first embodiment of the present invention. Figure 4 shows The traditional deposition technique 'simulates the carrier surface of the seed layer and the barrier layer without using the ultrasonic oscillation method. FIG. 5 shows a first embodiment according to the present invention, in CVD or PV During the D process, a schematic cross-sectional view of the seed layer and the barrier layer is simulated by using an ultrasonic energy oscillation method. Figures 6A and 6B show a second embodiment according to the present invention 'Using ultrasonic energy to anneal a conductive layer 134 Schematic diagram of the loading method of the method. 7 This paper size is applicable to China National Building Standard (CMS) 8-4 UlO.X297 mm} «-II 二 逦-I-I 1--ίι------ ^ 44i · J ^ n:. (Please read the precautions on the back before writing this page) Ministry of Economic Affairs, Central Standard, Employees' Cooperatives, printed A7 _____B7 V. Description of Invention () Figure 6C is a check of the optimal temperature Fig. 7A shows a schematic diagram of a carrier surface of an electroplating device that provides ultrasonic energy for electroplating metal on a wafer when the wafer is face down according to a third embodiment of the present invention. Fig. 7B shows According to a third embodiment of the present invention, a top view of a wafer clip and a wafer in a plating apparatus. FIG. 7C shows a third embodiment of the present invention. When the wafer faces upward, energy is provided for Schematic cross-section of a plating device for plating metal on a wafer Fig. S shows a schematic diagram of a wafer carrying surface using ultrasonic energy according to a third embodiment of the present invention. Fig. 9 shows an electric forging crystal using ultrasonic energy according to a third embodiment of the present invention. Schematic diagram of the cross section of the circle. Drawing number comparison description: 10 substrates, 11 flat plates, 1 2 ultrasonic energy, 8 paper sizes, using Chinese National Standards (CMS) A4 specifications (H0X 297 mm) (Please read the precautions on the back before filling (This page)-46497 A7 B7 Printed by the Central Standardization Bureau of the Ministry of Economic Affairs and the Consumers ’Cooperatives in China. V. Description of the invention () 1 3 Vacuum holes in the flat plate 2 0 Insulation layer 22 Hole 24 Barrier layer 3 0 Seed layer 34 Conductive layer 62 Seed layer or barrier layer formed by traditional technology 64 Seed layer or barrier layer formed by the present invention 1 1 2 Ultrasonic wave 120 Insulating layer 122 Contact hole 124 Barrier layer 1 34 Conductive layer 2 1 2 Ultrasonic energy 2 22 holes 224 barrier layer 226 seed layer 234 conductive layer 240 slot 242 plating solution 2 5 0 substrate clamp 250A ring 251 vibration device on the substrate clip 9 This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) ) (Please KS first (Please read the notes on the back and fill in the wooden pages) ------- ί. Lai Du printed by the Central Bureau of Standards of the Ministry of Economic Affairs 4 6 4 j 7 'j A7 B7 V. Description of the invention () I & quot Detailed description of the invention: The following details about the flow rate, pressure setting, thickness, etc. are helpful to understand the present invention. However, it is obvious that those skilled in the art can also operate without the following detailed description, that is, the scope of the present invention is not limited by the detailed process that has been widely understood. Regarding the flow velocity in the present invention, those skilled in the art can enlarge or reduce the size of the reactor in proportion to the size of the reactor. The first "Embodiment-During the Shenji Period", the first specific embodiment of the present invention is to provide ultrasonic energy to oscillate a substrate, which is used to deposit a first layer on a semiconductor structure (eg, a dielectric layer). (E.g. seed barrier / conductive layer). The first layer mentioned above can be formed by three different compositions / functions. Compared to conventional techniques, this first layer is not a _dielectric layer 'but (1) a barrier layer, (2) a seed layer, and / or (3) a conductive layer. The first layer is deposited and partially or completely filled. The holes in the full insulating layer u The ultrasonic method of the present invention can be used to form any one of the above three layers or various different combinations thereof. This ultrasonic method can make the deposition on the side walls of the opening more uniform 'and reduce the occurrence of overhangs and voids during the deposition process. The first specific embodiment is to use ultrasonic oscillation and CVD or PVD processes (such as the first to third) (Shown in the figure), a method for depositing a barrier layer and a first layer on a substrate. Referring to step 2), a semiconductor structure 10 is provided. The semiconductor structure 10 has a hole 22 extending through the insulating layer 20. The insulating layer can be an interlevel dielectric layer (ILD) (on the substrate), or an inter metal dielectric layer (IMD) (on the dielectric layer) Standard season (CMS) A4 specification (210X 297 mm) -----'----- f Policy -------- Order ------ J f Please read the notes on the back first Fill out the clothing page again} 46497 9 A7 B7 5. Description of the invention () and on the conductive layer (or on the substrate). The holes 22 expose the silicon surface of the substrate or the wires on the substrate insulation layer to the outside. The semiconductor 10 includes active and protective elements formed in a wafer and a wafer on-chain layer. "Semiconductor structure" is a device including components in a semiconductor wafer and a plating layer on the wafer. The substrate 10 is fixed on the plate 11 in a deposition reaction chamber. The above-mentioned deposition reaction chamber may be a chemical vapor deposition (CVD) ) Or one of the physical vapor deposition (PVD) reactors. As shown in Figure 1, the substrate 10 is fixed on the panel π by an electrostatic chuck or a vacuum device. The vacuum device is A vacuum clamp or a lost son, the panel η has a vacuum hole 1 3. Using the ultrasonic wave of the present invention and a chemical vapor deposition (CVD) or physical vapor deposition process, a first layer is deposited On the insulating layer 20, and at least partially fill the holes 22 on the substrate. The first layer mentioned above can be (a) the barrier layer consumer cooperation with the staff of the Central Standards Bureau of the Ministry of Economic Affairs. Please fill in this page again (barrier layer) 24 '(b) seedj layer 30 or (c) conductive layer 34 »The above PVD process can be: Thermal Evaporation > Sputtered molecular beam epitaxial deposition (M olecular Beam epitaxy), Laser sputtering deposition, shifted 11 This paper size applies Chinese National Standards (CNS) M see grid (210x29 * 7 mm) 464979 A7 B7 Printed by Consumer Cooperatives 5. Description of the invention () Ablation deposition, Ion Planting, or Cluster beam deposition. The above CVD process can be low pressure chemical vapor deposition (LPCVD) , Plasma Chemical Vapor Deposition (PECVD), Organometallic Chemical Vapor Deposition (MOCVD) and Atmospheric Chemical Vapor Deposition (APCVD), of which PECVD or MOCVD is the best. The key feature of the present invention is during deposition Or after deposition, the deposition is performed in the same reaction chamber, and the panel 11 is provided with ultrasonic energy 12 to oscillate the substrate 10. The substrate 10 may be horizontal, vertical, or both horizontal and vertical. The combined direction of oscillation. The vibration frequency of panel 11 is between IKHz and 70KHz (or greater than 70KHz); but it is best to be between 1 K and 70KHz. (A) The barrier layer is as described above. The first layer may be a barrier layer 24. The barrier layer 24 is composed of TiN / Ti'WN or Ta / TaN, and its optimal thickness is between 200 angstroms and 1000 angstroms. The PVD or CVD process is used to deposit the above. The barrier layer 24 has the following conditions: the temperature is between 25 ° C and 550 ° C, the pressure is between 4mtorr and 4torr, and the deposition time, power and gas are related to the design of the reaction chamber. (b) Seed layer 12 This paper size is in accordance with Chinese National Standard (CNS) A4 rules ^ (210X297 mm) (Please read the precautions on the back before filling this page) α '衣-flln f ^ nm Order— • d ...... I »m ^ i Printed by the Consumers' Cooperatives of the China Standards Bureau of the Ministry of Economic Affairs 6Λ Α7 ___ Β7 V. Description of the Invention () The first layer mentioned above can be the seed layer 30 (as shown in Figure 2) ) This seed layer 30 is composed of A1 or Cu. Its optimal thickness is between 50 Angstroms and 2000 Angstroms. PVD or CVD process is used to deposit the seed layer. The deposition conditions are as follows: the temperature is between 25 ° C and Between 55 ° C, the pressure is between 4mtorr and 4torr, and its deposition time, power and gas are related to the design of the reaction chamber. (c) Conductive layer The first layer mentioned above may be the conductive layer 34. This conductive layer is composed of Cu, Cu alloy or A1 alloy, and its optimal thickness is between ^ 100 and 20,000 angstroms, using PVD The CVD process is used to deposit the above-mentioned conductive layer composed of copper, and the deposition conditions are as follows: temperature is between 25 ° C. (: And 550 ° C, the force is between 4mtorr and 4torr, and its deposition time, power and gas are related to the design of the reaction chamber. The conductive layer composed of A1 may be the conductive layer 34 The conductive layer 34 is composed of A1, and its optimal thickness is between 1000 angstroms and 20,000 angstroms. The first conductive layer 34 composed of rhenium is deposited by a PVD or CVD process, and the seed layer is formed by ultrasonic waves. Deposition of barrier layer and conductive layer The first layer described above may be a multilayer structure composed of a barrier layer 24, a seed layer 30, and a conductive layer 34 (where the barrier layer 24 is made of Ti / TiN or Ta / TaN / WN Composition, the seed layer 30 is composed of A1 or Cu, and the conductive layer 34 is composed of A1 or Cu), and it is found that in the sedimentation process, the ultrasonic 13 S paper scale is applicable to the China National Standard (CNS) A4 (2! 0 × 297 public delay),】 Please read the notes on the back of the binding ff before writing this page} 4 649 Α7 Β7 V. Description of the invention () Energy 11 is used to oscillate the substrate. Table: Alpha vibration i substrate for ultrasonic energy , To guess the seed layer, barrier layer and conductive layer _ barrier layer seed layer guide Layer Ti / TiN A1 A1 Ta / TaN / WN Cu Cu Chess simulation results-results formed by the first Λ embodiment Figures 4A and 4B-Simulation of barrier layer Figure 4 is a traditional deposition (PVD) Technology, without using the ultrasonic method of the present invention, a schematic cross-sectional view of a seed layer and a barrier layer is simulated. FIG. 5 is a first specific embodiment of the present invention, which oscillates a substrate with ultrasonic energy during CVD and PVD processes In the case, the schematic diagram of the loading surface of the seed layer and the barrier layer is simulated. "As shown in Fig. 5, during the pvt) deposition, the seed layer and the barrier layer formed by the ultrasonic method of the present invention are more uniform, and at the same time, Improve the ability of step coverage. In Figs. 4 and 5, the 'plating layers 62 and 64 are regarded as seed layers or barrier layers. Printed by DuPont Consumer Cooperation of China Standards Bureau, Ministry of Economic Affairs I---- I n ^ u ^^ < 1 {Please read the precautions on the back before filling this page) This is indicated by the above simulation process, Figure 4 The plating layer 62 formed by the traditional technique in China is inferior to the plating layer formed by using the present invention in FIG. 5. The reason is that the thickness of the plating layer 62 formed on the horizontal surface is higher than the thickness on the side wall (as shown in Fig. 4) formed by the conventional technology; and the chain layer 64 formed by the ultrasonic method of the present invention is on the horizontal surface. The thickness and the 14 ^ paper size on the side wall are applicable to China ’s national standard (redundant) Congxie (2ΙΟΧ 297 ^ υ ~ ———— ^ ___ Printed by the Central Consumers ’Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 46A97 9 A7 __B7_ The thickness of () is about the same (as shown in Figure 5). According to the present invention, it is known that the deposition by using the ultrasonic method can make the deposition more uniform, because the ultrasonic vibration substrate can provide ultrasonic energy Used as an additional power to drive the surface to diffuse in bulk. The best process example of the first embodiment Λ itchy layer 24-the first layer mentioned above may be a barrier layer 24, which is made of TaN and TiN ( TaN / TiN), the optimal thickness is between .50 angstroms and 1,000 angstroms; the first layer is deposited using the PVD process, and the deposition conditions are as follows: the temperature is between 25C and 500C, and the force is between ltorr And 3torr, and its supersonic The wave oscillation frequency is between 1 KHz and 7 OKHz. Seed layer 30 (as shown in Figure 2) The seed layer 30 is composed of A1 or Cu, and its optimal thickness is between 50 angstroms and 3000 angstroms; using the pvD process The above-mentioned seed layer is deposited under the following conditions: the temperature is between 25t; and 30 (Γ {: 2), and the gas used for the deposition is gas (Ar), and the ultrasonic frequency is between IKHz and 70KHz. Conductive layer 34 The third option for the first layer mentioned above is the conductive layer 34. This conductive layer is made of Cu and its optimal thickness is between 15 and 20,000 Angstroms. This paper size is applicable to China National Standards (CNS) Α4ί ? / 丨 each (2ι〇χ297 ^ cent) (please read the precautions on the back before filling in this page)

A 4 6 4 9 T v A7 __B7 _ 5. Description of the invention () The above-mentioned conductive layer is deposited by PVD or CVD process, and the deposition conditions are as follows: the temperature is between 25 ° C and 300 ° C for Shen's accumulated gas is argon (Ar). The ultrasonic frequency is between 1 KHz and 70KΗζ. The second It embodiment-RTP / thermal oxidation furnace-in_situ or ex-situ A second embodiment of the present invention is a method using an ultrasonic wave during annealing or rapid thermal annealing (RTA). This ultrasonic method can make the deposition of barrier / seed / conductive layers in contact holes more flat. Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives --------- one binding {Please read the precautions on the back before filling this page) The second embodiment of the present invention is used during substrate annealing The ultrasonic method has the following steps: As shown in FIG. 6A, an insulating layer 120 is formed on the substrate 10. The contact hole exposes a part of the substrate 10 to the outside or the underlying conductive layer is exposed to the outside. A physical vapor deposition (PVD) method is used to deposit a barrier layer 124 composed of TiN or TaN »As shown in the first embodiment above, during the deposition of the barrier layer, the substrate is oscillated by ultrasonic waves in a vertical or horizontal direction. , And its optimal oscillation direction is two horizontal directions (X and Y directions). A conductive layer 134 is then deposited on the barrier layer 124 and at least partially fills the contact holes 1 2 2. When the conductive layer 1 3 4 is deposited, the substrate is further oscillated with ultrasound at the same time, as shown in the first embodiment. 16 This paper size is applicable to China National Standards (CNS) 4 See the standard (210 X 297 mm) 01 4 6 4 Staff cooperation of the Central Standards Bureau of the Ministry of Economic Affairs. Du printed A7 B7 Description of invention () As shown in Figure 6B As shown, this step is a key step, heating the substrate 10 and oscillating the substrate 10 with an ultrasonic wave Π2, so that the conductive layer flows and thus fills the contact holes. In N2 or Ar gas, heat the substrate to a temperature between 400 = c and 800 ° C; the oscillation frequency of this substrate is between i K and 70 KHz. Figure 6C shows an analysis of an optimum temperature. During the temperature τ 1, the temperature is increased from room temperature to a temperature between 4 8 (TC and 5 80 ° C.), And the heating time is between 25 seconds and 35 seconds. During the temperature T2, The temperature is kept constant, and the heating time is between 8 and 12 minutes. During the temperature T2, the deposition is performed by the ultrasonic method. The best embodiment of the second embodiment of the present invention is circle 6A and 6B. -The best special example of annealing the second specific embodiment of the present invention during the ultrasonic oscillation. As shown in FIG. 6A, an insulating layer 12 is formed on the substrate 10. The contact hole exposes a part of the substrate to the outside or The lower conductive layer is exposed to the outside. A barrier layer 124 composed of TiN and TaN is deposited by physical vapor deposition (PVD), and the thickness is between about 200 angstroms and 1,000 angstroms. Deposition the conductive layer and partially fill the contact holes 1 22. It further includes depositing the conductive layer 134 on the barrier layer 124 and oscillating with ultrasonic waves at the same time. This paper size is in accordance with China National Standard (CNS) A4. (210X297 mm) ^ 1.---I--I fy---—i ί--i ί ^ ϋρ-I.:,-(Please read the notes on the back before filling in this f) 464979 A7 B7 V. Description of the invention () Substrate. This conductive layer is made of Cu and is formed by PVD sputtering process. This The thickness of the copper layer of the conductive layer is between about 1000 angstroms and 3000 angstroms. As shown in FIG. 6B, this step is a critical step. The substrate 10 is heated and the substrate 10 is oscillated with an ultrasonic wave 1 12 to make it conductive. The layer flows and thus fills the contact holes. During the annealing process, the temperature provided is between 450 ° C and 550 ° C, the heating time is between 10 and 30 minutes, and the vibration frequency of the substrate is between Between 1K and 70KHz. In N2 or Ar gas or forming gas (N2 and H2), heat the substrate to a temperature-degree between 25 ° C and 400 ° C; and the vibration frequency of this substrate is between IK and 70KHz The process of this preferred second specific embodiment is summarized as follows: (Please read the notes on the back before filling out this page)-Install ----Order-Zhengong Consumer Cooperative, China Standards Bureau, Ministry of Economic Affairs Optimal parameters for printing steps 1-圊 6 A Deposition of barrier layer consisting of T a and T aN 2 Deposit a conductive layer and at least partially fill the hole 122 " Selection-combining deposition and ultrasonic oscillation-(combining the first and second specific embodiments of the present invention) 18 ir__ -17 This paper standard applies to the Chinese national standard Car (CNS_) A4 specification (210X 297 mm) 464979 A7 B7 Central Government Standards Bureau of the Ministry of Economic Affairs®: printed by industrial and consumer cooperation 5. Inventory (3-Figure 6B annealing and use of supersonic ~~~~ * ^- 1 time-between 10 minutes of wave energy oscillating to reflow and 30 minutes of conductive layer temperature = 450 and oscillating rate and parameters ^ lk to 70kHz direction of ultrasonic oscillating wave f vertical window and / or medium, ---- Second Embodiment-Ultrasonic Electric Money A third embodiment of the present invention is a method for electroplating Qu on a substrate by using an ultrasonic wave. Referring to FIG. 9, an insulating layer 220 is formed on the semiconductor structure 10. Then, a contact hole 220 is formed to extend through the insulating layer 220. A physical vapor deposition (PVD) process is used to deposit a barrier layer 224 of TaN / Ta on the insulating layer, and fill the contact hole 22o. A seed layer 226 is formed on the barrier layer 224, and the seed layer is composed of cu. In a key step, a conductive layer 234 containing at least steel is plated on the seed layer 22 6 and the substrate is oscillated with ultrasonic waves. In a critical electroplating step, there are two options for fixing the substrate to the substrate clip 2 50. The lost son can fix the substrate so that it faces up or down (preferably). The substrate 10 is fixed on the substrate clip 250. Make the insulating layer 220 19 this paper standard use the Chinese National Standard (CNS) standard of 8 4 squares (210X 2S > 7 mm) ^ ϋ- ί ^ —-1 ·. 2, I 1 I! 1-^ — n a * un i ^ i ^ i I f-m ^ i,! a. a s mouth a Λ f Please read the notes on the back before filling in too. Page} 4649 V. Description of the invention (A7 B7 Central Ministry of Economic Affairs The exposed side of the printed PCB or the barrier layer 224 of the quasi-brainer's consumer cooperative is facing down. FIG. 7A is a schematic diagram of a carrying surface of a plating device (slot 240). According to the third embodiment of the present invention, the substrate 10 Face down, use the device to provide-ultrasonic energy to record the metal on the substrate 10. Use the electroplating solution 242 to plate the metal on the substrate. Fix the substrate with a clip 250 and provide an oscillating device 251-ultrasonic energy 212 'is used to oscillate the substrate; in other words, the electric chain solution is also shaken at the same time. Section 7B 圊 is a schematic plan view of the substrate clip and the substrate 10 in the electroplating apparatus according to the third embodiment of the present invention, showing the substrate clip. Sheung Wan 250A »FIG. 7C Carrying surface of a plating apparatus according to a third embodiment of the present invention Intent 'This electroplating device uses ultrasonic waves to plate metal onto the substrate when the substrate is facing up-Figure 8 shows the substrate 210 facing down to the plating tank 240. The metal is plated on the holes 222, the insulating layer 220 and Located in the lower conductive layer 2 1 2 (for example, the surface of a metal wire or a silicon substrate). Use an oscillating device (as shown in 7A, 7B, and 7C), or use a solution 242 in an ultrasonic vibration tank to The sonic method oscillates the substrate. The semiconductor structure (substrate) is oscillated in the vertical or horizontal direction by ultrasonic waves. This ultrasonic method allows metal plating in small contact holes to have better step coverage. This ultrasonic method also Makes the electric bond dissolve 20 paper scales using the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back of K1 before filling out this page) '-— I I----)

464979 A7 ____B7 ___ 5. Description of the invention () Liquid is more likely to diffuse into / out of the tight holes in the seed layer. The electroplating process can be an electrochemical deposition (ECD), electroless plating (e 丨 ectroless planting) or electroplating (electroplanting) process. That is, the plating tank has an ultrasonic source for oscillating the plating solution. Example of the Third Preferred Process of the tt Embodiment Referring to FIG. 9, an insulating layer 220 is formed on the substrate 10. Contact holes are then formed which extend through the insulating layer 2 2 0. A sputtering process is used to deposit a barrier layer 224 made of TaN / Ta on the insulating layer and fill the contact hole 220. Next, a seed layer 226 is formed on the barrier layer 224. This seed layer 226 is composed of Cu. In a key step, the electrode layer 226 is electroplated—a conductive layer 234 including at least copper, and the substrate is oscillated with ultrasound. . (Please read the precautions on the back before filling out this page) The best process of the third embodiment is summarized in the following table. The best third product printed by the Ministry of Economic Affairs, the Bureau of Standardization and Consumer Cooperatives is implemented. The process is summarized. -Using the power amplifier

^ Good parameters

'--ί I 11 ^-: 1 —I----i I —II-----— II ..... I —I— _-I Deposit a barrier made of Ta or TaN Layer 224 21 This paper size is applicable to China National Standard (CNS) VIII (2! 〇χ297 公 广) 46497 9 Α7 Β7 V. Description of the invention (2 Deposit a race layer 226 Cu seed layer on the barrier layer 3 -圊 9 Shock the substrate or use ultrasonic plating to partially fill the hole 222, electroplating a conductive filling layer composed of Cu 234 HHI 1 f (read the precautions on the back before filling this page) The printing of the quasi-station employee consumer cooperative is particularly noteworthy in that the common technology published in the integrated circuit manufacturing process can be used in the process of the present invention. Furthermore, individual steps in the manufacturing process can also be performed using machines in commercial integrated circuit manufacturing processes. It is particularly important that after understanding the present invention, the data in the technical example can be further applied after being appropriately processed by those skilled in the art. 3 The present invention is described above with a preferred embodiment, and is only used to help understand the present invention. The implementation of the invention 'is not intended to limit the spirit of the present invention, but a person skilled in the art' will realize the spirit of the present invention, and without departing from the spirit of the present invention, it may be equivalent to make a few changes and retouching. The scope of patent protection shall be determined by the scope of equivalent patent application which is attached. 22 This paper size applies to Chinese Standards for Households (CNS) A4 this grid (210X297 mm) Order

Claims (1)

Repair 464979 C8 D8 rfM is being requested to be printed by t rt Central Samples Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives. 2. The method described in item 1 of the scope of patent application, where the first layer above ~ ^ _0 outside is the barrier layer 'The barrier layer is composed of Ta / TaN, and the thickness of the barrier layer is between 500 angstroms and 1000 angstroms' using physical vapor deposition pvD) ^ The first layer is deposited by a sputtering forging process.> The temperature during deposition is between 25 a ° C and 550 ° c, the deposition pressure is between 4mtOrr and 4torr, and the frequency of its ultrasonic disc is between 1 kHz and 70uIz. The scope of the patent claims Jing Jing Fan Yuan j. A method for depositing a first layer using ultrasonic vibration on a contact hole in an insulating layer, the method includes at least: a) providing a semiconductor structure 'the semiconductor structure has an extension through A hole in the insulating layer; b) fixing the semiconductor structure on a plate of a deposition reaction chamber; c. Providing an ultrasonic energy of the plate to vibrate the semiconductor structure; d) using a CVD or PVD process on the insulating layer A first layer is deposited, at least partially filling the holes in the semiconductor structure. 3. The method according to item 1 of the scope of the patent application, wherein the first layer is composed of a seed layer * the seed layer mountain Cu, and the thickness of the seed layer is between 500 angstroms and 1,000 angstroms; Physical vapor deposition (VI)) sputtering is used to deposit the first layer, and the deposition conditions are as follows: the temperature is between 25 ° C and 550 ° C, the pressure is between 4mtorr and 4ton. The ultrasonic oscillation frequency is between 1 kHz and 70 kliz. 23 This paper's scale is applicable to the Chinese country's gradient (CNS > AAAi grid (2l0x297mm) ί-一 —.1} 1 —; I dream I line (please read the precautions on the back before filling this page) ) C8 printed by Shelley Consumer Cooperative of Central Ministry of Economic Affairs of the Ministry of Economic Affairs. 6. Application for patent scope 4. The method described in item 1 of the scope of patent application, wherein the first layer is a conductive layer, and the conductive layer consists of Cu, Αί or A 丨 alloy, and the thickness of the conductive layer is between 2000 angstroms and 70 angstroms. 5, the method described in the first item of the scope of the patent application • its _ above The first layer is a conductive layer composed of Cu. The thickness of the conductive layer is between 2000 angstroms and 7000 angstroms. The conductive layer composed of Cu is deposited using a physical vapor deposition (PVD) sputtering process. Layer, the conditions for its deposition are as follows: the temperature is between 25 ° C and 55 (J ° C, the pressure is between 4mtorr and 4torr, and the ultrasonic vibration frequency is between 1kHz and 70kilz. '6, such The method described in item 丨 of the patent application range, wherein the first layer is a conductive layer, and the conductive layer is A The thickness of the conductive layer is between 1,000 angstroms and 1,000 angstroms. The first layer composed of CU is deposited using a physical vapor deposition (PVD) process. The conditions for the deposition are as follows: Between 25 ° c and 5 50 ×: the pressure is between 4mtorr and 4torr, and the ultrasonic oscillation frequency is between 1kHz and ': 70kHZ. 7. The method according to item 1 of the scope of patent application, wherein The first layer is a multilayer structure. The multilayer structure is composed of at least a barrier layer, a sublayer, and a conductive layer. The barrier layer is composed of Ti / TiN. The seed layer is composed of A 丨. The conductive layer is composed of A1; the ultrasonic energy is used to shock into the substrate 1 to deposit the barrier layer, the seed layer, and the conductive layer. The paper size is applicable to China National Standards (CNS) Ad. (2 丨 0 X 297 mm) -------: ---- f ------ IT ------. ^ (Please read the precautions for -M and read 5 before filling this page) ) 9 7 9 4 6 1- ABCD Printed by the Central Government Bureau of the Ministry of Economic Affairs, Consumer Cooperatives, Consumer Electronics Cooperatives 6. Apply the patent scope electric layer. The PVD process mentioned above is one of the following processes: thermal evaporation, sputter bonding, molecular beam epitaxy, ejection bond deposition, transfer deposition (ab 丨 a I i ο nde ρ 〇 siti ο η) > ionic electric bond , Cluster beam deposition. 9. The method described in item 1 of the scope of patent application *, wherein the above CVD process may be low pressure chemical vapor deposition (LPCVD), plasma chemical vapor deposition (PECVD), organic metal chemical vapor deposition (MOCVD) ), And atmospheric pressure chemical vapor deposition (APCVD). 10. The method according to item 丨 of the scope of patent application, wherein the above-mentioned substrate is fixed on the plate by an electrostatic clip or a physical device. 1 1. The method according to item 1 of the scope of patent application, wherein the above-mentioned substrate oscillates in one direction of 1P in vertical or horizontal or a combination of vertical and horizontal, and the plate has a vibration rate greater than 70 kl [2]. 1 2. A method of annealing a substrate using ultrasonic vibration, the method at least includes: a) forming an insulating layer on the substrate; b) forming a contact hole extending through the insulating layer; c) by CVD or Physical Vapor Deposition (PVD) / Yu Yi 1 111 25 Paper Wave Scale National Tihua (CNS) Λ4 Appearance (2 丨 0X297 mm)-^ ---: ---- -^ ------ ir ------ ^ (please note the item on the back of i31 * before filling out this page) 464979 A8 B8 C8 D8 VI. The scope of patent application or T a / T ia Barrier layer; d) depositing a conductive layer on the barrier layer and filling at least the contact hole; e) heating the substrate and vibrating the substrate with ultrasonic waves to make the conductive layer flow, so It's time to contact Lidong. 13. The method according to item 12 of the scope of patent application, wherein the above-mentioned insulating layer is an inner-layer dielectric layer or an inner metal dielectric layer, and the above-mentioned contact hole exposes a part of the wafer to the outside or It is the contact hole that exposes the underlying conductive layer to the outer u 1 4. The method as described in item 12 of the scope of the patent application, wherein the step (c) above further includes the substrate after ultrasonic vibration. 15. The method as described in item 12 of the scope of patent application, step (c) further includes oscillating the substrate in a vertical or horizontal direction with an ultrasonic wave. 1 16. As described in item 12 of the scope of patent application Method The deposition of the conductive layer further includes depositing the conductive layer and simultaneously oscillating the substrate with ultrasonic waves' 1 --------- t ------ IT ------ ^ (Please Read it first! Please fill out this note before filling in this note.) The Consumer Cooperatives Cooperative Policy of the Central Bureau of Economic Affairs, Ministry of Economic Affairs of the People's Republic of China. 1 7. Heat the substrate in nitrogen and argon as described in item 12 of the scope of patent application. To a temperature between 4 5 0 ° C and 5 0 ° C 'and the oscillation frequency of the substrate is between 1 K and 7 0 Κ Η z. 26 The good standard of this paper is applicable to the National Standards of China (CNS) AWJL (210 × 297 mm). Printed by the China Labor Standards Bureau of the Ministry of Economic Affairs of the Bayer Consumer Cooperatives. 4 6 4b Be C8 __ D8 6. Scope of patent application 1 8. — A method for electroplating a Cu layer on a substrate by using ultrasonic vibration, the method at least comprises: a) forming an insulating layer on a substrate; b) forming a contact hole extending through the insulating layer; c) using physical vapor deposition ( PVD) deposits a barrier layer composed of TaN / Ta on the insulating layer and fills the contact hole; d) deposits a seed layer composed of copper on the barrier layer; e) electric ship (Electroplating)-a copper layer on the barrier layer > and oscillating the substrate with ultrasonic waves. 19. The method according to item 18 of the scope of patent application, wherein the above method further includes attaching the substrate to the wafer clip with the exposed side of the insulating layer facing downward; and in a vertical or horizontal direction The substrate is oscillated with ultrasonic waves. 20. The method as described in item 18 of the scope of patent application, wherein the method further includes attaching the substrate to the wafer 'clip with the exposed side of the insulating layer facing up; and The substrate is oscillated with ultrasonic waves in the horizontal direction. 2 1. The method as described in item 18 of the scope of patent application, wherein the thickness of the above barrier layer is between about 200 angstroms and 1,000 angstroms. 27 The thick scale of this paper is applicable to China Gujia Pole ( CNS) Λ4 specification (2! 〇x 297 mm) --r -------------- tr ------ # (please fill in the precautions of «Reading νέ first> (This page) 4 6 4 9 7 ^-^ m, eg D8 6. Application scope 22. A method of electroplating a Cu layer on a substrate by using ultrasonic vibration, the method at least includes: a) forming an insulating layer on a substrate Above: b) forming a contact hole extending through the insulating layer; c) using physical vapor deposition (PVD) to form a barrier layer composed of TaN / Ta on the insulating layer and filling the contact hole; in the physical gas The substrate is shaken during the phase deposition. d) A PVD process is used to deposit a seed layer made of Cu on the barrier layer: shaking the substrate during the physical vapor deposition period of the seed layer; e) using ultrasonic waves to vibrate the substrate at the barrier A copper layer is electrically bonded on the layer. ----------- Envy ------ Order ------ line- (Please read it first. Please fill in this page for the precautions) Central Ministry of Economic Affairs Printed by the Industrial and Consumer Cooperatives 8 2 This paper size is applicable to China's National Insertion (CNS) ΛΌSeeGrid (2I0X 297 revolutions)